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Member "wscite/vhdl.properties" (11 Sep 2020, 4187 Bytes) of package /windows/misc/wscite445.zip:


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    1 # Define SciTE settings for vhdl files.
    2 
    3 # VHDL files
    4 file.patterns.vhdl=*.vhd;*.vhdl
    5 filter.vhdl=VHDL (vhd vhdl)|$(file.patterns.vhdl)|
    6 
    7 *filter.vhdl=$(filter.vhdl)
    8 
    9 lexer.$(file.patterns.vhdl)=vhdl
   10 
   11 *language.vhdl=VHDL|vhd||
   12 
   13 word.chars.vhdl=$(chars.alpha)$(chars.numeric)_
   14 word.characters.$(file.patterns.vhdl)=$(word.chars.vhdl)
   15 
   16 #calltip.vhdl.word.characters=$(chars.alpha)$(chars.numeric)_
   17 
   18 comment.block.vhdl=--
   19 #comment.block.at.line.start.vhdl=1
   20 #comment.stream.start.vhdl=/*
   21 #comment.stream.end.vhdl=*/
   22 #comment.box.start.vhdl=/*
   23 #comment.box.middle.vhdl= *
   24 #comment.box.end.vhdl= */
   25 
   26 #~ fold.at.Begin=1
   27 #~ fold.at.Parenthese=1
   28 
   29 #statement.lookback.$(file.patterns.vhdl)=20
   30 #block.start.$(file.patterns.vhdl)=5 begin
   31 #block.end.$(file.patterns.vhdl)=5 end
   32 #statement.indent.$(file.patterns.vhdl)=5 always case casex casez else for if while \
   33 #module function task
   34 
   35 indent.maintain.$(file.patterns.vhdl)=1;
   36 
   37 
   38 keywords.$(file.patterns.vhdl)=access after alias all architecture array assert attribute begin block \
   39 body buffer bus case component configuration constant disconnect downto else elsif end entity exit file \
   40 for function generate generic group guarded if impure in inertial inout is label library linkage literal \
   41 loop map new next null of on open others out package port postponed procedure process pure range record \
   42 register reject report return select severity shared signal subtype then to transport type unaffected \
   43 units until use variable wait when while with
   44 
   45 keywords2.$(file.patterns.vhdl)=                                                                            \
   46  abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
   47 
   48 keywords3.$(file.patterns.vhdl)=                                                                            \
   49  left right low high ascending image value pos val succ pred leftof rightof base range reverse_range        \
   50  length delayed stable quiet transaction event active last_event last_active last_value driving             \
   51  driving_value simple_name path_name instance_name
   52 
   53 keywords4.$(file.patterns.vhdl)=                                                                            \
   54  now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector      \
   55  to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left \
   56  rotate_right resize to_integer to_unsigned to_signed std_match to_01
   57 
   58 keywords5.$(file.patterns.vhdl)=                                                                            \
   59  std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed               \
   60  std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives        \
   61  vital_timing
   62 
   63 keywords6.$(file.patterns.vhdl)=                                                                            \
   64  boolean bit character severity_level integer real time delay_length natural positive string bit_vector     \
   65  file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic                \
   66  std_logic_vector X01 X01Z UX01 UX01Z unsigned signed
   67 
   68 # vhdl styles
   69 
   70 # Default
   71 style.vhdl.32=$(font.base)
   72 # White space
   73 style.vhdl.0=fore:#800080
   74 # Comment
   75 style.vhdl.1=$(colour.code.comment.line),$(font.code.comment.line)
   76 # Bang comment
   77 style.vhdl.2=fore:#3F7F3F,$(font.code.comment.line)
   78 # Number
   79 style.vhdl.3=$(colour.number)
   80 # Double quoted string
   81 style.vhdl.4=$(colour.string)
   82 # Operators
   83 style.vhdl.5=
   84 #style.vhdl.5=$(colour.operator)
   85 # Identifiers
   86 style.vhdl.6=
   87 # End of line where string is not closed
   88 style.vhdl.7=fore:#000000,$(font.string.literal),back:#E0C0E0,eolfilled
   89 # Keyword
   90 style.vhdl.8=$(colour.keyword)
   91 # Std operator
   92 style.vhdl.9=fore:#007F7F
   93 # Attribute
   94 style.vhdl.10=fore:#804020
   95 # Std Function
   96 style.vhdl.11=fore:#808020
   97 # Std Package
   98 style.vhdl.12=fore:#208020
   99 # Std Type
  100 style.vhdl.13=fore:#208080
  101 # User defined identifiers and tasks
  102 style.vhdl.14=fore:#804020,$(font.code.comment.doc)
  103 # Block comment
  104 style.vhdl.15=$(colour.code.comment.box),$(font.code.comment.box)
  105 # Braces are only matched in operator style
  106 braces.vhdl.style=5