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Member "wscite/verilog.properties" (11 Sep 2020, 12491 Bytes) of package /windows/misc/wscite445.zip:


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    1 # Define SciTE settings for Verilog files.
    2 
    3 # Verilog files
    4 file.patterns.verilog=*.v;*.vh
    5 filter.verilog=Verilog (verilog)|$(file.patterns.verilog)|
    6 
    7 *filter.verilog=$(filter.verilog)
    8 
    9 lexer.$(file.patterns.verilog)=verilog
   10 
   11 *language.verilog=Verilog|v||
   12 
   13 word.chars.verilog=$(chars.alpha)$(chars.numeric)_`$#
   14 word.characters.$(file.patterns.verilog)=$(word.chars.verilog)
   15 
   16 calltip.verilog.word.characters=$(chars.alpha)$(chars.numeric)_$
   17 
   18 comment.block.verilog=//~
   19 #comment.block.at.line.start.verilog=1
   20 comment.stream.start.verilog=/*
   21 comment.stream.end.verilog=*/
   22 comment.box.start.verilog=/*
   23 comment.box.middle.verilog= *
   24 comment.box.end.verilog= */
   25 
   26 fold.verilog.flags=0
   27 
   28 statement.lookback.$(file.patterns.verilog)=20
   29 statement.end.$(file.patterns.verilog)=10 ;
   30 block.start.$(file.patterns.verilog)=5 begin case casex casez
   31 block.end.$(file.patterns.verilog)=5 begin end endcase
   32 statement.indent.$(file.patterns.verilog)=5 always else for if while
   33 
   34 indent.maintain.$(file.patterns.verilog)=0
   35 
   36 preprocessor.symbol.$(file.patterns.verilog)=`
   37 preprocessor.start.$(file.patterns.verilog)=ifdef ifndef
   38 preprocessor.middle.$(file.patterns.verilog)=else
   39 preprocessor.end.$(file.patterns.verilog)=endif
   40 
   41 keywordclass.verilog= \
   42 always and assign automatic \
   43 begin buf bufif0 bufif1 \
   44 case casex casez cell cmos config \
   45 deassign default defparam design disable \
   46 edge else end endcase endconfig endfunction endgenerate endmodule endprimitive endspecify endtable endtask event \
   47 for force forever fork function \
   48 generate genvar \
   49 highz0 highz1 \
   50 if ifnone incdir include initial inout input instance integer \
   51 join \
   52 large liblist library localparam \
   53 macromodule medium module \
   54 nand negedge nmos nor noshowcancelled not notif0 notif1 \
   55 or output \
   56 parameter pmos posedge primitive pull0 pull1 pulldown pullup pulsestyle_ondetect pulsestyle_onevent \
   57 rcmos real realtime reg release repeat rnmos rpmos rtran rtranif0 rtranif1 \
   58 scalared showcancelled signed small specify specparam strong0 strong1 supply0 supply1 \
   59 table task time tran tranif0 tranif1 tri tri0 tri1 triand trior trireg \
   60 unsigned use uwire \
   61 vectored \
   62 wait wand weak0 weak1 while wire wor \
   63 xnor xor
   64 
   65 keywords.$(file.patterns.verilog)=$(keywordclass.verilog)
   66 
   67 # Secondary keywords and identifiers
   68 keywords2.$(file.patterns.verilog)=
   69 keywords3.$(file.patterns.verilog)= \
   70 $async$and$array $async$and$plane $async$nand$array $async$nand$plane $async$nor$array $async$nor$plane $async$or$array $async$or$plane \
   71 $bitstoreal \
   72 $countdrivers \
   73 $display $displayb $displayh $displayo \
   74 $dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson $dist_t $dist_uniform \
   75 $dumpall $dumpfile $dumpflush $dumplimit $dumpoff $dumpon $dumpportsall $dumpportsflush $dumpportslimit $dumpportsoff $dumpportson $dumpvars \
   76 $fclose $fdisplayh $fdisplay $fdisplayf $fdisplayb $feof $ferror $fflush $fgetc $fgets $finish $fmonitorb $fmonitor $fmonitorf $fmonitorh $fopen $fread $fscanf $fseek $fsscanf $fstrobe $fstrobebb $fstrobef $fstrobeh $ftel $fullskew $fwriteb $fwritef $fwriteh $fwrite \
   77 $getpattern \
   78 $history $hold \
   79 $incsave $input $itor \
   80 $key \
   81 $list $log \
   82 $monitorb $monitorh $monitoroff $monitoron $monitor $monitoro \
   83 $nochange $nokey $nolog \
   84 $period $printtimescale \
   85 $q_add $q_exam $q_full $q_initialize $q_remove \
   86 $random $readmemb $readmemh $readmemh $realtime $realtobits $recovery $recrem $removal $reset_count $reset $reset_value $restart $rewind $rtoi \
   87 $save $scale $scope $sdf_annotate $setup $setuphold $sformat $showscopes $showvariables $showvars $signed $skew $sreadmemb $sreadmemh $stime $stop $strobeb $strobe $strobeh $strobeo $swriteb $swriteh $swriteo $swrite $sync$and$array $sync$and$plane $sync$nand$array $sync$nand$plane $sync$nor$array $sync$nor$plane $sync$or$array $sync$or$plane \
   88 $test$plusargs $time $timeformat $timeskew \
   89 $ungetc $unsigned \
   90 $value$plusargs \
   91 $width $writeb $writeh $write $writeo
   92 # User defined tasks and identifiers
   93 keywords4.$(file.patterns.verilog)=
   94 # comment keyword
   95 keywords5.$(file.patterns.verilog)= synopsys parallel_case infer_mux TODO
   96 
   97 
   98 # Define SciTE settings for SystemVerilog files.
   99 
  100 # systemverilog files
  101 file.patterns.systemverilog=*.sv;*.svh
  102 filter.systemverilog=systemverilog (systemverilog)|$(file.patterns.systemverilog)|
  103 lexer.$(file.patterns.systemverilog)=verilog
  104 
  105 word.chars.systemverilog=$(chars.alpha)$(chars.numeric)_`$#
  106 word.characters.$(file.patterns.systemverilog)=$(word.chars.systemverilog)
  107 
  108 statement.lookback.$(file.patterns.systemverilog)=20
  109 statement.end.$(file.patterns.systemverilog)=10 ;
  110 block.start.$(file.patterns.systemverilog)=5 begin case casex casez
  111 block.end.$(file.patterns.systemverilog)=5 begin end endcase
  112 statement.indent.$(file.patterns.systemverilog)=5 always else for if while
  113 
  114 indent.maintain.$(file.patterns.systemverilog)= 0
  115 
  116 preprocessor.symbol.$(file.patterns.systemverilog)=`
  117 preprocessor.start.$(file.patterns.systemverilog)=ifdef ifndef
  118 preprocessor.middle.$(file.patterns.systemverilog)=else
  119 preprocessor.end.$(file.patterns.systemverilog)=endif
  120 
  121 # Taken from the SystemVerilog IEEE Std 1800-2005 Annex B
  122 keywords.$(file.patterns.systemverilog)=\
  123 alias always always_comb always_ff always_latch and assert assign assume \
  124 automatic before begin bind bins binsof bit break buf bufif0 bufif1 byte case \
  125 casex casez cell chandle class clocking cmos config const constraint context \
  126 continue cover covergroup coverpoint cross deassign default defparam design \
  127 disable dist do edge else end endcase endclass endclocking endconfig \
  128 endfunction endgenerate endgroup endinterface endmodule endpackage \
  129 endprimitive endprogram endproperty endspecify endsequence endtable endtask \
  130 enum event expect export extends extern final first_match for force foreach \
  131 forever fork forkjoin function generate genvar highz0 highz1 if iff ifnone \
  132 ignore_bins illegal_bins import incdir include initial inout input inside \
  133 instance int integer interface intersect join join_any join_none large liblist \
  134 library local localparam logic longint macromodule matches medium modport \
  135 module nand negedge new nmos nor noshowcancelled not notif0 notif1 null or \
  136 output package packed parameter pmos posedge primitive priority program \
  137 property protected pull0 pull1 pulldown pullup pulsestyle_onevent \
  138 pulsestyle_ondetect pure rand randc randcase randsequence rcmos real realtime \
  139 ref reg release repeat return rnmos rpmos rtran rtranif0 rtranif1 scalared \
  140 sequence shortint shortreal showcancelled signed small solve specify specparam \
  141 static string strong0 strong1 struct super supply0 supply1 table tagged task \
  142 this throughout time timeprecision timeunit tran tranif0 tranif1 tri tri0 tri1 \
  143 triand trior trireg type typedef union unique unsigned use uwire var vectored \
  144 virtual void wait wait_order wand weak0 weak1 while wildcard wire with within \
  145 wor xnor xor
  146 
  147 # Secondary keywords and identifiers
  148 keywords2.$(file.patterns.systemverilog)=
  149 
  150 # System Tasks
  151 keywords3.$(file.patterns.systemverilog)=\
  152 $acos $acosh $asin $asinh $assertfailoff $assertfailon $assertkill \
  153 $assertnonvacuouson $assertoff $asserton $assertpassoff $assertpasson \
  154 $assertvacuousoff $async$and$array $async$and$plane $async$nand$array \
  155 $async$nand$plane $async$nor$array $async$nor$plane $async$or$array \
  156 $async$or$plane $atan $atan2 $atanh $bits $bitstoreal $bitstoshortreal $cast \
  157 $ceil $changed $changed_gclk $changing_gclk $clog2 $cos $cosh $countdrivers \
  158 $countones $coverage_control $coverage_get $coverage_get_max $coverage_merge \
  159 $coverage_save $dimensions $display $displayb $displayh $displayo \
  160 $dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson \
  161 $dist_t $dist_uniform $dumpall $dumpfile $dumpflush $dumplimit $dumpoff \
  162 $dumpon $dumpports $dumpportsall $dumpportsflush $dumpportslimit $dumpportsoff \
  163 $dumpportson $dumpvars $error $exit $exp $falling_gclk $fatal $fclose \
  164 $fdisplay $fdisplayb $fdisplayf $fdisplayh $fdisplayo $fell $fell_gclk $feof \
  165 $ferror $fflush $fgetc $fgets $finish $floor $fmonitor $fmonitorb $fmonitorf \
  166 $fmonitorh $fmonitoro $fopen $fread $fscanf $fseek $fsscanf $fstrobe $fstrobeb \
  167 $fstrobebb $fstrobef $fstrobeh $fstrobeo $ftel $ftell $fullskew $future_gclk \
  168 $fwrite $fwriteb $fwritef $fwriteh $fwriteo $get_coverage $getpattern $high \
  169 $history $hold $hypot $increment $incsave $info $input $isunbounded $isunknown \
  170 $itor $key $left $list $ln $load_coverage_db $log $log10 $low $monitor \
  171 $monitorb $monitorh $monitoro $monitoroff $monitoron $nochange $nokey $nolog \
  172 $onehot $onehot0 $past $past_gclk $period $pow $printtimescale $q_add $q_exam \
  173 $q_full $q_initialize $q_remove $random $readmemb $readmemh $realtime \
  174 $realtobits $recovery $recrem $removal $reset $reset_count $reset_value \
  175 $restart $rewind $right $rising_gclk $root $rose $rose_gclk $rtoi $sampled \
  176 $save $scale $scope $sdf_annotate $set_coverage_db_name $setup $setuphold \
  177 $sformat $sformatf $shortrealtobits $showscopes $showvariables $showvars \
  178 $signed $sin $sinh $size $skew $sqrt $sreadmemb $sreadmemh $sscanf $stable \
  179 $stable_gclk $steady_gclk $stime $stop $strobe $strobeb $strobeh $strobeo \
  180 $swrite $swriteb $swriteh $swriteo $sync$and$array $sync$and$plane \
  181 $sync$nand$array $sync$nand$plane $sync$nor$array $sync$nor$plane \
  182 $sync$or$array $sync$or$plane $system $tan $tanh $test$plusargs $time \
  183 $timeformat $timeskew $typename $ungetc $unit $unpacked_dimensions $unsigned \
  184 $urandom $urandom_range $value$plusargs $warning $width $write $writeb $writeh \
  185 $writememb $writememh $writeo
  186 
  187 # User defined tasks and identifiers
  188 keywords4.$(file.patterns.systemverilog)=
  189 # comment keyword
  190 keywords5.$(file.patterns.systemverilog)= synopsys parallel_case infer_mux TODO
  191 
  192 
  193 # Verilog styles
  194 
  195 # Default
  196 style.verilog.32=$(font.base)
  197 # White space
  198 style.verilog.0=fore:#808080
  199 # Comment
  200 style.verilog.1=$(colour.code.comment.box),$(font.code.comment.box)
  201 # Line Comment
  202 style.verilog.2=$(colour.code.comment.line),$(font.code.comment.line)
  203 # Bang comment
  204 style.verilog.3=fore:#3F7F3F,$(font.code.comment.line),back:#E0F0FF,eolfilled
  205 # Number
  206 style.verilog.4=$(colour.number)
  207 # Keyword
  208 style.verilog.5=fore:#7f005f,bold
  209 # Double quoted string
  210 style.verilog.6=$(colour.string),$(font.string.literal)
  211 # Keyword2, Secondary keywords and identifiers
  212 style.verilog.7=fore:#007F7F
  213 # keywords3, System tasks
  214 style.verilog.8=fore:#804020
  215 # Preprocessor
  216 style.verilog.9=$(colour.preproc)
  217 # Operators
  218 style.verilog.10=fore:#007070
  219 # Identifiers
  220 style.verilog.11=
  221 # End of line where string is not closed
  222 style.verilog.12=fore:#000000,$(font.string.literal),back:#E0C0E0,eolfilled
  223 # keywords4, User defined identifiers and tasks
  224 style.verilog.19=fore:#2a00ff
  225 # comment keyword
  226 style.verilog.20=fore:#2A00FF
  227 # port declare (input output ioput)
  228 style.verilog.21=fore:#7F0000
  229 style.verilog.22=fore:#00007F
  230 style.verilog.23=fore:#0000FF
  231 # port connection
  232 style.verilog.24=fore:#005032,bold
  233 
  234 # Turn on port styling features
  235 lexer.verilog.portstyling=1
  236 # Turn on treatment of all uppercase identifiers as user-defined keywords
  237 lexer.verilog.allupperkeywords=1
  238 
  239 # Support for colorizing inactive code due to preprocessor directives
  240 lexer.verilog.track.preprocessor=1
  241 lexer.verilog.update.preprocessor=1
  242 
  243 # Inactive states are 64 greater than their active counterparts
  244 
  245 # White space
  246 style.verilog.64=back:#E0E0E0,eolfilled
  247 style.verilog.65=back:#E0E0E0,eolfilled,fore:#808080,italics
  248 style.verilog.66=back:#E0E0E0,eolfilled,fore:#808080,italics
  249 style.verilog.67=back:#E0E0E0,eolfilled,fore:#808080,italics
  250 style.verilog.68=back:#E0E0E0,eolfilled,fore:#808080,italics
  251 style.verilog.69=back:#E0E0E0,eolfilled,fore:#808080,italics
  252 style.verilog.70=back:#E0E0E0,eolfilled,fore:#808080,italics
  253 style.verilog.71=back:#E0E0E0,eolfilled,fore:#808080,italics
  254 style.verilog.72=back:#E0E0E0,eolfilled,fore:#808080,italics
  255 style.verilog.73=back:#E0E0E0,eolfilled,fore:#808080,italics
  256 style.verilog.74=back:#E0E0E0,eolfilled,fore:#808080,italics
  257 style.verilog.75=back:#E0E0E0,eolfilled,fore:#808080,italics
  258 style.verilog.76=back:#E0E0E0,eolfilled,fore:#808080,italics
  259 style.verilog.83=back:#E0E0E0,eolfilled,fore:#808080,italics
  260 style.verilog.84=back:#E0E0E0,eolfilled,fore:#808080,italics
  261 style.verilog.85=back:#E0E0E0,eolfilled,fore:#808080,italics
  262 style.verilog.86=back:#E0E0E0,eolfilled,fore:#808080,italics
  263 style.verilog.87=back:#E0E0E0,eolfilled,fore:#808080,italics
  264 style.verilog.88=back:#E0E0E0,eolfilled,fore:#808080,italics
  265 
  266 # Braces are only matched in operator style
  267 braces.verilog.style=10
  268