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    1 /*
    2  *    Stack-less Just-In-Time compiler
    3  *
    4  *    Copyright 2013-2013 Tilera Corporation(jiwang@tilera.com). All rights reserved.
    5  *    Copyright 2009-2012 Zoltan Herczeg (hzmester@freemail.hu). All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without modification, are
    8  * permitted provided that the following conditions are met:
    9  *
   10  *   1. Redistributions of source code must retain the above copyright notice, this list of
   11  *      conditions and the following disclaimer.
   12  *
   13  *   2. Redistributions in binary form must reproduce the above copyright notice, this list
   14  *      of conditions and the following disclaimer in the documentation and/or other materials
   15  *      provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER(S) AND CONTRIBUTORS ``AS IS'' AND ANY
   18  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
   20  * SHALL THE COPYRIGHT HOLDER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
   21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
   22  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
   23  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
   25  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   26  */
   27 
   28 /* This code is owned by Tilera Corporation, and distributed as part
   29    of multiple projects. In sljit, the code is under BSD licence.  */
   30 
   31 #include <stdio.h>
   32 #include <stdlib.h>
   33 #include <string.h>
   34 #define BFD_RELOC(x) R_##x
   35 
   36 /* Special registers. */
   37 #define TREG_LR 55
   38 #define TREG_SN 56
   39 #define TREG_ZERO 63
   40 
   41 /* Canonical name of each register. */
   42 const char *const tilegx_register_names[] =
   43 {
   44   "r0",   "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
   45   "r8",   "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
   46   "r16",  "r17", "r18", "r19", "r20", "r21", "r22", "r23",
   47   "r24",  "r25", "r26", "r27", "r28", "r29", "r30", "r31",
   48   "r32",  "r33", "r34", "r35", "r36", "r37", "r38", "r39",
   49   "r40",  "r41", "r42", "r43", "r44", "r45", "r46", "r47",
   50   "r48",  "r49", "r50", "r51", "r52", "tp",  "sp",  "lr",
   51   "sn",  "idn0", "idn1", "udn0", "udn1", "udn2", "udn3", "zero"
   52 };
   53 
   54 enum
   55 {
   56   R_NONE = 0,
   57   R_TILEGX_NONE = 0,
   58   R_TILEGX_64 = 1,
   59   R_TILEGX_32 = 2,
   60   R_TILEGX_16 = 3,
   61   R_TILEGX_8 = 4,
   62   R_TILEGX_64_PCREL = 5,
   63   R_TILEGX_32_PCREL = 6,
   64   R_TILEGX_16_PCREL = 7,
   65   R_TILEGX_8_PCREL = 8,
   66   R_TILEGX_HW0 = 9,
   67   R_TILEGX_HW1 = 10,
   68   R_TILEGX_HW2 = 11,
   69   R_TILEGX_HW3 = 12,
   70   R_TILEGX_HW0_LAST = 13,
   71   R_TILEGX_HW1_LAST = 14,
   72   R_TILEGX_HW2_LAST = 15,
   73   R_TILEGX_COPY = 16,
   74   R_TILEGX_GLOB_DAT = 17,
   75   R_TILEGX_JMP_SLOT = 18,
   76   R_TILEGX_RELATIVE = 19,
   77   R_TILEGX_BROFF_X1 = 20,
   78   R_TILEGX_JUMPOFF_X1 = 21,
   79   R_TILEGX_JUMPOFF_X1_PLT = 22,
   80   R_TILEGX_IMM8_X0 = 23,
   81   R_TILEGX_IMM8_Y0 = 24,
   82   R_TILEGX_IMM8_X1 = 25,
   83   R_TILEGX_IMM8_Y1 = 26,
   84   R_TILEGX_DEST_IMM8_X1 = 27,
   85   R_TILEGX_MT_IMM14_X1 = 28,
   86   R_TILEGX_MF_IMM14_X1 = 29,
   87   R_TILEGX_MMSTART_X0 = 30,
   88   R_TILEGX_MMEND_X0 = 31,
   89   R_TILEGX_SHAMT_X0 = 32,
   90   R_TILEGX_SHAMT_X1 = 33,
   91   R_TILEGX_SHAMT_Y0 = 34,
   92   R_TILEGX_SHAMT_Y1 = 35,
   93   R_TILEGX_IMM16_X0_HW0 = 36,
   94   R_TILEGX_IMM16_X1_HW0 = 37,
   95   R_TILEGX_IMM16_X0_HW1 = 38,
   96   R_TILEGX_IMM16_X1_HW1 = 39,
   97   R_TILEGX_IMM16_X0_HW2 = 40,
   98   R_TILEGX_IMM16_X1_HW2 = 41,
   99   R_TILEGX_IMM16_X0_HW3 = 42,
  100   R_TILEGX_IMM16_X1_HW3 = 43,
  101   R_TILEGX_IMM16_X0_HW0_LAST = 44,
  102   R_TILEGX_IMM16_X1_HW0_LAST = 45,
  103   R_TILEGX_IMM16_X0_HW1_LAST = 46,
  104   R_TILEGX_IMM16_X1_HW1_LAST = 47,
  105   R_TILEGX_IMM16_X0_HW2_LAST = 48,
  106   R_TILEGX_IMM16_X1_HW2_LAST = 49,
  107   R_TILEGX_IMM16_X0_HW0_PCREL = 50,
  108   R_TILEGX_IMM16_X1_HW0_PCREL = 51,
  109   R_TILEGX_IMM16_X0_HW1_PCREL = 52,
  110   R_TILEGX_IMM16_X1_HW1_PCREL = 53,
  111   R_TILEGX_IMM16_X0_HW2_PCREL = 54,
  112   R_TILEGX_IMM16_X1_HW2_PCREL = 55,
  113   R_TILEGX_IMM16_X0_HW3_PCREL = 56,
  114   R_TILEGX_IMM16_X1_HW3_PCREL = 57,
  115   R_TILEGX_IMM16_X0_HW0_LAST_PCREL = 58,
  116   R_TILEGX_IMM16_X1_HW0_LAST_PCREL = 59,
  117   R_TILEGX_IMM16_X0_HW1_LAST_PCREL = 60,
  118   R_TILEGX_IMM16_X1_HW1_LAST_PCREL = 61,
  119   R_TILEGX_IMM16_X0_HW2_LAST_PCREL = 62,
  120   R_TILEGX_IMM16_X1_HW2_LAST_PCREL = 63,
  121   R_TILEGX_IMM16_X0_HW0_GOT = 64,
  122   R_TILEGX_IMM16_X1_HW0_GOT = 65,
  123 
  124   R_TILEGX_IMM16_X0_HW0_PLT_PCREL = 66,
  125   R_TILEGX_IMM16_X1_HW0_PLT_PCREL = 67,
  126   R_TILEGX_IMM16_X0_HW1_PLT_PCREL = 68,
  127   R_TILEGX_IMM16_X1_HW1_PLT_PCREL = 69,
  128   R_TILEGX_IMM16_X0_HW2_PLT_PCREL = 70,
  129   R_TILEGX_IMM16_X1_HW2_PLT_PCREL = 71,
  130 
  131   R_TILEGX_IMM16_X0_HW0_LAST_GOT = 72,
  132   R_TILEGX_IMM16_X1_HW0_LAST_GOT = 73,
  133   R_TILEGX_IMM16_X0_HW1_LAST_GOT = 74,
  134   R_TILEGX_IMM16_X1_HW1_LAST_GOT = 75,
  135   R_TILEGX_IMM16_X0_HW0_TLS_GD = 78,
  136   R_TILEGX_IMM16_X1_HW0_TLS_GD = 79,
  137   R_TILEGX_IMM16_X0_HW0_TLS_LE = 80,
  138   R_TILEGX_IMM16_X1_HW0_TLS_LE = 81,
  139   R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE = 82,
  140   R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE = 83,
  141   R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE = 84,
  142   R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE = 85,
  143   R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD = 86,
  144   R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD = 87,
  145   R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD = 88,
  146   R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD = 89,
  147   R_TILEGX_IMM16_X0_HW0_TLS_IE = 92,
  148   R_TILEGX_IMM16_X1_HW0_TLS_IE = 93,
  149 
  150   R_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL = 94,
  151   R_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL = 95,
  152   R_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL = 96,
  153   R_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL = 97,
  154   R_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL = 98,
  155   R_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL = 99,
  156 
  157   R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE = 100,
  158   R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE = 101,
  159   R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE = 102,
  160   R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE = 103,
  161   R_TILEGX_TLS_DTPMOD64 = 106,
  162   R_TILEGX_TLS_DTPOFF64 = 107,
  163   R_TILEGX_TLS_TPOFF64 = 108,
  164   R_TILEGX_TLS_DTPMOD32 = 109,
  165   R_TILEGX_TLS_DTPOFF32 = 110,
  166   R_TILEGX_TLS_TPOFF32 = 111,
  167   R_TILEGX_TLS_GD_CALL = 112,
  168   R_TILEGX_IMM8_X0_TLS_GD_ADD = 113,
  169   R_TILEGX_IMM8_X1_TLS_GD_ADD = 114,
  170   R_TILEGX_IMM8_Y0_TLS_GD_ADD = 115,
  171   R_TILEGX_IMM8_Y1_TLS_GD_ADD = 116,
  172   R_TILEGX_TLS_IE_LOAD = 117,
  173   R_TILEGX_IMM8_X0_TLS_ADD = 118,
  174   R_TILEGX_IMM8_X1_TLS_ADD = 119,
  175   R_TILEGX_IMM8_Y0_TLS_ADD = 120,
  176   R_TILEGX_IMM8_Y1_TLS_ADD = 121,
  177   R_TILEGX_GNU_VTINHERIT = 128,
  178   R_TILEGX_GNU_VTENTRY = 129,
  179   R_TILEGX_IRELATIVE = 130,
  180   R_TILEGX_NUM = 131
  181 };
  182 
  183 typedef enum
  184 {
  185   TILEGX_PIPELINE_X0,
  186   TILEGX_PIPELINE_X1,
  187   TILEGX_PIPELINE_Y0,
  188   TILEGX_PIPELINE_Y1,
  189   TILEGX_PIPELINE_Y2,
  190 } tilegx_pipeline;
  191 
  192 typedef unsigned long long tilegx_bundle_bits;
  193 
  194 /* These are the bits that determine if a bundle is in the X encoding. */
  195 #define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62)
  196 
  197 enum
  198 {
  199   /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
  200   TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
  201 
  202   /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
  203   TILEGX_NUM_PIPELINE_ENCODINGS = 5,
  204 
  205   /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
  206   TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
  207 
  208   /* Instructions take this many bytes. */
  209   TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
  210 
  211   /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
  212   TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
  213 
  214   /* Bundles should be aligned modulo this number of bytes. */
  215   TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
  216     (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
  217 
  218   /* Number of registers (some are magic, such as network I/O). */
  219   TILEGX_NUM_REGISTERS = 64,
  220 };
  221 
  222 /* Make a few "tile_" variables to simplify common code between
  223    architectures.  */
  224 
  225 typedef tilegx_bundle_bits tile_bundle_bits;
  226 #define TILE_BUNDLE_SIZE_IN_BYTES TILEGX_BUNDLE_SIZE_IN_BYTES
  227 #define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES
  228 #define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \
  229   TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES
  230 
  231 /* 64-bit pattern for a { bpt ; nop } bundle. */
  232 #define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
  233 
  234 typedef enum
  235 {
  236   TILEGX_OP_TYPE_REGISTER,
  237   TILEGX_OP_TYPE_IMMEDIATE,
  238   TILEGX_OP_TYPE_ADDRESS,
  239   TILEGX_OP_TYPE_SPR
  240 } tilegx_operand_type;
  241 
  242 struct tilegx_operand
  243 {
  244   /* Is this operand a register, immediate or address? */
  245   tilegx_operand_type type;
  246 
  247   /* The default relocation type for this operand.  */
  248   signed int default_reloc : 16;
  249 
  250   /* How many bits is this value? (used for range checking) */
  251   unsigned int num_bits : 5;
  252 
  253   /* Is the value signed? (used for range checking) */
  254   unsigned int is_signed : 1;
  255 
  256   /* Is this operand a source register? */
  257   unsigned int is_src_reg : 1;
  258 
  259   /* Is this operand written? (i.e. is it a destination register) */
  260   unsigned int is_dest_reg : 1;
  261 
  262   /* Is this operand PC-relative? */
  263   unsigned int is_pc_relative : 1;
  264 
  265   /* By how many bits do we right shift the value before inserting? */
  266   unsigned int rightshift : 2;
  267 
  268   /* Return the bits for this operand to be ORed into an existing bundle. */
  269   tilegx_bundle_bits (*insert) (int op);
  270 
  271   /* Extract this operand and return it. */
  272   unsigned int (*extract) (tilegx_bundle_bits bundle);
  273 };
  274 
  275 typedef enum
  276 {
  277   TILEGX_OPC_BPT,
  278   TILEGX_OPC_INFO,
  279   TILEGX_OPC_INFOL,
  280   TILEGX_OPC_LD4S_TLS,
  281   TILEGX_OPC_LD_TLS,
  282   TILEGX_OPC_MOVE,
  283   TILEGX_OPC_MOVEI,
  284   TILEGX_OPC_MOVELI,
  285   TILEGX_OPC_PREFETCH,
  286   TILEGX_OPC_PREFETCH_ADD_L1,
  287   TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
  288   TILEGX_OPC_PREFETCH_ADD_L2,
  289   TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
  290   TILEGX_OPC_PREFETCH_ADD_L3,
  291   TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
  292   TILEGX_OPC_PREFETCH_L1,
  293   TILEGX_OPC_PREFETCH_L1_FAULT,
  294   TILEGX_OPC_PREFETCH_L2,
  295   TILEGX_OPC_PREFETCH_L2_FAULT,
  296   TILEGX_OPC_PREFETCH_L3,
  297   TILEGX_OPC_PREFETCH_L3_FAULT,
  298   TILEGX_OPC_RAISE,
  299   TILEGX_OPC_ADD,
  300   TILEGX_OPC_ADDI,
  301   TILEGX_OPC_ADDLI,
  302   TILEGX_OPC_ADDX,
  303   TILEGX_OPC_ADDXI,
  304   TILEGX_OPC_ADDXLI,
  305   TILEGX_OPC_ADDXSC,
  306   TILEGX_OPC_AND,
  307   TILEGX_OPC_ANDI,
  308   TILEGX_OPC_BEQZ,
  309   TILEGX_OPC_BEQZT,
  310   TILEGX_OPC_BFEXTS,
  311   TILEGX_OPC_BFEXTU,
  312   TILEGX_OPC_BFINS,
  313   TILEGX_OPC_BGEZ,
  314   TILEGX_OPC_BGEZT,
  315   TILEGX_OPC_BGTZ,
  316   TILEGX_OPC_BGTZT,
  317   TILEGX_OPC_BLBC,
  318   TILEGX_OPC_BLBCT,
  319   TILEGX_OPC_BLBS,
  320   TILEGX_OPC_BLBST,
  321   TILEGX_OPC_BLEZ,
  322   TILEGX_OPC_BLEZT,
  323   TILEGX_OPC_BLTZ,
  324   TILEGX_OPC_BLTZT,
  325   TILEGX_OPC_BNEZ,
  326   TILEGX_OPC_BNEZT,
  327   TILEGX_OPC_CLZ,
  328   TILEGX_OPC_CMOVEQZ,
  329   TILEGX_OPC_CMOVNEZ,
  330   TILEGX_OPC_CMPEQ,
  331   TILEGX_OPC_CMPEQI,
  332   TILEGX_OPC_CMPEXCH,
  333   TILEGX_OPC_CMPEXCH4,
  334   TILEGX_OPC_CMPLES,
  335   TILEGX_OPC_CMPLEU,
  336   TILEGX_OPC_CMPLTS,
  337   TILEGX_OPC_CMPLTSI,
  338   TILEGX_OPC_CMPLTU,
  339   TILEGX_OPC_CMPLTUI,
  340   TILEGX_OPC_CMPNE,
  341   TILEGX_OPC_CMUL,
  342   TILEGX_OPC_CMULA,
  343   TILEGX_OPC_CMULAF,
  344   TILEGX_OPC_CMULF,
  345   TILEGX_OPC_CMULFR,
  346   TILEGX_OPC_CMULH,
  347   TILEGX_OPC_CMULHR,
  348   TILEGX_OPC_CRC32_32,
  349   TILEGX_OPC_CRC32_8,
  350   TILEGX_OPC_CTZ,
  351   TILEGX_OPC_DBLALIGN,
  352   TILEGX_OPC_DBLALIGN2,
  353   TILEGX_OPC_DBLALIGN4,
  354   TILEGX_OPC_DBLALIGN6,
  355   TILEGX_OPC_DRAIN,
  356   TILEGX_OPC_DTLBPR,
  357   TILEGX_OPC_EXCH,
  358   TILEGX_OPC_EXCH4,
  359   TILEGX_OPC_FDOUBLE_ADD_FLAGS,
  360   TILEGX_OPC_FDOUBLE_ADDSUB,
  361   TILEGX_OPC_FDOUBLE_MUL_FLAGS,
  362   TILEGX_OPC_FDOUBLE_PACK1,
  363   TILEGX_OPC_FDOUBLE_PACK2,
  364   TILEGX_OPC_FDOUBLE_SUB_FLAGS,
  365   TILEGX_OPC_FDOUBLE_UNPACK_MAX,
  366   TILEGX_OPC_FDOUBLE_UNPACK_MIN,
  367   TILEGX_OPC_FETCHADD,
  368   TILEGX_OPC_FETCHADD4,
  369   TILEGX_OPC_FETCHADDGEZ,
  370   TILEGX_OPC_FETCHADDGEZ4,
  371   TILEGX_OPC_FETCHAND,
  372   TILEGX_OPC_FETCHAND4,
  373   TILEGX_OPC_FETCHOR,
  374   TILEGX_OPC_FETCHOR4,
  375   TILEGX_OPC_FINV,
  376   TILEGX_OPC_FLUSH,
  377   TILEGX_OPC_FLUSHWB,
  378   TILEGX_OPC_FNOP,
  379   TILEGX_OPC_FSINGLE_ADD1,
  380   TILEGX_OPC_FSINGLE_ADDSUB2,
  381   TILEGX_OPC_FSINGLE_MUL1,
  382   TILEGX_OPC_FSINGLE_MUL2,
  383   TILEGX_OPC_FSINGLE_PACK1,
  384   TILEGX_OPC_FSINGLE_PACK2,
  385   TILEGX_OPC_FSINGLE_SUB1,
  386   TILEGX_OPC_ICOH,
  387   TILEGX_OPC_ILL,
  388   TILEGX_OPC_INV,
  389   TILEGX_OPC_IRET,
  390   TILEGX_OPC_J,
  391   TILEGX_OPC_JAL,
  392   TILEGX_OPC_JALR,
  393   TILEGX_OPC_JALRP,
  394   TILEGX_OPC_JR,
  395   TILEGX_OPC_JRP,
  396   TILEGX_OPC_LD,
  397   TILEGX_OPC_LD1S,
  398   TILEGX_OPC_LD1S_ADD,
  399   TILEGX_OPC_LD1U,
  400   TILEGX_OPC_LD1U_ADD,
  401   TILEGX_OPC_LD2S,
  402   TILEGX_OPC_LD2S_ADD,
  403   TILEGX_OPC_LD2U,
  404   TILEGX_OPC_LD2U_ADD,
  405   TILEGX_OPC_LD4S,
  406   TILEGX_OPC_LD4S_ADD,
  407   TILEGX_OPC_LD4U,
  408   TILEGX_OPC_LD4U_ADD,
  409   TILEGX_OPC_LD_ADD,
  410   TILEGX_OPC_LDNA,
  411   TILEGX_OPC_LDNA_ADD,
  412   TILEGX_OPC_LDNT,
  413   TILEGX_OPC_LDNT1S,
  414   TILEGX_OPC_LDNT1S_ADD,
  415   TILEGX_OPC_LDNT1U,
  416   TILEGX_OPC_LDNT1U_ADD,
  417   TILEGX_OPC_LDNT2S,
  418   TILEGX_OPC_LDNT2S_ADD,
  419   TILEGX_OPC_LDNT2U,
  420   TILEGX_OPC_LDNT2U_ADD,
  421   TILEGX_OPC_LDNT4S,
  422   TILEGX_OPC_LDNT4S_ADD,
  423   TILEGX_OPC_LDNT4U,
  424   TILEGX_OPC_LDNT4U_ADD,
  425   TILEGX_OPC_LDNT_ADD,
  426   TILEGX_OPC_LNK,
  427   TILEGX_OPC_MF,
  428   TILEGX_OPC_MFSPR,
  429   TILEGX_OPC_MM,
  430   TILEGX_OPC_MNZ,
  431   TILEGX_OPC_MTSPR,
  432   TILEGX_OPC_MUL_HS_HS,
  433   TILEGX_OPC_MUL_HS_HU,
  434   TILEGX_OPC_MUL_HS_LS,
  435   TILEGX_OPC_MUL_HS_LU,
  436   TILEGX_OPC_MUL_HU_HU,
  437   TILEGX_OPC_MUL_HU_LS,
  438   TILEGX_OPC_MUL_HU_LU,
  439   TILEGX_OPC_MUL_LS_LS,
  440   TILEGX_OPC_MUL_LS_LU,
  441   TILEGX_OPC_MUL_LU_LU,
  442   TILEGX_OPC_MULA_HS_HS,
  443   TILEGX_OPC_MULA_HS_HU,
  444   TILEGX_OPC_MULA_HS_LS,
  445   TILEGX_OPC_MULA_HS_LU,
  446   TILEGX_OPC_MULA_HU_HU,
  447   TILEGX_OPC_MULA_HU_LS,
  448   TILEGX_OPC_MULA_HU_LU,
  449   TILEGX_OPC_MULA_LS_LS,
  450   TILEGX_OPC_MULA_LS_LU,
  451   TILEGX_OPC_MULA_LU_LU,
  452   TILEGX_OPC_MULAX,
  453   TILEGX_OPC_MULX,
  454   TILEGX_OPC_MZ,
  455   TILEGX_OPC_NAP,
  456   TILEGX_OPC_NOP,
  457   TILEGX_OPC_NOR,
  458   TILEGX_OPC_OR,
  459   TILEGX_OPC_ORI,
  460   TILEGX_OPC_PCNT,
  461   TILEGX_OPC_REVBITS,
  462   TILEGX_OPC_REVBYTES,
  463   TILEGX_OPC_ROTL,
  464   TILEGX_OPC_ROTLI,
  465   TILEGX_OPC_SHL,
  466   TILEGX_OPC_SHL16INSLI,
  467   TILEGX_OPC_SHL1ADD,
  468   TILEGX_OPC_SHL1ADDX,
  469   TILEGX_OPC_SHL2ADD,
  470   TILEGX_OPC_SHL2ADDX,
  471   TILEGX_OPC_SHL3ADD,
  472   TILEGX_OPC_SHL3ADDX,
  473   TILEGX_OPC_SHLI,
  474   TILEGX_OPC_SHLX,
  475   TILEGX_OPC_SHLXI,
  476   TILEGX_OPC_SHRS,
  477   TILEGX_OPC_SHRSI,
  478   TILEGX_OPC_SHRU,
  479   TILEGX_OPC_SHRUI,
  480   TILEGX_OPC_SHRUX,
  481   TILEGX_OPC_SHRUXI,
  482   TILEGX_OPC_SHUFFLEBYTES,
  483   TILEGX_OPC_ST,
  484   TILEGX_OPC_ST1,
  485   TILEGX_OPC_ST1_ADD,
  486   TILEGX_OPC_ST2,
  487   TILEGX_OPC_ST2_ADD,
  488   TILEGX_OPC_ST4,
  489   TILEGX_OPC_ST4_ADD,
  490   TILEGX_OPC_ST_ADD,
  491   TILEGX_OPC_STNT,
  492   TILEGX_OPC_STNT1,
  493   TILEGX_OPC_STNT1_ADD,
  494   TILEGX_OPC_STNT2,
  495   TILEGX_OPC_STNT2_ADD,
  496   TILEGX_OPC_STNT4,
  497   TILEGX_OPC_STNT4_ADD,
  498   TILEGX_OPC_STNT_ADD,
  499   TILEGX_OPC_SUB,
  500   TILEGX_OPC_SUBX,
  501   TILEGX_OPC_SUBXSC,
  502   TILEGX_OPC_SWINT0,
  503   TILEGX_OPC_SWINT1,
  504   TILEGX_OPC_SWINT2,
  505   TILEGX_OPC_SWINT3,
  506   TILEGX_OPC_TBLIDXB0,
  507   TILEGX_OPC_TBLIDXB1,
  508   TILEGX_OPC_TBLIDXB2,
  509   TILEGX_OPC_TBLIDXB3,
  510   TILEGX_OPC_V1ADD,
  511   TILEGX_OPC_V1ADDI,
  512   TILEGX_OPC_V1ADDUC,
  513   TILEGX_OPC_V1ADIFFU,
  514   TILEGX_OPC_V1AVGU,
  515   TILEGX_OPC_V1CMPEQ,
  516   TILEGX_OPC_V1CMPEQI,
  517   TILEGX_OPC_V1CMPLES,
  518   TILEGX_OPC_V1CMPLEU,
  519   TILEGX_OPC_V1CMPLTS,
  520   TILEGX_OPC_V1CMPLTSI,
  521   TILEGX_OPC_V1CMPLTU,
  522   TILEGX_OPC_V1CMPLTUI,
  523   TILEGX_OPC_V1CMPNE,
  524   TILEGX_OPC_V1DDOTPU,
  525   TILEGX_OPC_V1DDOTPUA,
  526   TILEGX_OPC_V1DDOTPUS,
  527   TILEGX_OPC_V1DDOTPUSA,
  528   TILEGX_OPC_V1DOTP,
  529   TILEGX_OPC_V1DOTPA,
  530   TILEGX_OPC_V1DOTPU,
  531   TILEGX_OPC_V1DOTPUA,
  532   TILEGX_OPC_V1DOTPUS,
  533   TILEGX_OPC_V1DOTPUSA,
  534   TILEGX_OPC_V1INT_H,
  535   TILEGX_OPC_V1INT_L,
  536   TILEGX_OPC_V1MAXU,
  537   TILEGX_OPC_V1MAXUI,
  538   TILEGX_OPC_V1MINU,
  539   TILEGX_OPC_V1MINUI,
  540   TILEGX_OPC_V1MNZ,
  541   TILEGX_OPC_V1MULTU,
  542   TILEGX_OPC_V1MULU,
  543   TILEGX_OPC_V1MULUS,
  544   TILEGX_OPC_V1MZ,
  545   TILEGX_OPC_V1SADAU,
  546   TILEGX_OPC_V1SADU,
  547   TILEGX_OPC_V1SHL,
  548   TILEGX_OPC_V1SHLI,
  549   TILEGX_OPC_V1SHRS,
  550   TILEGX_OPC_V1SHRSI,
  551   TILEGX_OPC_V1SHRU,
  552   TILEGX_OPC_V1SHRUI,
  553   TILEGX_OPC_V1SUB,
  554   TILEGX_OPC_V1SUBUC,
  555   TILEGX_OPC_V2ADD,
  556   TILEGX_OPC_V2ADDI,
  557   TILEGX_OPC_V2ADDSC,
  558   TILEGX_OPC_V2ADIFFS,
  559   TILEGX_OPC_V2AVGS,
  560   TILEGX_OPC_V2CMPEQ,
  561   TILEGX_OPC_V2CMPEQI,
  562   TILEGX_OPC_V2CMPLES,
  563   TILEGX_OPC_V2CMPLEU,
  564   TILEGX_OPC_V2CMPLTS,
  565   TILEGX_OPC_V2CMPLTSI,
  566   TILEGX_OPC_V2CMPLTU,
  567   TILEGX_OPC_V2CMPLTUI,
  568   TILEGX_OPC_V2CMPNE,
  569   TILEGX_OPC_V2DOTP,
  570   TILEGX_OPC_V2DOTPA,
  571   TILEGX_OPC_V2INT_H,
  572   TILEGX_OPC_V2INT_L,
  573   TILEGX_OPC_V2MAXS,
  574   TILEGX_OPC_V2MAXSI,
  575   TILEGX_OPC_V2MINS,
  576   TILEGX_OPC_V2MINSI,
  577   TILEGX_OPC_V2MNZ,
  578   TILEGX_OPC_V2MULFSC,
  579   TILEGX_OPC_V2MULS,
  580   TILEGX_OPC_V2MULTS,
  581   TILEGX_OPC_V2MZ,
  582   TILEGX_OPC_V2PACKH,
  583   TILEGX_OPC_V2PACKL,
  584   TILEGX_OPC_V2PACKUC,
  585   TILEGX_OPC_V2SADAS,
  586   TILEGX_OPC_V2SADAU,
  587   TILEGX_OPC_V2SADS,
  588   TILEGX_OPC_V2SADU,
  589   TILEGX_OPC_V2SHL,
  590   TILEGX_OPC_V2SHLI,
  591   TILEGX_OPC_V2SHLSC,
  592   TILEGX_OPC_V2SHRS,
  593   TILEGX_OPC_V2SHRSI,
  594   TILEGX_OPC_V2SHRU,
  595   TILEGX_OPC_V2SHRUI,
  596   TILEGX_OPC_V2SUB,
  597   TILEGX_OPC_V2SUBSC,
  598   TILEGX_OPC_V4ADD,
  599   TILEGX_OPC_V4ADDSC,
  600   TILEGX_OPC_V4INT_H,
  601   TILEGX_OPC_V4INT_L,
  602   TILEGX_OPC_V4PACKSC,
  603   TILEGX_OPC_V4SHL,
  604   TILEGX_OPC_V4SHLSC,
  605   TILEGX_OPC_V4SHRS,
  606   TILEGX_OPC_V4SHRU,
  607   TILEGX_OPC_V4SUB,
  608   TILEGX_OPC_V4SUBSC,
  609   TILEGX_OPC_WH64,
  610   TILEGX_OPC_XOR,
  611   TILEGX_OPC_XORI,
  612   TILEGX_OPC_NONE
  613 } tilegx_mnemonic;
  614 
  615 enum
  616 {
  617   TILEGX_MAX_OPERANDS = 4 /* bfexts */
  618 };
  619 
  620 struct tilegx_opcode
  621 {
  622   /* The opcode mnemonic, e.g. "add" */
  623   const char *name;
  624 
  625   /* The enum value for this mnemonic. */
  626   tilegx_mnemonic mnemonic;
  627 
  628   /* A bit mask of which of the five pipes this instruction
  629      is compatible with:
  630      X0  0x01
  631      X1  0x02
  632      Y0  0x04
  633      Y1  0x08
  634      Y2  0x10 */
  635   unsigned char pipes;
  636 
  637   /* How many operands are there? */
  638   unsigned char num_operands;
  639 
  640   /* Which register does this write implicitly, or TREG_ZERO if none? */
  641   unsigned char implicitly_written_register;
  642 
  643   /* Can this be bundled with other instructions (almost always true). */
  644   unsigned char can_bundle;
  645 
  646   /* The description of the operands. Each of these is an
  647    * index into the tilegx_operands[] table. */
  648   unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS];
  649 
  650   /* A mask of which bits have predefined values for each pipeline.
  651    * This is useful for disassembly. */
  652   tilegx_bundle_bits fixed_bit_masks[TILEGX_NUM_PIPELINE_ENCODINGS];
  653 
  654   /* For each bit set in fixed_bit_masks, what the value is for this
  655    * instruction. */
  656   tilegx_bundle_bits fixed_bit_values[TILEGX_NUM_PIPELINE_ENCODINGS];
  657 };
  658 
  659 /* Used for non-textual disassembly into structs. */
  660 struct tilegx_decoded_instruction
  661 {
  662   const struct tilegx_opcode *opcode;
  663   const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS];
  664   long long operand_values[TILEGX_MAX_OPERANDS];
  665 };
  666 
  667 enum
  668 {
  669   ADDI_IMM8_OPCODE_X0 = 1,
  670   ADDI_IMM8_OPCODE_X1 = 1,
  671   ADDI_OPCODE_Y0 = 0,
  672   ADDI_OPCODE_Y1 = 1,
  673   ADDLI_OPCODE_X0 = 1,
  674   ADDLI_OPCODE_X1 = 0,
  675   ADDXI_IMM8_OPCODE_X0 = 2,
  676   ADDXI_IMM8_OPCODE_X1 = 2,
  677   ADDXI_OPCODE_Y0 = 1,
  678   ADDXI_OPCODE_Y1 = 2,
  679   ADDXLI_OPCODE_X0 = 2,
  680   ADDXLI_OPCODE_X1 = 1,
  681   ADDXSC_RRR_0_OPCODE_X0 = 1,
  682   ADDXSC_RRR_0_OPCODE_X1 = 1,
  683   ADDX_RRR_0_OPCODE_X0 = 2,
  684   ADDX_RRR_0_OPCODE_X1 = 2,
  685   ADDX_RRR_0_OPCODE_Y0 = 0,
  686   ADDX_SPECIAL_0_OPCODE_Y1 = 0,
  687   ADD_RRR_0_OPCODE_X0 = 3,
  688   ADD_RRR_0_OPCODE_X1 = 3,
  689   ADD_RRR_0_OPCODE_Y0 = 1,
  690   ADD_SPECIAL_0_OPCODE_Y1 = 1,
  691   ANDI_IMM8_OPCODE_X0 = 3,
  692   ANDI_IMM8_OPCODE_X1 = 3,
  693   ANDI_OPCODE_Y0 = 2,
  694   ANDI_OPCODE_Y1 = 3,
  695   AND_RRR_0_OPCODE_X0 = 4,
  696   AND_RRR_0_OPCODE_X1 = 4,
  697   AND_RRR_5_OPCODE_Y0 = 0,
  698   AND_RRR_5_OPCODE_Y1 = 0,
  699   BEQZT_BRANCH_OPCODE_X1 = 16,
  700   BEQZ_BRANCH_OPCODE_X1 = 17,
  701   BFEXTS_BF_OPCODE_X0 = 4,
  702   BFEXTU_BF_OPCODE_X0 = 5,
  703   BFINS_BF_OPCODE_X0 = 6,
  704   BF_OPCODE_X0 = 3,
  705   BGEZT_BRANCH_OPCODE_X1 = 18,
  706   BGEZ_BRANCH_OPCODE_X1 = 19,
  707   BGTZT_BRANCH_OPCODE_X1 = 20,
  708   BGTZ_BRANCH_OPCODE_X1 = 21,
  709   BLBCT_BRANCH_OPCODE_X1 = 22,
  710   BLBC_BRANCH_OPCODE_X1 = 23,
  711   BLBST_BRANCH_OPCODE_X1 = 24,
  712   BLBS_BRANCH_OPCODE_X1 = 25,
  713   BLEZT_BRANCH_OPCODE_X1 = 26,
  714   BLEZ_BRANCH_OPCODE_X1 = 27,
  715   BLTZT_BRANCH_OPCODE_X1 = 28,
  716   BLTZ_BRANCH_OPCODE_X1 = 29,
  717   BNEZT_BRANCH_OPCODE_X1 = 30,
  718   BNEZ_BRANCH_OPCODE_X1 = 31,
  719   BRANCH_OPCODE_X1 = 2,
  720   CMOVEQZ_RRR_0_OPCODE_X0 = 5,
  721   CMOVEQZ_RRR_4_OPCODE_Y0 = 0,
  722   CMOVNEZ_RRR_0_OPCODE_X0 = 6,
  723   CMOVNEZ_RRR_4_OPCODE_Y0 = 1,
  724   CMPEQI_IMM8_OPCODE_X0 = 4,
  725   CMPEQI_IMM8_OPCODE_X1 = 4,
  726   CMPEQI_OPCODE_Y0 = 3,
  727   CMPEQI_OPCODE_Y1 = 4,
  728   CMPEQ_RRR_0_OPCODE_X0 = 7,
  729   CMPEQ_RRR_0_OPCODE_X1 = 5,
  730   CMPEQ_RRR_3_OPCODE_Y0 = 0,
  731   CMPEQ_RRR_3_OPCODE_Y1 = 2,
  732   CMPEXCH4_RRR_0_OPCODE_X1 = 6,
  733   CMPEXCH_RRR_0_OPCODE_X1 = 7,
  734   CMPLES_RRR_0_OPCODE_X0 = 8,
  735   CMPLES_RRR_0_OPCODE_X1 = 8,
  736   CMPLES_RRR_2_OPCODE_Y0 = 0,
  737   CMPLES_RRR_2_OPCODE_Y1 = 0,
  738   CMPLEU_RRR_0_OPCODE_X0 = 9,
  739   CMPLEU_RRR_0_OPCODE_X1 = 9,
  740   CMPLEU_RRR_2_OPCODE_Y0 = 1,
  741   CMPLEU_RRR_2_OPCODE_Y1 = 1,
  742   CMPLTSI_IMM8_OPCODE_X0 = 5,
  743   CMPLTSI_IMM8_OPCODE_X1 = 5,
  744   CMPLTSI_OPCODE_Y0 = 4,
  745   CMPLTSI_OPCODE_Y1 = 5,
  746   CMPLTS_RRR_0_OPCODE_X0 = 10,
  747   CMPLTS_RRR_0_OPCODE_X1 = 10,
  748   CMPLTS_RRR_2_OPCODE_Y0 = 2,
  749   CMPLTS_RRR_2_OPCODE_Y1 = 2,
  750   CMPLTUI_IMM8_OPCODE_X0 = 6,
  751   CMPLTUI_IMM8_OPCODE_X1 = 6,
  752   CMPLTU_RRR_0_OPCODE_X0 = 11,
  753   CMPLTU_RRR_0_OPCODE_X1 = 11,
  754   CMPLTU_RRR_2_OPCODE_Y0 = 3,
  755   CMPLTU_RRR_2_OPCODE_Y1 = 3,
  756   CMPNE_RRR_0_OPCODE_X0 = 12,
  757   CMPNE_RRR_0_OPCODE_X1 = 12,
  758   CMPNE_RRR_3_OPCODE_Y0 = 1,
  759   CMPNE_RRR_3_OPCODE_Y1 = 3,
  760   CMULAF_RRR_0_OPCODE_X0 = 13,
  761   CMULA_RRR_0_OPCODE_X0 = 14,
  762   CMULFR_RRR_0_OPCODE_X0 = 15,
  763   CMULF_RRR_0_OPCODE_X0 = 16,
  764   CMULHR_RRR_0_OPCODE_X0 = 17,
  765   CMULH_RRR_0_OPCODE_X0 = 18,
  766   CMUL_RRR_0_OPCODE_X0 = 19,
  767   CNTLZ_UNARY_OPCODE_X0 = 1,
  768   CNTLZ_UNARY_OPCODE_Y0 = 1,
  769   CNTTZ_UNARY_OPCODE_X0 = 2,
  770   CNTTZ_UNARY_OPCODE_Y0 = 2,
  771   CRC32_32_RRR_0_OPCODE_X0 = 20,
  772   CRC32_8_RRR_0_OPCODE_X0 = 21,
  773   DBLALIGN2_RRR_0_OPCODE_X0 = 22,
  774   DBLALIGN2_RRR_0_OPCODE_X1 = 13,
  775   DBLALIGN4_RRR_0_OPCODE_X0 = 23,
  776   DBLALIGN4_RRR_0_OPCODE_X1 = 14,
  777   DBLALIGN6_RRR_0_OPCODE_X0 = 24,
  778   DBLALIGN6_RRR_0_OPCODE_X1 = 15,
  779   DBLALIGN_RRR_0_OPCODE_X0 = 25,
  780   DRAIN_UNARY_OPCODE_X1 = 1,
  781   DTLBPR_UNARY_OPCODE_X1 = 2,
  782   EXCH4_RRR_0_OPCODE_X1 = 16,
  783   EXCH_RRR_0_OPCODE_X1 = 17,
  784   FDOUBLE_ADDSUB_RRR_0_OPCODE_X0 = 26,
  785   FDOUBLE_ADD_FLAGS_RRR_0_OPCODE_X0 = 27,
  786   FDOUBLE_MUL_FLAGS_RRR_0_OPCODE_X0 = 28,
  787   FDOUBLE_PACK1_RRR_0_OPCODE_X0 = 29,
  788   FDOUBLE_PACK2_RRR_0_OPCODE_X0 = 30,
  789   FDOUBLE_SUB_FLAGS_RRR_0_OPCODE_X0 = 31,
  790   FDOUBLE_UNPACK_MAX_RRR_0_OPCODE_X0 = 32,
  791   FDOUBLE_UNPACK_MIN_RRR_0_OPCODE_X0 = 33,
  792   FETCHADD4_RRR_0_OPCODE_X1 = 18,
  793   FETCHADDGEZ4_RRR_0_OPCODE_X1 = 19,
  794   FETCHADDGEZ_RRR_0_OPCODE_X1 = 20,
  795   FETCHADD_RRR_0_OPCODE_X1 = 21,
  796   FETCHAND4_RRR_0_OPCODE_X1 = 22,
  797   FETCHAND_RRR_0_OPCODE_X1 = 23,
  798   FETCHOR4_RRR_0_OPCODE_X1 = 24,
  799   FETCHOR_RRR_0_OPCODE_X1 = 25,
  800   FINV_UNARY_OPCODE_X1 = 3,
  801   FLUSHWB_UNARY_OPCODE_X1 = 4,
  802   FLUSH_UNARY_OPCODE_X1 = 5,
  803   FNOP_UNARY_OPCODE_X0 = 3,
  804   FNOP_UNARY_OPCODE_X1 = 6,
  805   FNOP_UNARY_OPCODE_Y0 = 3,
  806   FNOP_UNARY_OPCODE_Y1 = 8,
  807   FSINGLE_ADD1_RRR_0_OPCODE_X0 = 34,
  808   FSINGLE_ADDSUB2_RRR_0_OPCODE_X0 = 35,
  809   FSINGLE_MUL1_RRR_0_OPCODE_X0 = 36,
  810   FSINGLE_MUL2_RRR_0_OPCODE_X0 = 37,
  811   FSINGLE_PACK1_UNARY_OPCODE_X0 = 4,
  812   FSINGLE_PACK1_UNARY_OPCODE_Y0 = 4,
  813   FSINGLE_PACK2_RRR_0_OPCODE_X0 = 38,
  814   FSINGLE_SUB1_RRR_0_OPCODE_X0 = 39,
  815   ICOH_UNARY_OPCODE_X1 = 7,
  816   ILL_UNARY_OPCODE_X1 = 8,
  817   ILL_UNARY_OPCODE_Y1 = 9,
  818   IMM8_OPCODE_X0 = 4,
  819   IMM8_OPCODE_X1 = 3,
  820   INV_UNARY_OPCODE_X1 = 9,
  821   IRET_UNARY_OPCODE_X1 = 10,
  822   JALRP_UNARY_OPCODE_X1 = 11,
  823   JALRP_UNARY_OPCODE_Y1 = 10,
  824   JALR_UNARY_OPCODE_X1 = 12,
  825   JALR_UNARY_OPCODE_Y1 = 11,
  826   JAL_JUMP_OPCODE_X1 = 0,
  827   JRP_UNARY_OPCODE_X1 = 13,
  828   JRP_UNARY_OPCODE_Y1 = 12,
  829   JR_UNARY_OPCODE_X1 = 14,
  830   JR_UNARY_OPCODE_Y1 = 13,
  831   JUMP_OPCODE_X1 = 4,
  832   J_JUMP_OPCODE_X1 = 1,
  833   LD1S_ADD_IMM8_OPCODE_X1 = 7,
  834   LD1S_OPCODE_Y2 = 0,
  835   LD1S_UNARY_OPCODE_X1 = 15,
  836   LD1U_ADD_IMM8_OPCODE_X1 = 8,
  837   LD1U_OPCODE_Y2 = 1,
  838   LD1U_UNARY_OPCODE_X1 = 16,
  839   LD2S_ADD_IMM8_OPCODE_X1 = 9,
  840   LD2S_OPCODE_Y2 = 2,
  841   LD2S_UNARY_OPCODE_X1 = 17,
  842   LD2U_ADD_IMM8_OPCODE_X1 = 10,
  843   LD2U_OPCODE_Y2 = 3,
  844   LD2U_UNARY_OPCODE_X1 = 18,
  845   LD4S_ADD_IMM8_OPCODE_X1 = 11,
  846   LD4S_OPCODE_Y2 = 1,
  847   LD4S_UNARY_OPCODE_X1 = 19,
  848   LD4U_ADD_IMM8_OPCODE_X1 = 12,
  849   LD4U_OPCODE_Y2 = 2,
  850   LD4U_UNARY_OPCODE_X1 = 20,
  851   LDNA_UNARY_OPCODE_X1 = 21,
  852   LDNT1S_ADD_IMM8_OPCODE_X1 = 13,
  853   LDNT1S_UNARY_OPCODE_X1 = 22,
  854   LDNT1U_ADD_IMM8_OPCODE_X1 = 14,
  855   LDNT1U_UNARY_OPCODE_X1 = 23,
  856   LDNT2S_ADD_IMM8_OPCODE_X1 = 15,
  857   LDNT2S_UNARY_OPCODE_X1 = 24,
  858   LDNT2U_ADD_IMM8_OPCODE_X1 = 16,
  859   LDNT2U_UNARY_OPCODE_X1 = 25,
  860   LDNT4S_ADD_IMM8_OPCODE_X1 = 17,
  861   LDNT4S_UNARY_OPCODE_X1 = 26,
  862   LDNT4U_ADD_IMM8_OPCODE_X1 = 18,
  863   LDNT4U_UNARY_OPCODE_X1 = 27,
  864   LDNT_ADD_IMM8_OPCODE_X1 = 19,
  865   LDNT_UNARY_OPCODE_X1 = 28,
  866   LD_ADD_IMM8_OPCODE_X1 = 20,
  867   LD_OPCODE_Y2 = 3,
  868   LD_UNARY_OPCODE_X1 = 29,
  869   LNK_UNARY_OPCODE_X1 = 30,
  870   LNK_UNARY_OPCODE_Y1 = 14,
  871   LWNA_ADD_IMM8_OPCODE_X1 = 21,
  872   MFSPR_IMM8_OPCODE_X1 = 22,
  873   MF_UNARY_OPCODE_X1 = 31,
  874   MM_BF_OPCODE_X0 = 7,
  875   MNZ_RRR_0_OPCODE_X0 = 40,
  876   MNZ_RRR_0_OPCODE_X1 = 26,
  877   MNZ_RRR_4_OPCODE_Y0 = 2,
  878   MNZ_RRR_4_OPCODE_Y1 = 2,
  879   MODE_OPCODE_YA2 = 1,
  880   MODE_OPCODE_YB2 = 2,
  881   MODE_OPCODE_YC2 = 3,
  882   MTSPR_IMM8_OPCODE_X1 = 23,
  883   MULAX_RRR_0_OPCODE_X0 = 41,
  884   MULAX_RRR_3_OPCODE_Y0 = 2,
  885   MULA_HS_HS_RRR_0_OPCODE_X0 = 42,
  886   MULA_HS_HS_RRR_9_OPCODE_Y0 = 0,
  887   MULA_HS_HU_RRR_0_OPCODE_X0 = 43,
  888   MULA_HS_LS_RRR_0_OPCODE_X0 = 44,
  889   MULA_HS_LU_RRR_0_OPCODE_X0 = 45,
  890   MULA_HU_HU_RRR_0_OPCODE_X0 = 46,
  891   MULA_HU_HU_RRR_9_OPCODE_Y0 = 1,
  892   MULA_HU_LS_RRR_0_OPCODE_X0 = 47,
  893   MULA_HU_LU_RRR_0_OPCODE_X0 = 48,
  894   MULA_LS_LS_RRR_0_OPCODE_X0 = 49,
  895   MULA_LS_LS_RRR_9_OPCODE_Y0 = 2,
  896   MULA_LS_LU_RRR_0_OPCODE_X0 = 50,
  897   MULA_LU_LU_RRR_0_OPCODE_X0 = 51,
  898   MULA_LU_LU_RRR_9_OPCODE_Y0 = 3,
  899   MULX_RRR_0_OPCODE_X0 = 52,
  900   MULX_RRR_3_OPCODE_Y0 = 3,
  901   MUL_HS_HS_RRR_0_OPCODE_X0 = 53,
  902   MUL_HS_HS_RRR_8_OPCODE_Y0 = 0,
  903   MUL_HS_HU_RRR_0_OPCODE_X0 = 54,
  904   MUL_HS_LS_RRR_0_OPCODE_X0 = 55,
  905   MUL_HS_LU_RRR_0_OPCODE_X0 = 56,
  906   MUL_HU_HU_RRR_0_OPCODE_X0 = 57,
  907   MUL_HU_HU_RRR_8_OPCODE_Y0 = 1,
  908   MUL_HU_LS_RRR_0_OPCODE_X0 = 58,
  909   MUL_HU_LU_RRR_0_OPCODE_X0 = 59,
  910   MUL_LS_LS_RRR_0_OPCODE_X0 = 60,
  911   MUL_LS_LS_RRR_8_OPCODE_Y0 = 2,
  912   MUL_LS_LU_RRR_0_OPCODE_X0 = 61,
  913   MUL_LU_LU_RRR_0_OPCODE_X0 = 62,
  914   MUL_LU_LU_RRR_8_OPCODE_Y0 = 3,
  915   MZ_RRR_0_OPCODE_X0 = 63,
  916   MZ_RRR_0_OPCODE_X1 = 27,
  917   MZ_RRR_4_OPCODE_Y0 = 3,
  918   MZ_RRR_4_OPCODE_Y1 = 3,
  919   NAP_UNARY_OPCODE_X1 = 32,
  920   NOP_UNARY_OPCODE_X0 = 5,
  921   NOP_UNARY_OPCODE_X1 = 33,
  922   NOP_UNARY_OPCODE_Y0 = 5,
  923   NOP_UNARY_OPCODE_Y1 = 15,
  924   NOR_RRR_0_OPCODE_X0 = 64,
  925   NOR_RRR_0_OPCODE_X1 = 28,
  926   NOR_RRR_5_OPCODE_Y0 = 1,
  927   NOR_RRR_5_OPCODE_Y1 = 1,
  928   ORI_IMM8_OPCODE_X0 = 7,
  929   ORI_IMM8_OPCODE_X1 = 24,
  930   OR_RRR_0_OPCODE_X0 = 65,
  931   OR_RRR_0_OPCODE_X1 = 29,
  932   OR_RRR_5_OPCODE_Y0 = 2,
  933   OR_RRR_5_OPCODE_Y1 = 2,
  934   PCNT_UNARY_OPCODE_X0 = 6,
  935   PCNT_UNARY_OPCODE_Y0 = 6,
  936   REVBITS_UNARY_OPCODE_X0 = 7,
  937   REVBITS_UNARY_OPCODE_Y0 = 7,
  938   REVBYTES_UNARY_OPCODE_X0 = 8,
  939   REVBYTES_UNARY_OPCODE_Y0 = 8,
  940   ROTLI_SHIFT_OPCODE_X0 = 1,
  941   ROTLI_SHIFT_OPCODE_X1 = 1,
  942   ROTLI_SHIFT_OPCODE_Y0 = 0,
  943   ROTLI_SHIFT_OPCODE_Y1 = 0,
  944   ROTL_RRR_0_OPCODE_X0 = 66,
  945   ROTL_RRR_0_OPCODE_X1 = 30,
  946   ROTL_RRR_6_OPCODE_Y0 = 0,
  947   ROTL_RRR_6_OPCODE_Y1 = 0,
  948   RRR_0_OPCODE_X0 = 5,
  949   RRR_0_OPCODE_X1 = 5,
  950   RRR_0_OPCODE_Y0 = 5,
  951   RRR_0_OPCODE_Y1 = 6,
  952   RRR_1_OPCODE_Y0 = 6,
  953   RRR_1_OPCODE_Y1 = 7,
  954   RRR_2_OPCODE_Y0 = 7,
  955   RRR_2_OPCODE_Y1 = 8,
  956   RRR_3_OPCODE_Y0 = 8,
  957   RRR_3_OPCODE_Y1 = 9,
  958   RRR_4_OPCODE_Y0 = 9,
  959   RRR_4_OPCODE_Y1 = 10,
  960   RRR_5_OPCODE_Y0 = 10,
  961   RRR_5_OPCODE_Y1 = 11,
  962   RRR_6_OPCODE_Y0 = 11,
  963   RRR_6_OPCODE_Y1 = 12,
  964   RRR_7_OPCODE_Y0 = 12,
  965   RRR_7_OPCODE_Y1 = 13,
  966   RRR_8_OPCODE_Y0 = 13,
  967   RRR_9_OPCODE_Y0 = 14,
  968   SHIFT_OPCODE_X0 = 6,
  969   SHIFT_OPCODE_X1 = 6,
  970   SHIFT_OPCODE_Y0 = 15,
  971   SHIFT_OPCODE_Y1 = 14,
  972   SHL16INSLI_OPCODE_X0 = 7,
  973   SHL16INSLI_OPCODE_X1 = 7,
  974   SHL1ADDX_RRR_0_OPCODE_X0 = 67,
  975   SHL1ADDX_RRR_0_OPCODE_X1 = 31,
  976   SHL1ADDX_RRR_7_OPCODE_Y0 = 1,
  977   SHL1ADDX_RRR_7_OPCODE_Y1 = 1,
  978   SHL1ADD_RRR_0_OPCODE_X0 = 68,
  979   SHL1ADD_RRR_0_OPCODE_X1 = 32,
  980   SHL1ADD_RRR_1_OPCODE_Y0 = 0,
  981   SHL1ADD_RRR_1_OPCODE_Y1 = 0,
  982   SHL2ADDX_RRR_0_OPCODE_X0 = 69,
  983   SHL2ADDX_RRR_0_OPCODE_X1 = 33,
  984   SHL2ADDX_RRR_7_OPCODE_Y0 = 2,
  985   SHL2ADDX_RRR_7_OPCODE_Y1 = 2,
  986   SHL2ADD_RRR_0_OPCODE_X0 = 70,
  987   SHL2ADD_RRR_0_OPCODE_X1 = 34,
  988   SHL2ADD_RRR_1_OPCODE_Y0 = 1,
  989   SHL2ADD_RRR_1_OPCODE_Y1 = 1,
  990   SHL3ADDX_RRR_0_OPCODE_X0 = 71,
  991   SHL3ADDX_RRR_0_OPCODE_X1 = 35,
  992   SHL3ADDX_RRR_7_OPCODE_Y0 = 3,
  993   SHL3ADDX_RRR_7_OPCODE_Y1 = 3,
  994   SHL3ADD_RRR_0_OPCODE_X0 = 72,
  995   SHL3ADD_RRR_0_OPCODE_X1 = 36,
  996   SHL3ADD_RRR_1_OPCODE_Y0 = 2,
  997   SHL3ADD_RRR_1_OPCODE_Y1 = 2,
  998   SHLI_SHIFT_OPCODE_X0 = 2,
  999   SHLI_SHIFT_OPCODE_X1 = 2,
 1000   SHLI_SHIFT_OPCODE_Y0 = 1,
 1001   SHLI_SHIFT_OPCODE_Y1 = 1,
 1002   SHLXI_SHIFT_OPCODE_X0 = 3,
 1003   SHLXI_SHIFT_OPCODE_X1 = 3,
 1004   SHLX_RRR_0_OPCODE_X0 = 73,
 1005   SHLX_RRR_0_OPCODE_X1 = 37,
 1006   SHL_RRR_0_OPCODE_X0 = 74,
 1007   SHL_RRR_0_OPCODE_X1 = 38,
 1008   SHL_RRR_6_OPCODE_Y0 = 1,
 1009   SHL_RRR_6_OPCODE_Y1 = 1,
 1010   SHRSI_SHIFT_OPCODE_X0 = 4,
 1011   SHRSI_SHIFT_OPCODE_X1 = 4,
 1012   SHRSI_SHIFT_OPCODE_Y0 = 2,
 1013   SHRSI_SHIFT_OPCODE_Y1 = 2,
 1014   SHRS_RRR_0_OPCODE_X0 = 75,
 1015   SHRS_RRR_0_OPCODE_X1 = 39,
 1016   SHRS_RRR_6_OPCODE_Y0 = 2,
 1017   SHRS_RRR_6_OPCODE_Y1 = 2,
 1018   SHRUI_SHIFT_OPCODE_X0 = 5,
 1019   SHRUI_SHIFT_OPCODE_X1 = 5,
 1020   SHRUI_SHIFT_OPCODE_Y0 = 3,
 1021   SHRUI_SHIFT_OPCODE_Y1 = 3,
 1022   SHRUXI_SHIFT_OPCODE_X0 = 6,
 1023   SHRUXI_SHIFT_OPCODE_X1 = 6,
 1024   SHRUX_RRR_0_OPCODE_X0 = 76,
 1025   SHRUX_RRR_0_OPCODE_X1 = 40,
 1026   SHRU_RRR_0_OPCODE_X0 = 77,
 1027   SHRU_RRR_0_OPCODE_X1 = 41,
 1028   SHRU_RRR_6_OPCODE_Y0 = 3,
 1029   SHRU_RRR_6_OPCODE_Y1 = 3,
 1030   SHUFFLEBYTES_RRR_0_OPCODE_X0 = 78,
 1031   ST1_ADD_IMM8_OPCODE_X1 = 25,
 1032   ST1_OPCODE_Y2 = 0,
 1033   ST1_RRR_0_OPCODE_X1 = 42,
 1034   ST2_ADD_IMM8_OPCODE_X1 = 26,
 1035   ST2_OPCODE_Y2 = 1,
 1036   ST2_RRR_0_OPCODE_X1 = 43,
 1037   ST4_ADD_IMM8_OPCODE_X1 = 27,
 1038   ST4_OPCODE_Y2 = 2,
 1039   ST4_RRR_0_OPCODE_X1 = 44,
 1040   STNT1_ADD_IMM8_OPCODE_X1 = 28,
 1041   STNT1_RRR_0_OPCODE_X1 = 45,
 1042   STNT2_ADD_IMM8_OPCODE_X1 = 29,
 1043   STNT2_RRR_0_OPCODE_X1 = 46,
 1044   STNT4_ADD_IMM8_OPCODE_X1 = 30,
 1045   STNT4_RRR_0_OPCODE_X1 = 47,
 1046   STNT_ADD_IMM8_OPCODE_X1 = 31,
 1047   STNT_RRR_0_OPCODE_X1 = 48,
 1048   ST_ADD_IMM8_OPCODE_X1 = 32,
 1049   ST_OPCODE_Y2 = 3,
 1050   ST_RRR_0_OPCODE_X1 = 49,
 1051   SUBXSC_RRR_0_OPCODE_X0 = 79,
 1052   SUBXSC_RRR_0_OPCODE_X1 = 50,
 1053   SUBX_RRR_0_OPCODE_X0 = 80,
 1054   SUBX_RRR_0_OPCODE_X1 = 51,
 1055   SUBX_RRR_0_OPCODE_Y0 = 2,
 1056   SUBX_RRR_0_OPCODE_Y1 = 2,
 1057   SUB_RRR_0_OPCODE_X0 = 81,
 1058   SUB_RRR_0_OPCODE_X1 = 52,
 1059   SUB_RRR_0_OPCODE_Y0 = 3,
 1060   SUB_RRR_0_OPCODE_Y1 = 3,
 1061   SWINT0_UNARY_OPCODE_X1 = 34,
 1062   SWINT1_UNARY_OPCODE_X1 = 35,
 1063   SWINT2_UNARY_OPCODE_X1 = 36,
 1064   SWINT3_UNARY_OPCODE_X1 = 37,
 1065   TBLIDXB0_UNARY_OPCODE_X0 = 9,
 1066   TBLIDXB0_UNARY_OPCODE_Y0 = 9,
 1067   TBLIDXB1_UNARY_OPCODE_X0 = 10,
 1068   TBLIDXB1_UNARY_OPCODE_Y0 = 10,
 1069   TBLIDXB2_UNARY_OPCODE_X0 = 11,
 1070   TBLIDXB2_UNARY_OPCODE_Y0 = 11,
 1071   TBLIDXB3_UNARY_OPCODE_X0 = 12,
 1072   TBLIDXB3_UNARY_OPCODE_Y0 = 12,
 1073   UNARY_RRR_0_OPCODE_X0 = 82,
 1074   UNARY_RRR_0_OPCODE_X1 = 53,
 1075   UNARY_RRR_1_OPCODE_Y0 = 3,
 1076   UNARY_RRR_1_OPCODE_Y1 = 3,
 1077   V1ADDI_IMM8_OPCODE_X0 = 8,
 1078   V1ADDI_IMM8_OPCODE_X1 = 33,
 1079   V1ADDUC_RRR_0_OPCODE_X0 = 83,
 1080   V1ADDUC_RRR_0_OPCODE_X1 = 54,
 1081   V1ADD_RRR_0_OPCODE_X0 = 84,
 1082   V1ADD_RRR_0_OPCODE_X1 = 55,
 1083   V1ADIFFU_RRR_0_OPCODE_X0 = 85,
 1084   V1AVGU_RRR_0_OPCODE_X0 = 86,
 1085   V1CMPEQI_IMM8_OPCODE_X0 = 9,
 1086   V1CMPEQI_IMM8_OPCODE_X1 = 34,
 1087   V1CMPEQ_RRR_0_OPCODE_X0 = 87,
 1088   V1CMPEQ_RRR_0_OPCODE_X1 = 56,
 1089   V1CMPLES_RRR_0_OPCODE_X0 = 88,
 1090   V1CMPLES_RRR_0_OPCODE_X1 = 57,
 1091   V1CMPLEU_RRR_0_OPCODE_X0 = 89,
 1092   V1CMPLEU_RRR_0_OPCODE_X1 = 58,
 1093   V1CMPLTSI_IMM8_OPCODE_X0 = 10,
 1094   V1CMPLTSI_IMM8_OPCODE_X1 = 35,
 1095   V1CMPLTS_RRR_0_OPCODE_X0 = 90,
 1096   V1CMPLTS_RRR_0_OPCODE_X1 = 59,
 1097   V1CMPLTUI_IMM8_OPCODE_X0 = 11,
 1098   V1CMPLTUI_IMM8_OPCODE_X1 = 36,
 1099   V1CMPLTU_RRR_0_OPCODE_X0 = 91,
 1100   V1CMPLTU_RRR_0_OPCODE_X1 = 60,
 1101   V1CMPNE_RRR_0_OPCODE_X0 = 92,
 1102   V1CMPNE_RRR_0_OPCODE_X1 = 61,
 1103   V1DDOTPUA_RRR_0_OPCODE_X0 = 161,
 1104   V1DDOTPUSA_RRR_0_OPCODE_X0 = 93,
 1105   V1DDOTPUS_RRR_0_OPCODE_X0 = 94,
 1106   V1DDOTPU_RRR_0_OPCODE_X0 = 162,
 1107   V1DOTPA_RRR_0_OPCODE_X0 = 95,
 1108   V1DOTPUA_RRR_0_OPCODE_X0 = 163,
 1109   V1DOTPUSA_RRR_0_OPCODE_X0 = 96,
 1110   V1DOTPUS_RRR_0_OPCODE_X0 = 97,
 1111   V1DOTPU_RRR_0_OPCODE_X0 = 164,
 1112   V1DOTP_RRR_0_OPCODE_X0 = 98,
 1113   V1INT_H_RRR_0_OPCODE_X0 = 99,
 1114   V1INT_H_RRR_0_OPCODE_X1 = 62,
 1115   V1INT_L_RRR_0_OPCODE_X0 = 100,
 1116   V1INT_L_RRR_0_OPCODE_X1 = 63,
 1117   V1MAXUI_IMM8_OPCODE_X0 = 12,
 1118   V1MAXUI_IMM8_OPCODE_X1 = 37,
 1119   V1MAXU_RRR_0_OPCODE_X0 = 101,
 1120   V1MAXU_RRR_0_OPCODE_X1 = 64,
 1121   V1MINUI_IMM8_OPCODE_X0 = 13,
 1122   V1MINUI_IMM8_OPCODE_X1 = 38,
 1123   V1MINU_RRR_0_OPCODE_X0 = 102,
 1124   V1MINU_RRR_0_OPCODE_X1 = 65,
 1125   V1MNZ_RRR_0_OPCODE_X0 = 103,
 1126   V1MNZ_RRR_0_OPCODE_X1 = 66,
 1127   V1MULTU_RRR_0_OPCODE_X0 = 104,
 1128   V1MULUS_RRR_0_OPCODE_X0 = 105,
 1129   V1MULU_RRR_0_OPCODE_X0 = 106,
 1130   V1MZ_RRR_0_OPCODE_X0 = 107,
 1131   V1MZ_RRR_0_OPCODE_X1 = 67,
 1132   V1SADAU_RRR_0_OPCODE_X0 = 108,
 1133   V1SADU_RRR_0_OPCODE_X0 = 109,
 1134   V1SHLI_SHIFT_OPCODE_X0 = 7,
 1135   V1SHLI_SHIFT_OPCODE_X1 = 7,
 1136   V1SHL_RRR_0_OPCODE_X0 = 110,
 1137   V1SHL_RRR_0_OPCODE_X1 = 68,
 1138   V1SHRSI_SHIFT_OPCODE_X0 = 8,
 1139   V1SHRSI_SHIFT_OPCODE_X1 = 8,
 1140   V1SHRS_RRR_0_OPCODE_X0 = 111,
 1141   V1SHRS_RRR_0_OPCODE_X1 = 69,
 1142   V1SHRUI_SHIFT_OPCODE_X0 = 9,
 1143   V1SHRUI_SHIFT_OPCODE_X1 = 9,
 1144   V1SHRU_RRR_0_OPCODE_X0 = 112,
 1145   V1SHRU_RRR_0_OPCODE_X1 = 70,
 1146   V1SUBUC_RRR_0_OPCODE_X0 = 113,
 1147   V1SUBUC_RRR_0_OPCODE_X1 = 71,
 1148   V1SUB_RRR_0_OPCODE_X0 = 114,
 1149   V1SUB_RRR_0_OPCODE_X1 = 72,
 1150   V2ADDI_IMM8_OPCODE_X0 = 14,
 1151   V2ADDI_IMM8_OPCODE_X1 = 39,
 1152   V2ADDSC_RRR_0_OPCODE_X0 = 115,
 1153   V2ADDSC_RRR_0_OPCODE_X1 = 73,
 1154   V2ADD_RRR_0_OPCODE_X0 = 116,
 1155   V2ADD_RRR_0_OPCODE_X1 = 74,
 1156   V2ADIFFS_RRR_0_OPCODE_X0 = 117,
 1157   V2AVGS_RRR_0_OPCODE_X0 = 118,
 1158   V2CMPEQI_IMM8_OPCODE_X0 = 15,
 1159   V2CMPEQI_IMM8_OPCODE_X1 = 40,
 1160   V2CMPEQ_RRR_0_OPCODE_X0 = 119,
 1161   V2CMPEQ_RRR_0_OPCODE_X1 = 75,
 1162   V2CMPLES_RRR_0_OPCODE_X0 = 120,
 1163   V2CMPLES_RRR_0_OPCODE_X1 = 76,
 1164   V2CMPLEU_RRR_0_OPCODE_X0 = 121,
 1165   V2CMPLEU_RRR_0_OPCODE_X1 = 77,
 1166   V2CMPLTSI_IMM8_OPCODE_X0 = 16,
 1167   V2CMPLTSI_IMM8_OPCODE_X1 = 41,
 1168   V2CMPLTS_RRR_0_OPCODE_X0 = 122,
 1169   V2CMPLTS_RRR_0_OPCODE_X1 = 78,
 1170   V2CMPLTUI_IMM8_OPCODE_X0 = 17,
 1171   V2CMPLTUI_IMM8_OPCODE_X1 = 42,
 1172   V2CMPLTU_RRR_0_OPCODE_X0 = 123,
 1173   V2CMPLTU_RRR_0_OPCODE_X1 = 79,
 1174   V2CMPNE_RRR_0_OPCODE_X0 = 124,
 1175   V2CMPNE_RRR_0_OPCODE_X1 = 80,
 1176   V2DOTPA_RRR_0_OPCODE_X0 = 125,
 1177   V2DOTP_RRR_0_OPCODE_X0 = 126,
 1178   V2INT_H_RRR_0_OPCODE_X0 = 127,
 1179   V2INT_H_RRR_0_OPCODE_X1 = 81,
 1180   V2INT_L_RRR_0_OPCODE_X0 = 128,
 1181   V2INT_L_RRR_0_OPCODE_X1 = 82,
 1182   V2MAXSI_IMM8_OPCODE_X0 = 18,
 1183   V2MAXSI_IMM8_OPCODE_X1 = 43,
 1184   V2MAXS_RRR_0_OPCODE_X0 = 129,
 1185   V2MAXS_RRR_0_OPCODE_X1 = 83,
 1186   V2MINSI_IMM8_OPCODE_X0 = 19,
 1187   V2MINSI_IMM8_OPCODE_X1 = 44,
 1188   V2MINS_RRR_0_OPCODE_X0 = 130,
 1189   V2MINS_RRR_0_OPCODE_X1 = 84,
 1190   V2MNZ_RRR_0_OPCODE_X0 = 131,
 1191   V2MNZ_RRR_0_OPCODE_X1 = 85,
 1192   V2MULFSC_RRR_0_OPCODE_X0 = 132,
 1193   V2MULS_RRR_0_OPCODE_X0 = 133,
 1194   V2MULTS_RRR_0_OPCODE_X0 = 134,
 1195   V2MZ_RRR_0_OPCODE_X0 = 135,
 1196   V2MZ_RRR_0_OPCODE_X1 = 86,
 1197   V2PACKH_RRR_0_OPCODE_X0 = 136,
 1198   V2PACKH_RRR_0_OPCODE_X1 = 87,
 1199   V2PACKL_RRR_0_OPCODE_X0 = 137,
 1200   V2PACKL_RRR_0_OPCODE_X1 = 88,
 1201   V2PACKUC_RRR_0_OPCODE_X0 = 138,
 1202   V2PACKUC_RRR_0_OPCODE_X1 = 89,
 1203   V2SADAS_RRR_0_OPCODE_X0 = 139,
 1204   V2SADAU_RRR_0_OPCODE_X0 = 140,
 1205   V2SADS_RRR_0_OPCODE_X0 = 141,
 1206   V2SADU_RRR_0_OPCODE_X0 = 142,
 1207   V2SHLI_SHIFT_OPCODE_X0 = 10,
 1208   V2SHLI_SHIFT_OPCODE_X1 = 10,
 1209   V2SHLSC_RRR_0_OPCODE_X0 = 143,
 1210   V2SHLSC_RRR_0_OPCODE_X1 = 90,
 1211   V2SHL_RRR_0_OPCODE_X0 = 144,
 1212   V2SHL_RRR_0_OPCODE_X1 = 91,
 1213   V2SHRSI_SHIFT_OPCODE_X0 = 11,
 1214   V2SHRSI_SHIFT_OPCODE_X1 = 11,
 1215   V2SHRS_RRR_0_OPCODE_X0 = 145,
 1216   V2SHRS_RRR_0_OPCODE_X1 = 92,
 1217   V2SHRUI_SHIFT_OPCODE_X0 = 12,
 1218   V2SHRUI_SHIFT_OPCODE_X1 = 12,
 1219   V2SHRU_RRR_0_OPCODE_X0 = 146,
 1220   V2SHRU_RRR_0_OPCODE_X1 = 93,
 1221   V2SUBSC_RRR_0_OPCODE_X0 = 147,
 1222   V2SUBSC_RRR_0_OPCODE_X1 = 94,
 1223   V2SUB_RRR_0_OPCODE_X0 = 148,
 1224   V2SUB_RRR_0_OPCODE_X1 = 95,
 1225   V4ADDSC_RRR_0_OPCODE_X0 = 149,
 1226   V4ADDSC_RRR_0_OPCODE_X1 = 96,
 1227   V4ADD_RRR_0_OPCODE_X0 = 150,
 1228   V4ADD_RRR_0_OPCODE_X1 = 97,
 1229   V4INT_H_RRR_0_OPCODE_X0 = 151,
 1230   V4INT_H_RRR_0_OPCODE_X1 = 98,
 1231   V4INT_L_RRR_0_OPCODE_X0 = 152,
 1232   V4INT_L_RRR_0_OPCODE_X1 = 99,
 1233   V4PACKSC_RRR_0_OPCODE_X0 = 153,
 1234   V4PACKSC_RRR_0_OPCODE_X1 = 100,
 1235   V4SHLSC_RRR_0_OPCODE_X0 = 154,
 1236   V4SHLSC_RRR_0_OPCODE_X1 = 101,
 1237   V4SHL_RRR_0_OPCODE_X0 = 155,
 1238   V4SHL_RRR_0_OPCODE_X1 = 102,
 1239   V4SHRS_RRR_0_OPCODE_X0 = 156,
 1240   V4SHRS_RRR_0_OPCODE_X1 = 103,
 1241   V4SHRU_RRR_0_OPCODE_X0 = 157,
 1242   V4SHRU_RRR_0_OPCODE_X1 = 104,
 1243   V4SUBSC_RRR_0_OPCODE_X0 = 158,
 1244   V4SUBSC_RRR_0_OPCODE_X1 = 105,
 1245   V4SUB_RRR_0_OPCODE_X0 = 159,
 1246   V4SUB_RRR_0_OPCODE_X1 = 106,
 1247   WH64_UNARY_OPCODE_X1 = 38,
 1248   XORI_IMM8_OPCODE_X0 = 20,
 1249   XORI_IMM8_OPCODE_X1 = 45,
 1250   XOR_RRR_0_OPCODE_X0 = 160,
 1251   XOR_RRR_0_OPCODE_X1 = 107,
 1252   XOR_RRR_5_OPCODE_Y0 = 3,
 1253   XOR_RRR_5_OPCODE_Y1 = 3
 1254 };
 1255 
 1256 static __inline unsigned int
 1257 get_BFEnd_X0(tilegx_bundle_bits num)
 1258 {
 1259   const unsigned int n = (unsigned int)num;
 1260   return (((n >> 12)) & 0x3f);
 1261 }
 1262 
 1263 static __inline unsigned int
 1264 get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
 1265 {
 1266   const unsigned int n = (unsigned int)num;
 1267   return (((n >> 24)) & 0xf);
 1268 }
 1269 
 1270 static __inline unsigned int
 1271 get_BFStart_X0(tilegx_bundle_bits num)
 1272 {
 1273   const unsigned int n = (unsigned int)num;
 1274   return (((n >> 18)) & 0x3f);
 1275 }
 1276 
 1277 static __inline unsigned int
 1278 get_BrOff_X1(tilegx_bundle_bits n)
 1279 {
 1280   return (((unsigned int)(n >> 31)) & 0x0000003f) |
 1281          (((unsigned int)(n >> 37)) & 0x0001ffc0);
 1282 }
 1283 
 1284 static __inline unsigned int
 1285 get_BrType_X1(tilegx_bundle_bits n)
 1286 {
 1287   return (((unsigned int)(n >> 54)) & 0x1f);
 1288 }
 1289 
 1290 static __inline unsigned int
 1291 get_Dest_Imm8_X1(tilegx_bundle_bits n)
 1292 {
 1293   return (((unsigned int)(n >> 31)) & 0x0000003f) |
 1294          (((unsigned int)(n >> 43)) & 0x000000c0);
 1295 }
 1296 
 1297 static __inline unsigned int
 1298 get_Dest_X0(tilegx_bundle_bits num)
 1299 {
 1300   const unsigned int n = (unsigned int)num;
 1301   return (((n >> 0)) & 0x3f);
 1302 }
 1303 
 1304 static __inline unsigned int
 1305 get_Dest_X1(tilegx_bundle_bits n)
 1306 {
 1307   return (((unsigned int)(n >> 31)) & 0x3f);
 1308 }
 1309 
 1310 static __inline unsigned int
 1311 get_Dest_Y0(tilegx_bundle_bits num)
 1312 {
 1313   const unsigned int n = (unsigned int)num;
 1314   return (((n >> 0)) & 0x3f);
 1315 }
 1316 
 1317 static __inline unsigned int
 1318 get_Dest_Y1(tilegx_bundle_bits n)
 1319 {
 1320   return (((unsigned int)(n >> 31)) & 0x3f);
 1321 }
 1322 
 1323 static __inline unsigned int
 1324 get_Imm16_X0(tilegx_bundle_bits num)
 1325 {
 1326   const unsigned int n = (unsigned int)num;
 1327   return (((n >> 12)) & 0xffff);
 1328 }
 1329 
 1330 static __inline unsigned int
 1331 get_Imm16_X1(tilegx_bundle_bits n)
 1332 {
 1333   return (((unsigned int)(n >> 43)) & 0xffff);
 1334 }
 1335 
 1336 static __inline unsigned int
 1337 get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
 1338 {
 1339   const unsigned int n = (unsigned int)num;
 1340   return (((n >> 20)) & 0xff);
 1341 }
 1342 
 1343 static __inline unsigned int
 1344 get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
 1345 {
 1346   return (((unsigned int)(n >> 51)) & 0xff);
 1347 }
 1348 
 1349 static __inline unsigned int
 1350 get_Imm8_X0(tilegx_bundle_bits num)
 1351 {
 1352   const unsigned int n = (unsigned int)num;
 1353   return (((n >> 12)) & 0xff);
 1354 }
 1355 
 1356 static __inline unsigned int
 1357 get_Imm8_X1(tilegx_bundle_bits n)
 1358 {
 1359   return (((unsigned int)(n >> 43)) & 0xff);
 1360 }
 1361 
 1362 static __inline unsigned int
 1363 get_Imm8_Y0(tilegx_bundle_bits num)
 1364 {
 1365   const unsigned int n = (unsigned int)num;
 1366   return (((n >> 12)) & 0xff);
 1367 }
 1368 
 1369 static __inline unsigned int
 1370 get_Imm8_Y1(tilegx_bundle_bits n)
 1371 {
 1372   return (((unsigned int)(n >> 43)) & 0xff);
 1373 }
 1374 
 1375 static __inline unsigned int
 1376 get_JumpOff_X1(tilegx_bundle_bits n)
 1377 {
 1378   return (((unsigned int)(n >> 31)) & 0x7ffffff);
 1379 }
 1380 
 1381 static __inline unsigned int
 1382 get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
 1383 {
 1384   return (((unsigned int)(n >> 58)) & 0x1);
 1385 }
 1386 
 1387 static __inline unsigned int
 1388 get_MF_Imm14_X1(tilegx_bundle_bits n)
 1389 {
 1390   return (((unsigned int)(n >> 37)) & 0x3fff);
 1391 }
 1392 
 1393 static __inline unsigned int
 1394 get_MT_Imm14_X1(tilegx_bundle_bits n)
 1395 {
 1396   return (((unsigned int)(n >> 31)) & 0x0000003f) |
 1397          (((unsigned int)(n >> 37)) & 0x00003fc0);
 1398 }
 1399 
 1400 static __inline unsigned int
 1401 get_Mode(tilegx_bundle_bits n)
 1402 {
 1403   return (((unsigned int)(n >> 62)) & 0x3);
 1404 }
 1405 
 1406 static __inline unsigned int
 1407 get_Opcode_X0(tilegx_bundle_bits num)
 1408 {
 1409   const unsigned int n = (unsigned int)num;
 1410   return (((n >> 28)) & 0x7);
 1411 }
 1412 
 1413 static __inline unsigned int
 1414 get_Opcode_X1(tilegx_bundle_bits n)
 1415 {
 1416   return (((unsigned int)(n >> 59)) & 0x7);
 1417 }
 1418 
 1419 static __inline unsigned int
 1420 get_Opcode_Y0(tilegx_bundle_bits num)
 1421 {
 1422   const unsigned int n = (unsigned int)num;
 1423   return (((n >> 27)) & 0xf);
 1424 }
 1425 
 1426 static __inline unsigned int
 1427 get_Opcode_Y1(tilegx_bundle_bits n)
 1428 {
 1429   return (((unsigned int)(n >> 58)) & 0xf);
 1430 }
 1431 
 1432 static __inline unsigned int
 1433 get_Opcode_Y2(tilegx_bundle_bits n)
 1434 {
 1435   return (((n >> 26)) & 0x00000001) |
 1436          (((unsigned int)(n >> 56)) & 0x00000002);
 1437 }
 1438 
 1439 static __inline unsigned int
 1440 get_RRROpcodeExtension_X0(tilegx_bundle_bits num)
 1441 {
 1442   const unsigned int n = (unsigned int)num;
 1443   return (((n >> 18)) & 0x3ff);
 1444 }
 1445 
 1446 static __inline unsigned int
 1447 get_RRROpcodeExtension_X1(tilegx_bundle_bits n)
 1448 {
 1449   return (((unsigned int)(n >> 49)) & 0x3ff);
 1450 }
 1451 
 1452 static __inline unsigned int
 1453 get_RRROpcodeExtension_Y0(tilegx_bundle_bits num)
 1454 {
 1455   const unsigned int n = (unsigned int)num;
 1456   return (((n >> 18)) & 0x3);
 1457 }
 1458 
 1459 static __inline unsigned int
 1460 get_RRROpcodeExtension_Y1(tilegx_bundle_bits n)
 1461 {
 1462   return (((unsigned int)(n >> 49)) & 0x3);
 1463 }
 1464 
 1465 static __inline unsigned int
 1466 get_ShAmt_X0(tilegx_bundle_bits num)
 1467 {
 1468   const unsigned int n = (unsigned int)num;
 1469   return (((n >> 12)) & 0x3f);
 1470 }
 1471 
 1472 static __inline unsigned int
 1473 get_ShAmt_X1(tilegx_bundle_bits n)
 1474 {
 1475   return (((unsigned int)(n >> 43)) & 0x3f);
 1476 }
 1477 
 1478 static __inline unsigned int
 1479 get_ShAmt_Y0(tilegx_bundle_bits num)
 1480 {
 1481   const unsigned int n = (unsigned int)num;
 1482   return (((n >> 12)) & 0x3f);
 1483 }
 1484 
 1485 static __inline unsigned int
 1486 get_ShAmt_Y1(tilegx_bundle_bits n)
 1487 {
 1488   return (((unsigned int)(n >> 43)) & 0x3f);
 1489 }
 1490 
 1491 static __inline unsigned int
 1492 get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num)
 1493 {
 1494   const unsigned int n = (unsigned int)num;
 1495   return (((n >> 18)) & 0x3ff);
 1496 }
 1497 
 1498 static __inline unsigned int
 1499 get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n)
 1500 {
 1501   return (((unsigned int)(n >> 49)) & 0x3ff);
 1502 }
 1503 
 1504 static __inline unsigned int
 1505 get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num)
 1506 {
 1507   const unsigned int n = (unsigned int)num;
 1508   return (((n >> 18)) & 0x3);
 1509 }
 1510 
 1511 static __inline unsigned int
 1512 get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n)
 1513 {
 1514   return (((unsigned int)(n >> 49)) & 0x3);
 1515 }
 1516 
 1517 static __inline unsigned int
 1518 get_SrcA_X0(tilegx_bundle_bits num)
 1519 {
 1520   const unsigned int n = (unsigned int)num;
 1521   return (((n >> 6)) & 0x3f);
 1522 }
 1523 
 1524 static __inline unsigned int
 1525 get_SrcA_X1(tilegx_bundle_bits n)
 1526 {
 1527   return (((unsigned int)(n >> 37)) & 0x3f);
 1528 }
 1529 
 1530 static __inline unsigned int
 1531 get_SrcA_Y0(tilegx_bundle_bits num)
 1532 {
 1533   const unsigned int n = (unsigned int)num;
 1534   return (((n >> 6)) & 0x3f);
 1535 }
 1536 
 1537 static __inline unsigned int
 1538 get_SrcA_Y1(tilegx_bundle_bits n)
 1539 {
 1540   return (((unsigned int)(n >> 37)) & 0x3f);
 1541 }
 1542 
 1543 static __inline unsigned int
 1544 get_SrcA_Y2(tilegx_bundle_bits num)
 1545 {
 1546   const unsigned int n = (unsigned int)num;
 1547   return (((n >> 20)) & 0x3f);
 1548 }
 1549 
 1550 static __inline unsigned int
 1551 get_SrcBDest_Y2(tilegx_bundle_bits n)
 1552 {
 1553   return (((unsigned int)(n >> 51)) & 0x3f);
 1554 }
 1555 
 1556 static __inline unsigned int
 1557 get_SrcB_X0(tilegx_bundle_bits num)
 1558 {
 1559   const unsigned int n = (unsigned int)num;
 1560   return (((n >> 12)) & 0x3f);
 1561 }
 1562 
 1563 static __inline unsigned int
 1564 get_SrcB_X1(tilegx_bundle_bits n)
 1565 {
 1566   return (((unsigned int)(n >> 43)) & 0x3f);
 1567 }
 1568 
 1569 static __inline unsigned int
 1570 get_SrcB_Y0(tilegx_bundle_bits num)
 1571 {
 1572   const unsigned int n = (unsigned int)num;
 1573   return (((n >> 12)) & 0x3f);
 1574 }
 1575 
 1576 static __inline unsigned int
 1577 get_SrcB_Y1(tilegx_bundle_bits n)
 1578 {
 1579   return (((unsigned int)(n >> 43)) & 0x3f);
 1580 }
 1581 
 1582 static __inline unsigned int
 1583 get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num)
 1584 {
 1585   const unsigned int n = (unsigned int)num;
 1586   return (((n >> 12)) & 0x3f);
 1587 }
 1588 
 1589 static __inline unsigned int
 1590 get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n)
 1591 {
 1592   return (((unsigned int)(n >> 43)) & 0x3f);
 1593 }
 1594 
 1595 static __inline unsigned int
 1596 get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num)
 1597 {
 1598   const unsigned int n = (unsigned int)num;
 1599   return (((n >> 12)) & 0x3f);
 1600 }
 1601 
 1602 static __inline unsigned int
 1603 get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n)
 1604 {
 1605   return (((unsigned int)(n >> 43)) & 0x3f);
 1606 }
 1607 
 1608 static __inline int
 1609 sign_extend(int n, int num_bits)
 1610 {
 1611   int shift = (int)(sizeof(int) * 8 - num_bits);
 1612   return (n << shift) >> shift;
 1613 }
 1614 
 1615 static __inline tilegx_bundle_bits
 1616 create_BFEnd_X0(int num)
 1617 {
 1618   const unsigned int n = (unsigned int)num;
 1619   return ((n & 0x3f) << 12);
 1620 }
 1621 
 1622 static __inline tilegx_bundle_bits
 1623 create_BFOpcodeExtension_X0(int num)
 1624 {
 1625   const unsigned int n = (unsigned int)num;
 1626   return ((n & 0xf) << 24);
 1627 }
 1628 
 1629 static __inline tilegx_bundle_bits
 1630 create_BFStart_X0(int num)
 1631 {
 1632   const unsigned int n = (unsigned int)num;
 1633   return ((n & 0x3f) << 18);
 1634 }
 1635 
 1636 static __inline tilegx_bundle_bits
 1637 create_BrOff_X1(int num)
 1638 {
 1639   const unsigned int n = (unsigned int)num;
 1640   return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
 1641          (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37);
 1642 }
 1643 
 1644 static __inline tilegx_bundle_bits
 1645 create_BrType_X1(int num)
 1646 {
 1647   const unsigned int n = (unsigned int)num;
 1648   return (((tilegx_bundle_bits)(n & 0x1f)) << 54);
 1649 }
 1650 
 1651 static __inline tilegx_bundle_bits
 1652 create_Dest_Imm8_X1(int num)
 1653 {
 1654   const unsigned int n = (unsigned int)num;
 1655   return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
 1656          (((tilegx_bundle_bits)(n & 0x000000c0)) << 43);
 1657 }
 1658 
 1659 static __inline tilegx_bundle_bits
 1660 create_Dest_X0(int num)
 1661 {
 1662   const unsigned int n = (unsigned int)num;
 1663   return ((n & 0x3f) << 0);
 1664 }
 1665 
 1666 static __inline tilegx_bundle_bits
 1667 create_Dest_X1(int num)
 1668 {
 1669   const unsigned int n = (unsigned int)num;
 1670   return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
 1671 }
 1672 
 1673 static __inline tilegx_bundle_bits
 1674 create_Dest_Y0(int num)
 1675 {
 1676   const unsigned int n = (unsigned int)num;
 1677   return ((n & 0x3f) << 0);
 1678 }
 1679 
 1680 static __inline tilegx_bundle_bits
 1681 create_Dest_Y1(int num)
 1682 {
 1683   const unsigned int n = (unsigned int)num;
 1684   return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
 1685 }
 1686 
 1687 static __inline tilegx_bundle_bits
 1688 create_Imm16_X0(int num)
 1689 {
 1690   const unsigned int n = (unsigned int)num;
 1691   return ((n & 0xffff) << 12);
 1692 }
 1693 
 1694 static __inline tilegx_bundle_bits
 1695 create_Imm16_X1(int num)
 1696 {
 1697   const unsigned int n = (unsigned int)num;
 1698   return (((tilegx_bundle_bits)(n & 0xffff)) << 43);
 1699 }
 1700 
 1701 static __inline tilegx_bundle_bits
 1702 create_Imm8OpcodeExtension_X0(int num)
 1703 {
 1704   const unsigned int n = (unsigned int)num;
 1705   return ((n & 0xff) << 20);
 1706 }
 1707 
 1708 static __inline tilegx_bundle_bits
 1709 create_Imm8OpcodeExtension_X1(int num)
 1710 {
 1711   const unsigned int n = (unsigned int)num;
 1712   return (((tilegx_bundle_bits)(n & 0xff)) << 51);
 1713 }
 1714 
 1715 static __inline tilegx_bundle_bits
 1716 create_Imm8_X0(int num)
 1717 {
 1718   const unsigned int n = (unsigned int)num;
 1719   return ((n & 0xff) << 12);
 1720 }
 1721 
 1722 static __inline tilegx_bundle_bits
 1723 create_Imm8_X1(int num)
 1724 {
 1725   const unsigned int n = (unsigned int)num;
 1726   return (((tilegx_bundle_bits)(n & 0xff)) << 43);
 1727 }
 1728 
 1729 static __inline tilegx_bundle_bits
 1730 create_Imm8_Y0(int num)
 1731 {
 1732   const unsigned int n = (unsigned int)num;
 1733   return ((n & 0xff) << 12);
 1734 }
 1735 
 1736 static __inline tilegx_bundle_bits
 1737 create_Imm8_Y1(int num)
 1738 {
 1739   const unsigned int n = (unsigned int)num;
 1740   return (((tilegx_bundle_bits)(n & 0xff)) << 43);
 1741 }
 1742 
 1743 static __inline tilegx_bundle_bits
 1744 create_JumpOff_X1(int num)
 1745 {
 1746   const unsigned int n = (unsigned int)num;
 1747   return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31);
 1748 }
 1749 
 1750 static __inline tilegx_bundle_bits
 1751 create_JumpOpcodeExtension_X1(int num)
 1752 {
 1753   const unsigned int n = (unsigned int)num;
 1754   return (((tilegx_bundle_bits)(n & 0x1)) << 58);
 1755 }
 1756 
 1757 static __inline tilegx_bundle_bits
 1758 create_MF_Imm14_X1(int num)
 1759 {
 1760   const unsigned int n = (unsigned int)num;
 1761   return (((tilegx_bundle_bits)(n & 0x3fff)) << 37);
 1762 }
 1763 
 1764 static __inline tilegx_bundle_bits
 1765 create_MT_Imm14_X1(int num)
 1766 {
 1767   const unsigned int n = (unsigned int)num;
 1768   return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
 1769          (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37);
 1770 }
 1771 
 1772 static __inline tilegx_bundle_bits
 1773 create_Mode(int num)
 1774 {
 1775   const unsigned int n = (unsigned int)num;
 1776   return (((tilegx_bundle_bits)(n & 0x3)) << 62);
 1777 }
 1778 
 1779 static __inline tilegx_bundle_bits
 1780 create_Opcode_X0(int num)
 1781 {
 1782   const unsigned int n = (unsigned int)num;
 1783   return ((n & 0x7) << 28);
 1784 }
 1785 
 1786 static __inline tilegx_bundle_bits
 1787 create_Opcode_X1(int num)
 1788 {
 1789   const unsigned int n = (unsigned int)num;
 1790   return (((tilegx_bundle_bits)(n & 0x7)) << 59);
 1791 }
 1792 
 1793 static __inline tilegx_bundle_bits
 1794 create_Opcode_Y0(int num)
 1795 {
 1796   const unsigned int n = (unsigned int)num;
 1797   return ((n & 0xf) << 27);
 1798 }
 1799 
 1800 static __inline tilegx_bundle_bits
 1801 create_Opcode_Y1(int num)
 1802 {
 1803   const unsigned int n = (unsigned int)num;
 1804   return (((tilegx_bundle_bits)(n & 0xf)) << 58);
 1805 }
 1806 
 1807 static __inline tilegx_bundle_bits
 1808 create_Opcode_Y2(int num)
 1809 {
 1810   const unsigned int n = (unsigned int)num;
 1811   return ((n & 0x00000001) << 26) |
 1812          (((tilegx_bundle_bits)(n & 0x00000002)) << 56);
 1813 }
 1814 
 1815 static __inline tilegx_bundle_bits
 1816 create_RRROpcodeExtension_X0(int num)
 1817 {
 1818   const unsigned int n = (unsigned int)num;
 1819   return ((n & 0x3ff) << 18);
 1820 }
 1821 
 1822 static __inline tilegx_bundle_bits
 1823 create_RRROpcodeExtension_X1(int num)
 1824 {
 1825   const unsigned int n = (unsigned int)num;
 1826   return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
 1827 }
 1828 
 1829 static __inline tilegx_bundle_bits
 1830 create_RRROpcodeExtension_Y0(int num)
 1831 {
 1832   const unsigned int n = (unsigned int)num;
 1833   return ((n & 0x3) << 18);
 1834 }
 1835 
 1836 static __inline tilegx_bundle_bits
 1837 create_RRROpcodeExtension_Y1(int num)
 1838 {
 1839   const unsigned int n = (unsigned int)num;
 1840   return (((tilegx_bundle_bits)(n & 0x3)) << 49);
 1841 }
 1842 
 1843 static __inline tilegx_bundle_bits
 1844 create_ShAmt_X0(int num)
 1845 {
 1846   const unsigned int n = (unsigned int)num;
 1847   return ((n & 0x3f) << 12);
 1848 }
 1849 
 1850 static __inline tilegx_bundle_bits
 1851 create_ShAmt_X1(int num)
 1852 {
 1853   const unsigned int n = (unsigned int)num;
 1854   return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
 1855 }
 1856 
 1857 static __inline tilegx_bundle_bits
 1858 create_ShAmt_Y0(int num)
 1859 {
 1860   const unsigned int n = (unsigned int)num;
 1861   return ((n & 0x3f) << 12);
 1862 }
 1863 
 1864 static __inline tilegx_bundle_bits
 1865 create_ShAmt_Y1(int num)
 1866 {
 1867   const unsigned int n = (unsigned int)num;
 1868   return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
 1869 }
 1870 
 1871 static __inline tilegx_bundle_bits
 1872 create_ShiftOpcodeExtension_X0(int num)
 1873 {
 1874   const unsigned int n = (unsigned int)num;
 1875   return ((n & 0x3ff) << 18);
 1876 }
 1877 
 1878 static __inline tilegx_bundle_bits
 1879 create_ShiftOpcodeExtension_X1(int num)
 1880 {
 1881   const unsigned int n = (unsigned int)num;
 1882   return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
 1883 }
 1884 
 1885 static __inline tilegx_bundle_bits
 1886 create_ShiftOpcodeExtension_Y0(int num)
 1887 {
 1888   const unsigned int n = (unsigned int)num;
 1889   return ((n & 0x3) << 18);
 1890 }
 1891 
 1892 static __inline tilegx_bundle_bits
 1893 create_ShiftOpcodeExtension_Y1(int num)
 1894 {
 1895   const unsigned int n = (unsigned int)num;
 1896   return (((tilegx_bundle_bits)(n & 0x3)) << 49);
 1897 }
 1898 
 1899 static __inline tilegx_bundle_bits
 1900 create_SrcA_X0(int num)
 1901 {
 1902   const unsigned int n = (unsigned int)num;
 1903   return ((n & 0x3f) << 6);
 1904 }
 1905 
 1906 static __inline tilegx_bundle_bits
 1907 create_SrcA_X1(int num)
 1908 {
 1909   const unsigned int n = (unsigned int)num;
 1910   return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
 1911 }
 1912 
 1913 static __inline tilegx_bundle_bits
 1914 create_SrcA_Y0(int num)
 1915 {
 1916   const unsigned int n = (unsigned int)num;
 1917   return ((n & 0x3f) << 6);
 1918 }
 1919 
 1920 static __inline tilegx_bundle_bits
 1921 create_SrcA_Y1(int num)
 1922 {
 1923   const unsigned int n = (unsigned int)num;
 1924   return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
 1925 }
 1926 
 1927 static __inline tilegx_bundle_bits
 1928 create_SrcA_Y2(int num)
 1929 {
 1930   const unsigned int n = (unsigned int)num;
 1931   return ((n & 0x3f) << 20);
 1932 }
 1933 
 1934 static __inline tilegx_bundle_bits
 1935 create_SrcBDest_Y2(int num)
 1936 {
 1937   const unsigned int n = (unsigned int)num;
 1938   return (((tilegx_bundle_bits)(n & 0x3f)) << 51);
 1939 }
 1940 
 1941 static __inline tilegx_bundle_bits
 1942 create_SrcB_X0(int num)
 1943 {
 1944   const unsigned int n = (unsigned int)num;
 1945   return ((n & 0x3f) << 12);
 1946 }
 1947 
 1948 static __inline tilegx_bundle_bits
 1949 create_SrcB_X1(int num)
 1950 {
 1951   const unsigned int n = (unsigned int)num;
 1952   return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
 1953 }
 1954 
 1955 static __inline tilegx_bundle_bits
 1956 create_SrcB_Y0(int num)
 1957 {
 1958   const unsigned int n = (unsigned int)num;
 1959   return ((n & 0x3f) << 12);
 1960 }
 1961 
 1962 static __inline tilegx_bundle_bits
 1963 create_SrcB_Y1(int num)
 1964 {
 1965   const unsigned int n = (unsigned int)num;
 1966   return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
 1967 }
 1968 
 1969 static __inline tilegx_bundle_bits
 1970 create_UnaryOpcodeExtension_X0(int num)
 1971 {
 1972   const unsigned int n = (unsigned int)num;
 1973   return ((n & 0x3f) << 12);
 1974 }
 1975 
 1976 static __inline tilegx_bundle_bits
 1977 create_UnaryOpcodeExtension_X1(int num)
 1978 {
 1979   const unsigned int n = (unsigned int)num;
 1980   return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
 1981 }
 1982 
 1983 static __inline tilegx_bundle_bits
 1984 create_UnaryOpcodeExtension_Y0(int num)
 1985 {
 1986   const unsigned int n = (unsigned int)num;
 1987   return ((n & 0x3f) << 12);
 1988 }
 1989 
 1990 static __inline tilegx_bundle_bits
 1991 create_UnaryOpcodeExtension_Y1(int num)
 1992 {
 1993   const unsigned int n = (unsigned int)num;
 1994   return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
 1995 }
 1996 
 1997 const struct tilegx_opcode tilegx_opcodes[336] =
 1998 {
 1999  { "bpt", TILEGX_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
 2000     { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
 2001 #ifndef DISASM_ONLY
 2002     {
 2003       0ULL,
 2004       0xffffffff80000000ULL,
 2005       0ULL,
 2006       0ULL,
 2007       0ULL
 2008     },
 2009     {
 2010       -1ULL,
 2011       0x286a44ae00000000ULL,
 2012       -1ULL,
 2013       -1ULL,
 2014       -1ULL
 2015     }
 2016 #endif
 2017   },
 2018   { "info", TILEGX_OPC_INFO, 0xf, 1, TREG_ZERO, 1,
 2019     { { 0 }, { 1 }, { 2 }, { 3 }, { 0, } },
 2020 #ifndef DISASM_ONLY
 2021     {
 2022       0xc00000007ff00fffULL,
 2023       0xfff807ff80000000ULL,
 2024       0x0000000078000fffULL,
 2025       0x3c0007ff80000000ULL,
 2026       0ULL
 2027     },
 2028     {
 2029       0x0000000040300fffULL,
 2030       0x181807ff80000000ULL,
 2031       0x0000000010000fffULL,
 2032       0x0c0007ff80000000ULL,
 2033       -1ULL
 2034     }
 2035 #endif
 2036   },
 2037   { "infol", TILEGX_OPC_INFOL, 0x3, 1, TREG_ZERO, 1,
 2038     { { 4 }, { 5 }, { 0, }, { 0, }, { 0, } },
 2039 #ifndef DISASM_ONLY
 2040     {
 2041       0xc000000070000fffULL,
 2042       0xf80007ff80000000ULL,
 2043       0ULL,
 2044       0ULL,
 2045       0ULL
 2046     },
 2047     {
 2048       0x0000000070000fffULL,
 2049       0x380007ff80000000ULL,
 2050       -1ULL,
 2051       -1ULL,
 2052       -1ULL
 2053     }
 2054 #endif
 2055   },
 2056   { "ld4s_tls", TILEGX_OPC_LD4S_TLS, 0x2, 3, TREG_ZERO, 1,
 2057     { { 0, }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
 2058 #ifndef DISASM_ONLY
 2059     {
 2060       0ULL,
 2061       0xfffff80000000000ULL,
 2062       0ULL,
 2063       0ULL,
 2064       0ULL
 2065     },
 2066     {
 2067       -1ULL,
 2068       0x1858000000000000ULL,
 2069       -1ULL,
 2070       -1ULL,
 2071       -1ULL
 2072     }
 2073 #endif
 2074   },
 2075   { "ld_tls", TILEGX_OPC_LD_TLS, 0x2, 3, TREG_ZERO, 1,
 2076     { { 0, }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
 2077 #ifndef DISASM_ONLY
 2078     {
 2079       0ULL,
 2080       0xfffff80000000000ULL,
 2081       0ULL,
 2082       0ULL,
 2083       0ULL
 2084     },
 2085     {
 2086       -1ULL,
 2087       0x18a0000000000000ULL,
 2088       -1ULL,
 2089       -1ULL,
 2090       -1ULL
 2091     }
 2092 #endif
 2093   },
 2094   { "move", TILEGX_OPC_MOVE, 0xf, 2, TREG_ZERO, 1,
 2095     { { 8, 9 }, { 6, 7 }, { 10, 11 }, { 12, 13 }, { 0, } },
 2096 #ifndef DISASM_ONLY
 2097     {
 2098       0xc00000007ffff000ULL,
 2099       0xfffff80000000000ULL,
 2100       0x00000000780ff000ULL,
 2101       0x3c07f80000000000ULL,
 2102       0ULL
 2103     },
 2104     {
 2105       0x000000005107f000ULL,
 2106       0x283bf80000000000ULL,
 2107       0x00000000500bf000ULL,
 2108       0x2c05f80000000000ULL,
 2109       -1ULL
 2110     }
 2111 #endif
 2112   },
 2113   { "movei", TILEGX_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1,
 2114     { { 8, 0 }, { 6, 1 }, { 10, 2 }, { 12, 3 }, { 0, } },
 2115 #ifndef DISASM_ONLY
 2116     {
 2117       0xc00000007ff00fc0ULL,
 2118       0xfff807e000000000ULL,
 2119       0x0000000078000fc0ULL,
 2120       0x3c0007e000000000ULL,
 2121       0ULL
 2122     },
 2123     {
 2124       0x0000000040100fc0ULL,
 2125       0x180807e000000000ULL,
 2126       0x0000000000000fc0ULL,
 2127       0x040007e000000000ULL,
 2128       -1ULL
 2129     }
 2130 #endif
 2131   },
 2132   { "moveli", TILEGX_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1,
 2133     { { 8, 4 }, { 6, 5 }, { 0, }, { 0, }, { 0, } },
 2134 #ifndef DISASM_ONLY
 2135     {
 2136       0xc000000070000fc0ULL,
 2137       0xf80007e000000000ULL,
 2138       0ULL,
 2139       0ULL,
 2140       0ULL
 2141     },
 2142     {
 2143       0x0000000010000fc0ULL,
 2144       0x000007e000000000ULL,
 2145       -1ULL,
 2146       -1ULL,
 2147       -1ULL
 2148     }
 2149 #endif
 2150   },
 2151   { "prefetch", TILEGX_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1,
 2152     { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
 2153 #ifndef DISASM_ONLY
 2154     {
 2155       0ULL,
 2156       0xfffff81f80000000ULL,
 2157       0ULL,
 2158       0ULL,
 2159       0xc3f8000004000000ULL
 2160     },
 2161     {
 2162       -1ULL,
 2163       0x286a801f80000000ULL,
 2164       -1ULL,
 2165       -1ULL,
 2166       0x41f8000004000000ULL
 2167     }
 2168 #endif
 2169   },
 2170   { "prefetch_add_l1", TILEGX_OPC_PREFETCH_ADD_L1, 0x2, 2, TREG_ZERO, 1,
 2171     { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
 2172 #ifndef DISASM_ONLY
 2173     {
 2174       0ULL,
 2175       0xfff8001f80000000ULL,
 2176       0ULL,
 2177       0ULL,
 2178       0ULL
 2179     },
 2180     {
 2181       -1ULL,
 2182       0x1840001f80000000ULL,
 2183       -1ULL,
 2184       -1ULL,
 2185       -1ULL
 2186     }
 2187 #endif
 2188   },
 2189   { "prefetch_add_l1_fault", TILEGX_OPC_PREFETCH_ADD_L1_FAULT, 0x2, 2, TREG_ZERO, 1,
 2190     { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
 2191 #ifndef DISASM_ONLY
 2192     {
 2193       0ULL,
 2194       0xfff8001f80000000ULL,
 2195       0ULL,
 2196       0ULL,
 2197       0ULL
 2198     },
 2199     {
 2200       -1ULL,
 2201       0x1838001f80000000ULL,
 2202       -1ULL,
 2203       -1ULL,
 2204       -1ULL
 2205     }
 2206 #endif
 2207   },
 2208   { "prefetch_add_l2", TILEGX_OPC_PREFETCH_ADD_L2, 0x2, 2, TREG_ZERO, 1,
 2209     { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
 2210 #ifndef DISASM_ONLY
 2211     {
 2212       0ULL,
 2213       0xfff8001f80000000ULL,
 2214       0ULL,
 2215       0ULL,
 2216       0ULL
 2217     },
 2218     {
 2219       -1ULL,
 2220       0x1850001f80000000ULL,
 2221       -1ULL,
 2222       -1ULL,
 2223       -1ULL
 2224     }
 2225 #endif
 2226   },
 2227   { "prefetch_add_l2_fault", TILEGX_OPC_PREFETCH_ADD_L2_FAULT, 0x2, 2, TREG_ZERO, 1,
 2228     { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
 2229 #ifndef DISASM_ONLY
 2230     {
 2231       0ULL,
 2232       0xfff8001f80000000ULL,
 2233       0ULL,
 2234       0ULL,
 2235       0ULL
 2236     },
 2237     {
 2238       -1ULL,
 2239       0x1848001f80000000ULL,
 2240       -1ULL,
 2241       -1ULL,
 2242       -1ULL
 2243     }
 2244 #endif
 2245   },
 2246   { "prefetch_add_l3", TILEGX_OPC_PREFETCH_ADD_L3, 0x2, 2, TREG_ZERO, 1,
 2247     { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
 2248 #ifndef DISASM_ONLY
 2249     {
 2250       0ULL,
 2251       0xfff8001f80000000ULL,
 2252       0ULL,
 2253       0ULL,
 2254       0ULL
 2255     },
 2256     {
 2257       -1ULL,
 2258       0x1860001f80000000ULL,
 2259       -1ULL,
 2260       -1ULL,
 2261       -1ULL
 2262     }
 2263 #endif
 2264   },
 2265   { "prefetch_add_l3_fault", TILEGX_OPC_PREFETCH_ADD_L3_FAULT, 0x2, 2, TREG_ZERO, 1,
 2266     { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
 2267 #ifndef DISASM_ONLY
 2268     {
 2269       0ULL,
 2270       0xfff8001f80000000ULL,
 2271       0ULL,
 2272       0ULL,
 2273       0ULL
 2274     },
 2275     {
 2276       -1ULL,
 2277       0x1858001f80000000ULL,
 2278       -1ULL,
 2279       -1ULL,
 2280       -1ULL
 2281     }
 2282 #endif
 2283   },
 2284   { "prefetch_l1", TILEGX_OPC_PREFETCH_L1, 0x12, 1, TREG_ZERO, 1,
 2285     { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
 2286 #ifndef DISASM_ONLY
 2287     {
 2288       0ULL,
 2289       0xfffff81f80000000ULL,
 2290       0ULL,
 2291       0ULL,
 2292       0xc3f8000004000000ULL
 2293     },
 2294     {
 2295       -1ULL,
 2296       0x286a801f80000000ULL,
 2297       -1ULL,
 2298       -1ULL,
 2299       0x41f8000004000000ULL
 2300     }
 2301 #endif
 2302   },
 2303   { "prefetch_l1_fault", TILEGX_OPC_PREFETCH_L1_FAULT, 0x12, 1, TREG_ZERO, 1,
 2304     { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
 2305 #ifndef DISASM_ONLY
 2306     {
 2307       0ULL,
 2308       0xfffff81f80000000ULL,
 2309       0ULL,
 2310       0ULL,
 2311       0xc3f8000004000000ULL
 2312     },
 2313     {
 2314       -1ULL,
 2315       0x286a781f80000000ULL,
 2316       -1ULL,
 2317       -1ULL,
 2318       0x41f8000000000000ULL
 2319     }
 2320 #endif
 2321   },
 2322   { "prefetch_l2", TILEGX_OPC_PREFETCH_L2, 0x12, 1, TREG_ZERO, 1,
 2323     { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
 2324 #ifndef DISASM_ONLY
 2325     {
 2326       0ULL,
 2327       0xfffff81f80000000ULL,
 2328       0ULL,
 2329       0ULL,
 2330       0xc3f8000004000000ULL
 2331     },
 2332     {
 2333       -1ULL,
 2334       0x286a901f80000000ULL,
 2335       -1ULL,
 2336       -1ULL,
 2337       0x43f8000004000000ULL
 2338     }
 2339 #endif
 2340   },
 2341   { "prefetch_l2_fault", TILEGX_OPC_PREFETCH_L2_FAULT, 0x12, 1, TREG_ZERO, 1,
 2342     { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
 2343 #ifndef DISASM_ONLY
 2344     {
 2345       0ULL,
 2346       0xfffff81f80000000ULL,
 2347       0ULL,
 2348       0ULL,
 2349       0xc3f8000004000000ULL
 2350     },
 2351     {
 2352       -1ULL,
 2353       0x286a881f80000000ULL,
 2354       -1ULL,
 2355       -1ULL,
 2356       0x43f8000000000000ULL
 2357     }
 2358 #endif
 2359   },
 2360   { "prefetch_l3", TILEGX_OPC_PREFETCH_L3, 0x12, 1, TREG_ZERO, 1,
 2361     { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
 2362 #ifndef DISASM_ONLY
 2363     {
 2364       0ULL,
 2365       0xfffff81f80000000ULL,
 2366       0ULL,
 2367       0ULL,
 2368       0xc3f8000004000000ULL
 2369     },
 2370     {
 2371       -1ULL,
 2372       0x286aa01f80000000ULL,
 2373       -1ULL,
 2374       -1ULL,
 2375       0x83f8000000000000ULL
 2376     }
 2377 #endif
 2378   },
 2379   { "prefetch_l3_fault", TILEGX_OPC_PREFETCH_L3_FAULT, 0x12, 1, TREG_ZERO, 1,
 2380     { { 0, }, { 7 }, { 0, }, { 0, }, { 14 } },
 2381 #ifndef DISASM_ONLY
 2382     {
 2383       0ULL,
 2384       0xfffff81f80000000ULL,
 2385       0ULL,
 2386       0ULL,
 2387       0xc3f8000004000000ULL
 2388     },
 2389     {
 2390       -1ULL,
 2391       0x286a981f80000000ULL,
 2392       -1ULL,
 2393       -1ULL,
 2394       0x81f8000004000000ULL
 2395     }
 2396 #endif
 2397   },
 2398   { "raise", TILEGX_OPC_RAISE, 0x2, 0, TREG_ZERO, 1,
 2399     { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
 2400 #ifndef DISASM_ONLY
 2401     {
 2402       0ULL,
 2403       0xffffffff80000000ULL,
 2404       0ULL,
 2405       0ULL,
 2406       0ULL
 2407     },
 2408     {
 2409       -1ULL,
 2410       0x286a44ae80000000ULL,
 2411       -1ULL,
 2412       -1ULL,
 2413       -1ULL
 2414     }
 2415 #endif
 2416   },
 2417   { "add", TILEGX_OPC_ADD, 0xf, 3, TREG_ZERO, 1,
 2418     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
 2419 #ifndef DISASM_ONLY
 2420     {
 2421       0xc00000007ffc0000ULL,
 2422       0xfffe000000000000ULL,
 2423       0x00000000780c0000ULL,
 2424       0x3c06000000000000ULL,
 2425       0ULL
 2426     },
 2427     {
 2428       0x00000000500c0000ULL,
 2429       0x2806000000000000ULL,
 2430       0x0000000028040000ULL,
 2431       0x1802000000000000ULL,
 2432       -1ULL
 2433     }
 2434 #endif
 2435   },
 2436   { "addi", TILEGX_OPC_ADDI, 0xf, 3, TREG_ZERO, 1,
 2437     { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
 2438 #ifndef DISASM_ONLY
 2439     {
 2440       0xc00000007ff00000ULL,
 2441       0xfff8000000000000ULL,
 2442       0x0000000078000000ULL,
 2443       0x3c00000000000000ULL,
 2444       0ULL
 2445     },
 2446     {
 2447       0x0000000040100000ULL,
 2448       0x1808000000000000ULL,
 2449       0ULL,
 2450       0x0400000000000000ULL,
 2451       -1ULL
 2452     }
 2453 #endif
 2454   },
 2455   { "addli", TILEGX_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1,
 2456     { { 8, 9, 4 }, { 6, 7, 5 }, { 0, }, { 0, }, { 0, } },
 2457 #ifndef DISASM_ONLY
 2458     {
 2459       0xc000000070000000ULL,
 2460       0xf800000000000000ULL,
 2461       0ULL,
 2462       0ULL,
 2463       0ULL
 2464     },
 2465     {
 2466       0x0000000010000000ULL,
 2467       0ULL,
 2468       -1ULL,
 2469       -1ULL,
 2470       -1ULL
 2471     }
 2472 #endif
 2473   },
 2474   { "addx", TILEGX_OPC_ADDX, 0xf, 3, TREG_ZERO, 1,
 2475     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
 2476 #ifndef DISASM_ONLY
 2477     {
 2478       0xc00000007ffc0000ULL,
 2479       0xfffe000000000000ULL,
 2480       0x00000000780c0000ULL,
 2481       0x3c06000000000000ULL,
 2482       0ULL
 2483     },
 2484     {
 2485       0x0000000050080000ULL,
 2486       0x2804000000000000ULL,
 2487       0x0000000028000000ULL,
 2488       0x1800000000000000ULL,
 2489       -1ULL
 2490     }
 2491 #endif
 2492   },
 2493   { "addxi", TILEGX_OPC_ADDXI, 0xf, 3, TREG_ZERO, 1,
 2494     { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
 2495 #ifndef DISASM_ONLY
 2496     {
 2497       0xc00000007ff00000ULL,
 2498       0xfff8000000000000ULL,
 2499       0x0000000078000000ULL,
 2500       0x3c00000000000000ULL,
 2501       0ULL
 2502     },
 2503     {
 2504       0x0000000040200000ULL,
 2505       0x1810000000000000ULL,
 2506       0x0000000008000000ULL,
 2507       0x0800000000000000ULL,
 2508       -1ULL
 2509     }
 2510 #endif
 2511   },
 2512   { "addxli", TILEGX_OPC_ADDXLI, 0x3, 3, TREG_ZERO, 1,
 2513     { { 8, 9, 4 }, { 6, 7, 5 }, { 0, }, { 0, }, { 0, } },
 2514 #ifndef DISASM_ONLY
 2515     {
 2516       0xc000000070000000ULL,
 2517       0xf800000000000000ULL,
 2518       0ULL,
 2519       0ULL,
 2520       0ULL
 2521     },
 2522     {
 2523       0x0000000020000000ULL,
 2524       0x0800000000000000ULL,
 2525       -1ULL,
 2526       -1ULL,
 2527       -1ULL
 2528     }
 2529 #endif
 2530   },
 2531   { "addxsc", TILEGX_OPC_ADDXSC, 0x3, 3, TREG_ZERO, 1,
 2532     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
 2533 #ifndef DISASM_ONLY
 2534     {
 2535       0xc00000007ffc0000ULL,
 2536       0xfffe000000000000ULL,
 2537       0ULL,
 2538       0ULL,
 2539       0ULL
 2540     },
 2541     {
 2542       0x0000000050040000ULL,
 2543       0x2802000000000000ULL,
 2544       -1ULL,
 2545       -1ULL,
 2546       -1ULL
 2547     }
 2548 #endif
 2549   },
 2550   { "and", TILEGX_OPC_AND, 0xf, 3, TREG_ZERO, 1,
 2551     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
 2552 #ifndef DISASM_ONLY
 2553     {
 2554       0xc00000007ffc0000ULL,
 2555       0xfffe000000000000ULL,
 2556       0x00000000780c0000ULL,
 2557       0x3c06000000000000ULL,
 2558       0ULL
 2559     },
 2560     {
 2561       0x0000000050100000ULL,
 2562       0x2808000000000000ULL,
 2563       0x0000000050000000ULL,
 2564       0x2c00000000000000ULL,
 2565       -1ULL
 2566     }
 2567 #endif
 2568   },
 2569   { "andi", TILEGX_OPC_ANDI, 0xf, 3, TREG_ZERO, 1,
 2570     { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
 2571 #ifndef DISASM_ONLY
 2572     {
 2573       0xc00000007ff00000ULL,
 2574       0xfff8000000000000ULL,
 2575       0x0000000078000000ULL,
 2576       0x3c00000000000000ULL,
 2577       0ULL
 2578     },
 2579     {
 2580       0x0000000040300000ULL,
 2581       0x1818000000000000ULL,
 2582       0x0000000010000000ULL,
 2583       0x0c00000000000000ULL,
 2584       -1ULL
 2585     }
 2586 #endif
 2587   },
 2588   { "beqz", TILEGX_OPC_BEQZ, 0x2, 2, TREG_ZERO, 1,
 2589     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
 2590 #ifndef DISASM_ONLY
 2591     {
 2592       0ULL,
 2593       0xffc0000000000000ULL,
 2594       0ULL,
 2595       0ULL,
 2596       0ULL
 2597     },
 2598     {
 2599       -1ULL,
 2600       0x1440000000000000ULL,
 2601       -1ULL,
 2602       -1ULL,
 2603       -1ULL
 2604     }
 2605 #endif
 2606   },
 2607   { "beqzt", TILEGX_OPC_BEQZT, 0x2, 2, TREG_ZERO, 1,
 2608     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
 2609 #ifndef DISASM_ONLY
 2610     {
 2611       0ULL,
 2612       0xffc0000000000000ULL,
 2613       0ULL,
 2614       0ULL,
 2615       0ULL
 2616     },
 2617     {
 2618       -1ULL,
 2619       0x1400000000000000ULL,
 2620       -1ULL,
 2621       -1ULL,
 2622       -1ULL
 2623     }
 2624 #endif
 2625   },
 2626   { "bfexts", TILEGX_OPC_BFEXTS, 0x1, 4, TREG_ZERO, 1,
 2627     { { 8, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
 2628 #ifndef DISASM_ONLY
 2629     {
 2630       0xc00000007f000000ULL,
 2631       0ULL,
 2632       0ULL,
 2633       0ULL,
 2634       0ULL
 2635     },
 2636     {
 2637       0x0000000034000000ULL,
 2638       -1ULL,
 2639       -1ULL,
 2640       -1ULL,
 2641       -1ULL
 2642     }
 2643 #endif
 2644   },
 2645   { "bfextu", TILEGX_OPC_BFEXTU, 0x1, 4, TREG_ZERO, 1,
 2646     { { 8, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
 2647 #ifndef DISASM_ONLY
 2648     {
 2649       0xc00000007f000000ULL,
 2650       0ULL,
 2651       0ULL,
 2652       0ULL,
 2653       0ULL
 2654     },
 2655     {
 2656       0x0000000035000000ULL,
 2657       -1ULL,
 2658       -1ULL,
 2659       -1ULL,
 2660       -1ULL
 2661     }
 2662 #endif
 2663   },
 2664   { "bfins", TILEGX_OPC_BFINS, 0x1, 4, TREG_ZERO, 1,
 2665     { { 23, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
 2666 #ifndef DISASM_ONLY
 2667     {
 2668       0xc00000007f000000ULL,
 2669       0ULL,
 2670       0ULL,
 2671       0ULL,
 2672       0ULL
 2673     },
 2674     {
 2675       0x0000000036000000ULL,
 2676       -1ULL,
 2677       -1ULL,
 2678       -1ULL,
 2679       -1ULL
 2680     }
 2681 #endif
 2682   },
 2683   { "bgez", TILEGX_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1,
 2684     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
 2685 #ifndef DISASM_ONLY
 2686     {
 2687       0ULL,
 2688       0xffc0000000000000ULL,
 2689       0ULL,
 2690       0ULL,
 2691       0ULL
 2692     },
 2693     {
 2694       -1ULL,
 2695       0x14c0000000000000ULL,
 2696       -1ULL,
 2697       -1ULL,
 2698       -1ULL
 2699     }
 2700 #endif
 2701   },
 2702   { "bgezt", TILEGX_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1,
 2703     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
 2704 #ifndef DISASM_ONLY
 2705     {
 2706       0ULL,
 2707       0xffc0000000000000ULL,
 2708       0ULL,
 2709       0ULL,
 2710       0ULL
 2711     },
 2712     {
 2713       -1ULL,
 2714       0x1480000000000000ULL,
 2715       -1ULL,
 2716       -1ULL,
 2717       -1ULL
 2718     }
 2719 #endif
 2720   },
 2721   { "bgtz", TILEGX_OPC_BGTZ, 0x2, 2, TREG_ZERO, 1,
 2722     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
 2723 #ifndef DISASM_ONLY
 2724     {
 2725       0ULL,
 2726       0xffc0000000000000ULL,
 2727       0ULL,
 2728       0ULL,
 2729       0ULL
 2730     },
 2731     {
 2732       -1ULL,
 2733       0x1540000000000000ULL,
 2734       -1ULL,
 2735       -1ULL,
 2736       -1ULL
 2737     }
 2738 #endif
 2739   },
 2740   { "bgtzt", TILEGX_OPC_BGTZT, 0x2, 2, TREG_ZERO, 1,
 2741     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
 2742 #ifndef DISASM_ONLY
 2743     {
 2744       0ULL,
 2745       0xffc0000000000000ULL,
 2746       0ULL,
 2747       0ULL,
 2748       0ULL
 2749     },
 2750     {
 2751       -1ULL,
 2752       0x1500000000000000ULL,
 2753       -1ULL,
 2754       -1ULL,
 2755       -1ULL
 2756     }
 2757 #endif
 2758   },
 2759   { "blbc", TILEGX_OPC_BLBC, 0x2, 2, TREG_ZERO, 1,
 2760     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
 2761 #ifndef DISASM_ONLY
 2762     {
 2763       0ULL,
 2764       0xffc0000000000000ULL,
 2765       0ULL,
 2766       0ULL,
 2767       0ULL
 2768     },
 2769     {
 2770       -1ULL,
 2771       0x15c0000000000000ULL,
 2772       -1ULL,
 2773       -1ULL,
 2774       -1ULL
 2775     }
 2776 #endif
 2777   },
 2778   { "blbct", TILEGX_OPC_BLBCT, 0x2, 2, TREG_ZERO, 1,
 2779     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
 2780 #ifndef DISASM_ONLY
 2781     {
 2782       0ULL,
 2783       0xffc0000000000000ULL,
 2784       0ULL,
 2785       0ULL,
 2786       0ULL
 2787     },
 2788     {
 2789       -1ULL,
 2790       0x1580000000000000ULL,
 2791       -1ULL,
 2792       -1ULL,
 2793       -1ULL
 2794     }
 2795 #endif
 2796   },
 2797   { "blbs", TILEGX_OPC_BLBS, 0x2, 2, TREG_ZERO, 1,
 2798     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
 2799 #ifndef DISASM_ONLY
 2800     {
 2801       0ULL,
 2802       0xffc0000000000000ULL,
 2803       0ULL,
 2804       0ULL,
 2805       0ULL
 2806     },
 2807     {
 2808       -1ULL,
 2809       0x1640000000000000ULL,
 2810       -1ULL,
 2811       -1ULL,
 2812       -1ULL
 2813     }
 2814 #endif
 2815   },
 2816   { "blbst", TILEGX_OPC_BLBST, 0x2, 2, TREG_ZERO, 1,
 2817     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
 2818 #ifndef DISASM_ONLY
 2819     {
 2820       0ULL,
 2821       0xffc0000000000000ULL,
 2822       0ULL,
 2823       0ULL,
 2824       0ULL
 2825     },
 2826     {
 2827       -1ULL,
 2828       0x1600000000000000ULL,
 2829       -1ULL,
 2830       -1ULL,
 2831       -1ULL
 2832     }
 2833 #endif
 2834   },
 2835   { "blez", TILEGX_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1,
 2836     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
 2837 #ifndef DISASM_ONLY
 2838     {
 2839       0ULL,
 2840       0xffc0000000000000ULL,
 2841       0ULL,
 2842       0ULL,
 2843       0ULL
 2844     },
 2845     {
 2846       -1ULL,
 2847       0x16c0000000000000ULL,
 2848       -1ULL,
 2849       -1ULL,
 2850       -1ULL
 2851     }
 2852 #endif
 2853   },
 2854   { "blezt", TILEGX_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1,
 2855     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
 2856 #ifndef DISASM_ONLY
 2857     {
 2858       0ULL,
 2859       0xffc0000000000000ULL,
 2860       0ULL,
 2861       0ULL,
 2862       0ULL
 2863     },
 2864     {
 2865       -1ULL,
 2866       0x1680000000000000ULL,
 2867       -1ULL,
 2868       -1ULL,
 2869       -1ULL
 2870     }
 2871 #endif
 2872   },
 2873   { "bltz", TILEGX_OPC_BLTZ, 0x2, 2, TREG_ZERO, 1,
 2874     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
 2875 #ifndef DISASM_ONLY
 2876     {
 2877       0ULL,
 2878       0xffc0000000000000ULL,
 2879       0ULL,
 2880       0ULL,
 2881       0ULL
 2882     },
 2883     {
 2884       -1ULL,
 2885       0x1740000000000000ULL,
 2886       -1ULL,
 2887       -1ULL,
 2888       -1ULL
 2889     }
 2890 #endif
 2891   },
 2892   { "bltzt", TILEGX_OPC_BLTZT, 0x2, 2, TREG_ZERO, 1,
 2893     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
 2894 #ifndef DISASM_ONLY
 2895     {
 2896       0ULL,
 2897       0xffc0000000000000ULL,
 2898       0ULL,
 2899       0ULL,
 2900       0ULL
 2901     },
 2902     {
 2903       -1ULL,
 2904       0x1700000000000000ULL,
 2905       -1ULL,
 2906       -1ULL,
 2907       -1ULL
 2908     }
 2909 #endif
 2910   },
 2911   { "bnez", TILEGX_OPC_BNEZ, 0x2, 2, TREG_ZERO, 1,
 2912     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
 2913 #ifndef DISASM_ONLY
 2914     {
 2915       0ULL,
 2916       0xffc0000000000000ULL,
 2917       0ULL,
 2918       0ULL,
 2919       0ULL
 2920     },
 2921     {
 2922       -1ULL,
 2923       0x17c0000000000000ULL,
 2924       -1ULL,
 2925       -1ULL,
 2926       -1ULL
 2927     }
 2928 #endif
 2929   },
 2930   { "bnezt", TILEGX_OPC_BNEZT, 0x2, 2, TREG_ZERO, 1,
 2931     { { 0, }, { 7, 20 }, { 0, }, { 0, }, { 0, } },
 2932 #ifndef DISASM_ONLY
 2933     {
 2934       0ULL,
 2935       0xffc0000000000000ULL,
 2936       0ULL,
 2937       0ULL,
 2938       0ULL
 2939     },
 2940     {
 2941       -1ULL,
 2942       0x1780000000000000ULL,
 2943       -1ULL,
 2944       -1ULL,
 2945       -1ULL
 2946     }
 2947 #endif
 2948   },
 2949   { "clz", TILEGX_OPC_CLZ, 0x5, 2, TREG_ZERO, 1,
 2950     { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
 2951 #ifndef DISASM_ONLY
 2952     {
 2953       0xc00000007ffff000ULL,
 2954       0ULL,
 2955       0x00000000780ff000ULL,
 2956       0ULL,
 2957       0ULL
 2958     },
 2959     {
 2960       0x0000000051481000ULL,
 2961       -1ULL,
 2962       0x00000000300c1000ULL,
 2963       -1ULL,
 2964       -1ULL
 2965     }
 2966 #endif
 2967   },
 2968   { "cmoveqz", TILEGX_OPC_CMOVEQZ, 0x5, 3, TREG_ZERO, 1,
 2969     { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
 2970 #ifndef DISASM_ONLY
 2971     {
 2972       0xc00000007ffc0000ULL,
 2973       0ULL,
 2974       0x00000000780c0000ULL,
 2975       0ULL,
 2976       0ULL
 2977     },
 2978     {
 2979       0x0000000050140000ULL,
 2980       -1ULL,
 2981       0x0000000048000000ULL,
 2982       -1ULL,
 2983       -1ULL
 2984     }
 2985 #endif
 2986   },
 2987   { "cmovnez", TILEGX_OPC_CMOVNEZ, 0x5, 3, TREG_ZERO, 1,
 2988     { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
 2989 #ifndef DISASM_ONLY
 2990     {
 2991       0xc00000007ffc0000ULL,
 2992       0ULL,
 2993       0x00000000780c0000ULL,
 2994       0ULL,
 2995       0ULL
 2996     },
 2997     {
 2998       0x0000000050180000ULL,
 2999       -1ULL,
 3000       0x0000000048040000ULL,
 3001       -1ULL,
 3002       -1ULL
 3003     }
 3004 #endif
 3005   },
 3006   { "cmpeq", TILEGX_OPC_CMPEQ, 0xf, 3, TREG_ZERO, 1,
 3007     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
 3008 #ifndef DISASM_ONLY
 3009     {
 3010       0xc00000007ffc0000ULL,
 3011       0xfffe000000000000ULL,
 3012       0x00000000780c0000ULL,
 3013       0x3c06000000000000ULL,
 3014       0ULL
 3015     },
 3016     {
 3017       0x00000000501c0000ULL,
 3018       0x280a000000000000ULL,
 3019       0x0000000040000000ULL,
 3020       0x2404000000000000ULL,
 3021       -1ULL
 3022     }
 3023 #endif
 3024   },
 3025   { "cmpeqi", TILEGX_OPC_CMPEQI, 0xf, 3, TREG_ZERO, 1,
 3026     { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
 3027 #ifndef DISASM_ONLY
 3028     {
 3029       0xc00000007ff00000ULL,
 3030       0xfff8000000000000ULL,
 3031       0x0000000078000000ULL,
 3032       0x3c00000000000000ULL,
 3033       0ULL
 3034     },
 3035     {
 3036       0x0000000040400000ULL,
 3037       0x1820000000000000ULL,
 3038       0x0000000018000000ULL,
 3039       0x1000000000000000ULL,
 3040       -1ULL
 3041     }
 3042 #endif
 3043   },
 3044   { "cmpexch", TILEGX_OPC_CMPEXCH, 0x2, 3, TREG_ZERO, 1,
 3045     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
 3046 #ifndef DISASM_ONLY
 3047     {
 3048       0ULL,
 3049       0xfffe000000000000ULL,
 3050       0ULL,
 3051       0ULL,
 3052       0ULL
 3053     },
 3054     {
 3055       -1ULL,
 3056       0x280e000000000000ULL,
 3057       -1ULL,
 3058       -1ULL,
 3059       -1ULL
 3060     }
 3061 #endif
 3062   },
 3063   { "cmpexch4", TILEGX_OPC_CMPEXCH4, 0x2, 3, TREG_ZERO, 1,
 3064     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
 3065 #ifndef DISASM_ONLY
 3066     {
 3067       0ULL,
 3068       0xfffe000000000000ULL,
 3069       0ULL,
 3070       0ULL,
 3071       0ULL
 3072     },
 3073     {
 3074       -1ULL,
 3075       0x280c000000000000ULL,
 3076       -1ULL,
 3077       -1ULL,
 3078       -1ULL
 3079     }
 3080 #endif
 3081   },
 3082   { "cmples", TILEGX_OPC_CMPLES, 0xf, 3, TREG_ZERO, 1,
 3083     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
 3084 #ifndef DISASM_ONLY
 3085     {
 3086       0xc00000007ffc0000ULL,
 3087       0xfffe000000000000ULL,
 3088       0x00000000780c0000ULL,
 3089       0x3c06000000000000ULL,
 3090       0ULL
 3091     },
 3092     {
 3093       0x0000000050200000ULL,
 3094       0x2810000000000000ULL,
 3095       0x0000000038000000ULL,
 3096       0x2000000000000000ULL,
 3097       -1ULL
 3098     }
 3099 #endif
 3100   },
 3101   { "cmpleu", TILEGX_OPC_CMPLEU, 0xf, 3, TREG_ZERO, 1,
 3102     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
 3103 #ifndef DISASM_ONLY
 3104     {
 3105       0xc00000007ffc0000ULL,
 3106       0xfffe000000000000ULL,
 3107       0x00000000780c0000ULL,
 3108       0x3c06000000000000ULL,
 3109       0ULL
 3110     },
 3111     {
 3112       0x0000000050240000ULL,
 3113       0x2812000000000000ULL,
 3114       0x0000000038040000ULL,
 3115       0x2002000000000000ULL,
 3116       -1ULL
 3117     }
 3118 #endif
 3119   },
 3120   { "cmplts", TILEGX_OPC_CMPLTS, 0xf, 3, TREG_ZERO, 1,
 3121     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
 3122 #ifndef DISASM_ONLY
 3123     {
 3124       0xc00000007ffc0000ULL,
 3125       0xfffe000000000000ULL,
 3126       0x00000000780c0000ULL,
 3127       0x3c06000000000000ULL,
 3128       0ULL
 3129     },
 3130     {
 3131       0x0000000050280000ULL,
 3132       0x2814000000000000ULL,
 3133       0x0000000038080000ULL,
 3134       0x2004000000000000ULL,
 3135       -1ULL
 3136     }
 3137 #endif
 3138   },
 3139   { "cmpltsi", TILEGX_OPC_CMPLTSI, 0xf, 3, TREG_ZERO, 1,
 3140     { { 8, 9, 0 }, { 6, 7, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
 3141 #ifndef DISASM_ONLY
 3142     {
 3143       0xc00000007ff00000ULL,
 3144       0xfff8000000000000ULL,
 3145       0x0000000078000000ULL,
 3146       0x3c00000000000000ULL,
 3147       0ULL
 3148     },
 3149     {
 3150       0x0000000040500000ULL,
 3151       0x1828000000000000ULL,
 3152       0x0000000020000000ULL,
 3153       0x1400000000000000ULL,
 3154       -1ULL
 3155     }
 3156 #endif
 3157   },
 3158   { "cmpltu", TILEGX_OPC_CMPLTU, 0xf, 3, TREG_ZERO, 1,
 3159     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
 3160 #ifndef DISASM_ONLY
 3161     {
 3162       0xc00000007ffc0000ULL,
 3163       0xfffe000000000000ULL,
 3164       0x00000000780c0000ULL,
 3165       0x3c06000000000000ULL,
 3166       0ULL
 3167     },
 3168     {
 3169       0x00000000502c0000ULL,
 3170       0x2816000000000000ULL,
 3171       0x00000000380c0000ULL,
 3172       0x2006000000000000ULL,
 3173       -1ULL
 3174     }
 3175 #endif
 3176   },
 3177   { "cmpltui", TILEGX_OPC_CMPLTUI, 0x3, 3, TREG_ZERO, 1,
 3178     { { 8, 9, 0 }, { 6, 7, 1 }, { 0, }, { 0, }, { 0, } },
 3179 #ifndef DISASM_ONLY
 3180     {
 3181       0xc00000007ff00000ULL,
 3182       0xfff8000000000000ULL,
 3183       0ULL,
 3184       0ULL,
 3185       0ULL
 3186     },
 3187     {
 3188       0x0000000040600000ULL,
 3189       0x1830000000000000ULL,
 3190       -1ULL,
 3191       -1ULL,
 3192       -1ULL
 3193     }
 3194 #endif
 3195   },
 3196   { "cmpne", TILEGX_OPC_CMPNE, 0xf, 3, TREG_ZERO, 1,
 3197     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
 3198 #ifndef DISASM_ONLY
 3199     {
 3200       0xc00000007ffc0000ULL,
 3201       0xfffe000000000000ULL,
 3202       0x00000000780c0000ULL,
 3203       0x3c06000000000000ULL,
 3204       0ULL
 3205     },
 3206     {
 3207       0x0000000050300000ULL,
 3208       0x2818000000000000ULL,
 3209       0x0000000040040000ULL,
 3210       0x2406000000000000ULL,
 3211       -1ULL
 3212     }
 3213 #endif
 3214   },
 3215   { "cmul", TILEGX_OPC_CMUL, 0x1, 3, TREG_ZERO, 1,
 3216     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3217 #ifndef DISASM_ONLY
 3218     {
 3219       0xc00000007ffc0000ULL,
 3220       0ULL,
 3221       0ULL,
 3222       0ULL,
 3223       0ULL
 3224     },
 3225     {
 3226       0x00000000504c0000ULL,
 3227       -1ULL,
 3228       -1ULL,
 3229       -1ULL,
 3230       -1ULL
 3231     }
 3232 #endif
 3233   },
 3234   { "cmula", TILEGX_OPC_CMULA, 0x1, 3, TREG_ZERO, 1,
 3235     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3236 #ifndef DISASM_ONLY
 3237     {
 3238       0xc00000007ffc0000ULL,
 3239       0ULL,
 3240       0ULL,
 3241       0ULL,
 3242       0ULL
 3243     },
 3244     {
 3245       0x0000000050380000ULL,
 3246       -1ULL,
 3247       -1ULL,
 3248       -1ULL,
 3249       -1ULL
 3250     }
 3251 #endif
 3252   },
 3253   { "cmulaf", TILEGX_OPC_CMULAF, 0x1, 3, TREG_ZERO, 1,
 3254     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3255 #ifndef DISASM_ONLY
 3256     {
 3257       0xc00000007ffc0000ULL,
 3258       0ULL,
 3259       0ULL,
 3260       0ULL,
 3261       0ULL
 3262     },
 3263     {
 3264       0x0000000050340000ULL,
 3265       -1ULL,
 3266       -1ULL,
 3267       -1ULL,
 3268       -1ULL
 3269     }
 3270 #endif
 3271   },
 3272   { "cmulf", TILEGX_OPC_CMULF, 0x1, 3, TREG_ZERO, 1,
 3273     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3274 #ifndef DISASM_ONLY
 3275     {
 3276       0xc00000007ffc0000ULL,
 3277       0ULL,
 3278       0ULL,
 3279       0ULL,
 3280       0ULL
 3281     },
 3282     {
 3283       0x0000000050400000ULL,
 3284       -1ULL,
 3285       -1ULL,
 3286       -1ULL,
 3287       -1ULL
 3288     }
 3289 #endif
 3290   },
 3291   { "cmulfr", TILEGX_OPC_CMULFR, 0x1, 3, TREG_ZERO, 1,
 3292     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3293 #ifndef DISASM_ONLY
 3294     {
 3295       0xc00000007ffc0000ULL,
 3296       0ULL,
 3297       0ULL,
 3298       0ULL,
 3299       0ULL
 3300     },
 3301     {
 3302       0x00000000503c0000ULL,
 3303       -1ULL,
 3304       -1ULL,
 3305       -1ULL,
 3306       -1ULL
 3307     }
 3308 #endif
 3309   },
 3310   { "cmulh", TILEGX_OPC_CMULH, 0x1, 3, TREG_ZERO, 1,
 3311     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3312 #ifndef DISASM_ONLY
 3313     {
 3314       0xc00000007ffc0000ULL,
 3315       0ULL,
 3316       0ULL,
 3317       0ULL,
 3318       0ULL
 3319     },
 3320     {
 3321       0x0000000050480000ULL,
 3322       -1ULL,
 3323       -1ULL,
 3324       -1ULL,
 3325       -1ULL
 3326     }
 3327 #endif
 3328   },
 3329   { "cmulhr", TILEGX_OPC_CMULHR, 0x1, 3, TREG_ZERO, 1,
 3330     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3331 #ifndef DISASM_ONLY
 3332     {
 3333       0xc00000007ffc0000ULL,
 3334       0ULL,
 3335       0ULL,
 3336       0ULL,
 3337       0ULL
 3338     },
 3339     {
 3340       0x0000000050440000ULL,
 3341       -1ULL,
 3342       -1ULL,
 3343       -1ULL,
 3344       -1ULL
 3345     }
 3346 #endif
 3347   },
 3348   { "crc32_32", TILEGX_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1,
 3349     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3350 #ifndef DISASM_ONLY
 3351     {
 3352       0xc00000007ffc0000ULL,
 3353       0ULL,
 3354       0ULL,
 3355       0ULL,
 3356       0ULL
 3357     },
 3358     {
 3359       0x0000000050500000ULL,
 3360       -1ULL,
 3361       -1ULL,
 3362       -1ULL,
 3363       -1ULL
 3364     }
 3365 #endif
 3366   },
 3367   { "crc32_8", TILEGX_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1,
 3368     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3369 #ifndef DISASM_ONLY
 3370     {
 3371       0xc00000007ffc0000ULL,
 3372       0ULL,
 3373       0ULL,
 3374       0ULL,
 3375       0ULL
 3376     },
 3377     {
 3378       0x0000000050540000ULL,
 3379       -1ULL,
 3380       -1ULL,
 3381       -1ULL,
 3382       -1ULL
 3383     }
 3384 #endif
 3385   },
 3386   { "ctz", TILEGX_OPC_CTZ, 0x5, 2, TREG_ZERO, 1,
 3387     { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
 3388 #ifndef DISASM_ONLY
 3389     {
 3390       0xc00000007ffff000ULL,
 3391       0ULL,
 3392       0x00000000780ff000ULL,
 3393       0ULL,
 3394       0ULL
 3395     },
 3396     {
 3397       0x0000000051482000ULL,
 3398       -1ULL,
 3399       0x00000000300c2000ULL,
 3400       -1ULL,
 3401       -1ULL
 3402     }
 3403 #endif
 3404   },
 3405   { "dblalign", TILEGX_OPC_DBLALIGN, 0x1, 3, TREG_ZERO, 1,
 3406     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3407 #ifndef DISASM_ONLY
 3408     {
 3409       0xc00000007ffc0000ULL,
 3410       0ULL,
 3411       0ULL,
 3412       0ULL,
 3413       0ULL
 3414     },
 3415     {
 3416       0x0000000050640000ULL,
 3417       -1ULL,
 3418       -1ULL,
 3419       -1ULL,
 3420       -1ULL
 3421     }
 3422 #endif
 3423   },
 3424   { "dblalign2", TILEGX_OPC_DBLALIGN2, 0x3, 3, TREG_ZERO, 1,
 3425     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
 3426 #ifndef DISASM_ONLY
 3427     {
 3428       0xc00000007ffc0000ULL,
 3429       0xfffe000000000000ULL,
 3430       0ULL,
 3431       0ULL,
 3432       0ULL
 3433     },
 3434     {
 3435       0x0000000050580000ULL,
 3436       0x281a000000000000ULL,
 3437       -1ULL,
 3438       -1ULL,
 3439       -1ULL
 3440     }
 3441 #endif
 3442   },
 3443   { "dblalign4", TILEGX_OPC_DBLALIGN4, 0x3, 3, TREG_ZERO, 1,
 3444     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
 3445 #ifndef DISASM_ONLY
 3446     {
 3447       0xc00000007ffc0000ULL,
 3448       0xfffe000000000000ULL,
 3449       0ULL,
 3450       0ULL,
 3451       0ULL
 3452     },
 3453     {
 3454       0x00000000505c0000ULL,
 3455       0x281c000000000000ULL,
 3456       -1ULL,
 3457       -1ULL,
 3458       -1ULL
 3459     }
 3460 #endif
 3461   },
 3462   { "dblalign6", TILEGX_OPC_DBLALIGN6, 0x3, 3, TREG_ZERO, 1,
 3463     { { 8, 9, 16 }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
 3464 #ifndef DISASM_ONLY
 3465     {
 3466       0xc00000007ffc0000ULL,
 3467       0xfffe000000000000ULL,
 3468       0ULL,
 3469       0ULL,
 3470       0ULL
 3471     },
 3472     {
 3473       0x0000000050600000ULL,
 3474       0x281e000000000000ULL,
 3475       -1ULL,
 3476       -1ULL,
 3477       -1ULL
 3478     }
 3479 #endif
 3480   },
 3481   { "drain", TILEGX_OPC_DRAIN, 0x2, 0, TREG_ZERO, 0,
 3482     { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
 3483 #ifndef DISASM_ONLY
 3484     {
 3485       0ULL,
 3486       0xfffff80000000000ULL,
 3487       0ULL,
 3488       0ULL,
 3489       0ULL
 3490     },
 3491     {
 3492       -1ULL,
 3493       0x286a080000000000ULL,
 3494       -1ULL,
 3495       -1ULL,
 3496       -1ULL
 3497     }
 3498 #endif
 3499   },
 3500   { "dtlbpr", TILEGX_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1,
 3501     { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
 3502 #ifndef DISASM_ONLY
 3503     {
 3504       0ULL,
 3505       0xfffff80000000000ULL,
 3506       0ULL,
 3507       0ULL,
 3508       0ULL
 3509     },
 3510     {
 3511       -1ULL,
 3512       0x286a100000000000ULL,
 3513       -1ULL,
 3514       -1ULL,
 3515       -1ULL
 3516     }
 3517 #endif
 3518   },
 3519   { "exch", TILEGX_OPC_EXCH, 0x2, 3, TREG_ZERO, 1,
 3520     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
 3521 #ifndef DISASM_ONLY
 3522     {
 3523       0ULL,
 3524       0xfffe000000000000ULL,
 3525       0ULL,
 3526       0ULL,
 3527       0ULL
 3528     },
 3529     {
 3530       -1ULL,
 3531       0x2822000000000000ULL,
 3532       -1ULL,
 3533       -1ULL,
 3534       -1ULL
 3535     }
 3536 #endif
 3537   },
 3538   { "exch4", TILEGX_OPC_EXCH4, 0x2, 3, TREG_ZERO, 1,
 3539     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
 3540 #ifndef DISASM_ONLY
 3541     {
 3542       0ULL,
 3543       0xfffe000000000000ULL,
 3544       0ULL,
 3545       0ULL,
 3546       0ULL
 3547     },
 3548     {
 3549       -1ULL,
 3550       0x2820000000000000ULL,
 3551       -1ULL,
 3552       -1ULL,
 3553       -1ULL
 3554     }
 3555 #endif
 3556   },
 3557   { "fdouble_add_flags", TILEGX_OPC_FDOUBLE_ADD_FLAGS, 0x1, 3, TREG_ZERO, 1,
 3558     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3559 #ifndef DISASM_ONLY
 3560     {
 3561       0xc00000007ffc0000ULL,
 3562       0ULL,
 3563       0ULL,
 3564       0ULL,
 3565       0ULL
 3566     },
 3567     {
 3568       0x00000000506c0000ULL,
 3569       -1ULL,
 3570       -1ULL,
 3571       -1ULL,
 3572       -1ULL
 3573     }
 3574 #endif
 3575   },
 3576   { "fdouble_addsub", TILEGX_OPC_FDOUBLE_ADDSUB, 0x1, 3, TREG_ZERO, 1,
 3577     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3578 #ifndef DISASM_ONLY
 3579     {
 3580       0xc00000007ffc0000ULL,
 3581       0ULL,
 3582       0ULL,
 3583       0ULL,
 3584       0ULL
 3585     },
 3586     {
 3587       0x0000000050680000ULL,
 3588       -1ULL,
 3589       -1ULL,
 3590       -1ULL,
 3591       -1ULL
 3592     }
 3593 #endif
 3594   },
 3595   { "fdouble_mul_flags", TILEGX_OPC_FDOUBLE_MUL_FLAGS, 0x1, 3, TREG_ZERO, 1,
 3596     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3597 #ifndef DISASM_ONLY
 3598     {
 3599       0xc00000007ffc0000ULL,
 3600       0ULL,
 3601       0ULL,
 3602       0ULL,
 3603       0ULL
 3604     },
 3605     {
 3606       0x0000000050700000ULL,
 3607       -1ULL,
 3608       -1ULL,
 3609       -1ULL,
 3610       -1ULL
 3611     }
 3612 #endif
 3613   },
 3614   { "fdouble_pack1", TILEGX_OPC_FDOUBLE_PACK1, 0x1, 3, TREG_ZERO, 1,
 3615     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3616 #ifndef DISASM_ONLY
 3617     {
 3618       0xc00000007ffc0000ULL,
 3619       0ULL,
 3620       0ULL,
 3621       0ULL,
 3622       0ULL
 3623     },
 3624     {
 3625       0x0000000050740000ULL,
 3626       -1ULL,
 3627       -1ULL,
 3628       -1ULL,
 3629       -1ULL
 3630     }
 3631 #endif
 3632   },
 3633   { "fdouble_pack2", TILEGX_OPC_FDOUBLE_PACK2, 0x1, 3, TREG_ZERO, 1,
 3634     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3635 #ifndef DISASM_ONLY
 3636     {
 3637       0xc00000007ffc0000ULL,
 3638       0ULL,
 3639       0ULL,
 3640       0ULL,
 3641       0ULL
 3642     },
 3643     {
 3644       0x0000000050780000ULL,
 3645       -1ULL,
 3646       -1ULL,
 3647       -1ULL,
 3648       -1ULL
 3649     }
 3650 #endif
 3651   },
 3652   { "fdouble_sub_flags", TILEGX_OPC_FDOUBLE_SUB_FLAGS, 0x1, 3, TREG_ZERO, 1,
 3653     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3654 #ifndef DISASM_ONLY
 3655     {
 3656       0xc00000007ffc0000ULL,
 3657       0ULL,
 3658       0ULL,
 3659       0ULL,
 3660       0ULL
 3661     },
 3662     {
 3663       0x00000000507c0000ULL,
 3664       -1ULL,
 3665       -1ULL,
 3666       -1ULL,
 3667       -1ULL
 3668     }
 3669 #endif
 3670   },
 3671   { "fdouble_unpack_max", TILEGX_OPC_FDOUBLE_UNPACK_MAX, 0x1, 3, TREG_ZERO, 1,
 3672     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3673 #ifndef DISASM_ONLY
 3674     {
 3675       0xc00000007ffc0000ULL,
 3676       0ULL,
 3677       0ULL,
 3678       0ULL,
 3679       0ULL
 3680     },
 3681     {
 3682       0x0000000050800000ULL,
 3683       -1ULL,
 3684       -1ULL,
 3685       -1ULL,
 3686       -1ULL
 3687     }
 3688 #endif
 3689   },
 3690   { "fdouble_unpack_min", TILEGX_OPC_FDOUBLE_UNPACK_MIN, 0x1, 3, TREG_ZERO, 1,
 3691     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3692 #ifndef DISASM_ONLY
 3693     {
 3694       0xc00000007ffc0000ULL,
 3695       0ULL,
 3696       0ULL,
 3697       0ULL,
 3698       0ULL
 3699     },
 3700     {
 3701       0x0000000050840000ULL,
 3702       -1ULL,
 3703       -1ULL,
 3704       -1ULL,
 3705       -1ULL
 3706     }
 3707 #endif
 3708   },
 3709   { "fetchadd", TILEGX_OPC_FETCHADD, 0x2, 3, TREG_ZERO, 1,
 3710     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
 3711 #ifndef DISASM_ONLY
 3712     {
 3713       0ULL,
 3714       0xfffe000000000000ULL,
 3715       0ULL,
 3716       0ULL,
 3717       0ULL
 3718     },
 3719     {
 3720       -1ULL,
 3721       0x282a000000000000ULL,
 3722       -1ULL,
 3723       -1ULL,
 3724       -1ULL
 3725     }
 3726 #endif
 3727   },
 3728   { "fetchadd4", TILEGX_OPC_FETCHADD4, 0x2, 3, TREG_ZERO, 1,
 3729     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
 3730 #ifndef DISASM_ONLY
 3731     {
 3732       0ULL,
 3733       0xfffe000000000000ULL,
 3734       0ULL,
 3735       0ULL,
 3736       0ULL
 3737     },
 3738     {
 3739       -1ULL,
 3740       0x2824000000000000ULL,
 3741       -1ULL,
 3742       -1ULL,
 3743       -1ULL
 3744     }
 3745 #endif
 3746   },
 3747   { "fetchaddgez", TILEGX_OPC_FETCHADDGEZ, 0x2, 3, TREG_ZERO, 1,
 3748     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
 3749 #ifndef DISASM_ONLY
 3750     {
 3751       0ULL,
 3752       0xfffe000000000000ULL,
 3753       0ULL,
 3754       0ULL,
 3755       0ULL
 3756     },
 3757     {
 3758       -1ULL,
 3759       0x2828000000000000ULL,
 3760       -1ULL,
 3761       -1ULL,
 3762       -1ULL
 3763     }
 3764 #endif
 3765   },
 3766   { "fetchaddgez4", TILEGX_OPC_FETCHADDGEZ4, 0x2, 3, TREG_ZERO, 1,
 3767     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
 3768 #ifndef DISASM_ONLY
 3769     {
 3770       0ULL,
 3771       0xfffe000000000000ULL,
 3772       0ULL,
 3773       0ULL,
 3774       0ULL
 3775     },
 3776     {
 3777       -1ULL,
 3778       0x2826000000000000ULL,
 3779       -1ULL,
 3780       -1ULL,
 3781       -1ULL
 3782     }
 3783 #endif
 3784   },
 3785   { "fetchand", TILEGX_OPC_FETCHAND, 0x2, 3, TREG_ZERO, 1,
 3786     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
 3787 #ifndef DISASM_ONLY
 3788     {
 3789       0ULL,
 3790       0xfffe000000000000ULL,
 3791       0ULL,
 3792       0ULL,
 3793       0ULL
 3794     },
 3795     {
 3796       -1ULL,
 3797       0x282e000000000000ULL,
 3798       -1ULL,
 3799       -1ULL,
 3800       -1ULL
 3801     }
 3802 #endif
 3803   },
 3804   { "fetchand4", TILEGX_OPC_FETCHAND4, 0x2, 3, TREG_ZERO, 1,
 3805     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
 3806 #ifndef DISASM_ONLY
 3807     {
 3808       0ULL,
 3809       0xfffe000000000000ULL,
 3810       0ULL,
 3811       0ULL,
 3812       0ULL
 3813     },
 3814     {
 3815       -1ULL,
 3816       0x282c000000000000ULL,
 3817       -1ULL,
 3818       -1ULL,
 3819       -1ULL
 3820     }
 3821 #endif
 3822   },
 3823   { "fetchor", TILEGX_OPC_FETCHOR, 0x2, 3, TREG_ZERO, 1,
 3824     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
 3825 #ifndef DISASM_ONLY
 3826     {
 3827       0ULL,
 3828       0xfffe000000000000ULL,
 3829       0ULL,
 3830       0ULL,
 3831       0ULL
 3832     },
 3833     {
 3834       -1ULL,
 3835       0x2832000000000000ULL,
 3836       -1ULL,
 3837       -1ULL,
 3838       -1ULL
 3839     }
 3840 #endif
 3841   },
 3842   { "fetchor4", TILEGX_OPC_FETCHOR4, 0x2, 3, TREG_ZERO, 1,
 3843     { { 0, }, { 6, 7, 17 }, { 0, }, { 0, }, { 0, } },
 3844 #ifndef DISASM_ONLY
 3845     {
 3846       0ULL,
 3847       0xfffe000000000000ULL,
 3848       0ULL,
 3849       0ULL,
 3850       0ULL
 3851     },
 3852     {
 3853       -1ULL,
 3854       0x2830000000000000ULL,
 3855       -1ULL,
 3856       -1ULL,
 3857       -1ULL
 3858     }
 3859 #endif
 3860   },
 3861   { "finv", TILEGX_OPC_FINV, 0x2, 1, TREG_ZERO, 1,
 3862     { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
 3863 #ifndef DISASM_ONLY
 3864     {
 3865       0ULL,
 3866       0xfffff80000000000ULL,
 3867       0ULL,
 3868       0ULL,
 3869       0ULL
 3870     },
 3871     {
 3872       -1ULL,
 3873       0x286a180000000000ULL,
 3874       -1ULL,
 3875       -1ULL,
 3876       -1ULL
 3877     }
 3878 #endif
 3879   },
 3880   { "flush", TILEGX_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1,
 3881     { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
 3882 #ifndef DISASM_ONLY
 3883     {
 3884       0ULL,
 3885       0xfffff80000000000ULL,
 3886       0ULL,
 3887       0ULL,
 3888       0ULL
 3889     },
 3890     {
 3891       -1ULL,
 3892       0x286a280000000000ULL,
 3893       -1ULL,
 3894       -1ULL,
 3895       -1ULL
 3896     }
 3897 #endif
 3898   },
 3899   { "flushwb", TILEGX_OPC_FLUSHWB, 0x2, 0, TREG_ZERO, 1,
 3900     { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
 3901 #ifndef DISASM_ONLY
 3902     {
 3903       0ULL,
 3904       0xfffff80000000000ULL,
 3905       0ULL,
 3906       0ULL,
 3907       0ULL
 3908     },
 3909     {
 3910       -1ULL,
 3911       0x286a200000000000ULL,
 3912       -1ULL,
 3913       -1ULL,
 3914       -1ULL
 3915     }
 3916 #endif
 3917   },
 3918   { "fnop", TILEGX_OPC_FNOP, 0xf, 0, TREG_ZERO, 1,
 3919     { {  }, {  }, {  }, {  }, { 0, } },
 3920 #ifndef DISASM_ONLY
 3921     {
 3922       0xc00000007ffff000ULL,
 3923       0xfffff80000000000ULL,
 3924       0x00000000780ff000ULL,
 3925       0x3c07f80000000000ULL,
 3926       0ULL
 3927     },
 3928     {
 3929       0x0000000051483000ULL,
 3930       0x286a300000000000ULL,
 3931       0x00000000300c3000ULL,
 3932       0x1c06400000000000ULL,
 3933       -1ULL
 3934     }
 3935 #endif
 3936   },
 3937   { "fsingle_add1", TILEGX_OPC_FSINGLE_ADD1, 0x1, 3, TREG_ZERO, 1,
 3938     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3939 #ifndef DISASM_ONLY
 3940     {
 3941       0xc00000007ffc0000ULL,
 3942       0ULL,
 3943       0ULL,
 3944       0ULL,
 3945       0ULL
 3946     },
 3947     {
 3948       0x0000000050880000ULL,
 3949       -1ULL,
 3950       -1ULL,
 3951       -1ULL,
 3952       -1ULL
 3953     }
 3954 #endif
 3955   },
 3956   { "fsingle_addsub2", TILEGX_OPC_FSINGLE_ADDSUB2, 0x1, 3, TREG_ZERO, 1,
 3957     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3958 #ifndef DISASM_ONLY
 3959     {
 3960       0xc00000007ffc0000ULL,
 3961       0ULL,
 3962       0ULL,
 3963       0ULL,
 3964       0ULL
 3965     },
 3966     {
 3967       0x00000000508c0000ULL,
 3968       -1ULL,
 3969       -1ULL,
 3970       -1ULL,
 3971       -1ULL
 3972     }
 3973 #endif
 3974   },
 3975   { "fsingle_mul1", TILEGX_OPC_FSINGLE_MUL1, 0x1, 3, TREG_ZERO, 1,
 3976     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3977 #ifndef DISASM_ONLY
 3978     {
 3979       0xc00000007ffc0000ULL,
 3980       0ULL,
 3981       0ULL,
 3982       0ULL,
 3983       0ULL
 3984     },
 3985     {
 3986       0x0000000050900000ULL,
 3987       -1ULL,
 3988       -1ULL,
 3989       -1ULL,
 3990       -1ULL
 3991     }
 3992 #endif
 3993   },
 3994   { "fsingle_mul2", TILEGX_OPC_FSINGLE_MUL2, 0x1, 3, TREG_ZERO, 1,
 3995     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 3996 #ifndef DISASM_ONLY
 3997     {
 3998       0xc00000007ffc0000ULL,
 3999       0ULL,
 4000       0ULL,
 4001       0ULL,
 4002       0ULL
 4003     },
 4004     {
 4005       0x0000000050940000ULL,
 4006       -1ULL,
 4007       -1ULL,
 4008       -1ULL,
 4009       -1ULL
 4010     }
 4011 #endif
 4012   },
 4013   { "fsingle_pack1", TILEGX_OPC_FSINGLE_PACK1, 0x5, 2, TREG_ZERO, 1,
 4014     { { 8, 9 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
 4015 #ifndef DISASM_ONLY
 4016     {
 4017       0xc00000007ffff000ULL,
 4018       0ULL,
 4019       0x00000000780ff000ULL,
 4020       0ULL,
 4021       0ULL
 4022     },
 4023     {
 4024       0x0000000051484000ULL,
 4025       -1ULL,
 4026       0x00000000300c4000ULL,
 4027       -1ULL,
 4028       -1ULL
 4029     }
 4030 #endif
 4031   },
 4032   { "fsingle_pack2", TILEGX_OPC_FSINGLE_PACK2, 0x1, 3, TREG_ZERO, 1,
 4033     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 4034 #ifndef DISASM_ONLY
 4035     {
 4036       0xc00000007ffc0000ULL,
 4037       0ULL,
 4038       0ULL,
 4039       0ULL,
 4040       0ULL
 4041     },
 4042     {
 4043       0x0000000050980000ULL,
 4044       -1ULL,
 4045       -1ULL,
 4046       -1ULL,
 4047       -1ULL
 4048     }
 4049 #endif
 4050   },
 4051   { "fsingle_sub1", TILEGX_OPC_FSINGLE_SUB1, 0x1, 3, TREG_ZERO, 1,
 4052     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 4053 #ifndef DISASM_ONLY
 4054     {
 4055       0xc00000007ffc0000ULL,
 4056       0ULL,
 4057       0ULL,
 4058       0ULL,
 4059       0ULL
 4060     },
 4061     {
 4062       0x00000000509c0000ULL,
 4063       -1ULL,
 4064       -1ULL,
 4065       -1ULL,
 4066       -1ULL
 4067     }
 4068 #endif
 4069   },
 4070   { "icoh", TILEGX_OPC_ICOH, 0x2, 1, TREG_ZERO, 1,
 4071     { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
 4072 #ifndef DISASM_ONLY
 4073     {
 4074       0ULL,
 4075       0xfffff80000000000ULL,
 4076       0ULL,
 4077       0ULL,
 4078       0ULL
 4079     },
 4080     {
 4081       -1ULL,
 4082       0x286a380000000000ULL,
 4083       -1ULL,
 4084       -1ULL,
 4085       -1ULL
 4086     }
 4087 #endif
 4088   },
 4089   { "ill", TILEGX_OPC_ILL, 0xa, 0, TREG_ZERO, 1,
 4090     { { 0, }, {  }, { 0, }, {  }, { 0, } },
 4091 #ifndef DISASM_ONLY
 4092     {
 4093       0ULL,
 4094       0xfffff80000000000ULL,
 4095       0ULL,
 4096       0x3c07f80000000000ULL,
 4097       0ULL
 4098     },
 4099     {
 4100       -1ULL,
 4101       0x286a400000000000ULL,
 4102       -1ULL,
 4103       0x1c06480000000000ULL,
 4104       -1ULL
 4105     }
 4106 #endif
 4107   },
 4108   { "inv", TILEGX_OPC_INV, 0x2, 1, TREG_ZERO, 1,
 4109     { { 0, }, { 7 }, { 0, }, { 0, }, { 0, } },
 4110 #ifndef DISASM_ONLY
 4111     {
 4112       0ULL,
 4113       0xfffff80000000000ULL,
 4114       0ULL,
 4115       0ULL,
 4116       0ULL
 4117     },
 4118     {
 4119       -1ULL,
 4120       0x286a480000000000ULL,
 4121       -1ULL,
 4122       -1ULL,
 4123       -1ULL
 4124     }
 4125 #endif
 4126   },
 4127   { "iret", TILEGX_OPC_IRET, 0x2, 0, TREG_ZERO, 1,
 4128     { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
 4129 #ifndef DISASM_ONLY
 4130     {
 4131       0ULL,
 4132       0xfffff80000000000ULL,
 4133       0ULL,
 4134       0ULL,
 4135       0ULL
 4136     },
 4137     {
 4138       -1ULL,
 4139       0x286a500000000000ULL,
 4140       -1ULL,
 4141       -1ULL,
 4142       -1ULL
 4143     }
 4144 #endif
 4145   },
 4146   { "j", TILEGX_OPC_J, 0x2, 1, TREG_ZERO, 1,
 4147     { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } },
 4148 #ifndef DISASM_ONLY
 4149     {
 4150       0ULL,
 4151       0xfc00000000000000ULL,
 4152       0ULL,
 4153       0ULL,
 4154       0ULL
 4155     },
 4156     {
 4157       -1ULL,
 4158       0x2400000000000000ULL,
 4159       -1ULL,
 4160       -1ULL,
 4161       -1ULL
 4162     }
 4163 #endif
 4164   },
 4165   { "jal", TILEGX_OPC_JAL, 0x2, 1, TREG_LR, 1,
 4166     { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } },
 4167 #ifndef DISASM_ONLY
 4168     {
 4169       0ULL,
 4170       0xfc00000000000000ULL,
 4171       0ULL,
 4172       0ULL,
 4173       0ULL
 4174     },
 4175     {
 4176       -1ULL,
 4177       0x2000000000000000ULL,
 4178       -1ULL,
 4179       -1ULL,
 4180       -1ULL
 4181     }
 4182 #endif
 4183   },
 4184   { "jalr", TILEGX_OPC_JALR, 0xa, 1, TREG_LR, 1,
 4185     { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } },
 4186 #ifndef DISASM_ONLY
 4187     {
 4188       0ULL,
 4189       0xfffff80000000000ULL,
 4190       0ULL,
 4191       0x3c07f80000000000ULL,
 4192       0ULL
 4193     },
 4194     {
 4195       -1ULL,
 4196       0x286a600000000000ULL,
 4197       -1ULL,
 4198       0x1c06580000000000ULL,
 4199       -1ULL
 4200     }
 4201 #endif
 4202   },
 4203   { "jalrp", TILEGX_OPC_JALRP, 0xa, 1, TREG_LR, 1,
 4204     { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } },
 4205 #ifndef DISASM_ONLY
 4206     {
 4207       0ULL,
 4208       0xfffff80000000000ULL,
 4209       0ULL,
 4210       0x3c07f80000000000ULL,
 4211       0ULL
 4212     },
 4213     {
 4214       -1ULL,
 4215       0x286a580000000000ULL,
 4216       -1ULL,
 4217       0x1c06500000000000ULL,
 4218       -1ULL
 4219     }
 4220 #endif
 4221   },
 4222   { "jr", TILEGX_OPC_JR, 0xa, 1, TREG_ZERO, 1,
 4223     { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } },
 4224 #ifndef DISASM_ONLY
 4225     {
 4226       0ULL,
 4227       0xfffff80000000000ULL,
 4228       0ULL,
 4229       0x3c07f80000000000ULL,
 4230       0ULL
 4231     },
 4232     {
 4233       -1ULL,
 4234       0x286a700000000000ULL,
 4235       -1ULL,
 4236       0x1c06680000000000ULL,
 4237       -1ULL
 4238     }
 4239 #endif
 4240   },
 4241   { "jrp", TILEGX_OPC_JRP, 0xa, 1, TREG_ZERO, 1,
 4242     { { 0, }, { 7 }, { 0, }, { 13 }, { 0, } },
 4243 #ifndef DISASM_ONLY
 4244     {
 4245       0ULL,
 4246       0xfffff80000000000ULL,
 4247       0ULL,
 4248       0x3c07f80000000000ULL,
 4249       0ULL
 4250     },
 4251     {
 4252       -1ULL,
 4253       0x286a680000000000ULL,
 4254       -1ULL,
 4255       0x1c06600000000000ULL,
 4256       -1ULL
 4257     }
 4258 #endif
 4259   },
 4260   { "ld", TILEGX_OPC_LD, 0x12, 2, TREG_ZERO, 1,
 4261     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
 4262 #ifndef DISASM_ONLY
 4263     {
 4264       0ULL,
 4265       0xfffff80000000000ULL,
 4266       0ULL,
 4267       0ULL,
 4268       0xc200000004000000ULL
 4269     },
 4270     {
 4271       -1ULL,
 4272       0x286ae80000000000ULL,
 4273       -1ULL,
 4274       -1ULL,
 4275       0x8200000004000000ULL
 4276     }
 4277 #endif
 4278   },
 4279   { "ld1s", TILEGX_OPC_LD1S, 0x12, 2, TREG_ZERO, 1,
 4280     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
 4281 #ifndef DISASM_ONLY
 4282     {
 4283       0ULL,
 4284       0xfffff80000000000ULL,
 4285       0ULL,
 4286       0ULL,
 4287       0xc200000004000000ULL
 4288     },
 4289     {
 4290       -1ULL,
 4291       0x286a780000000000ULL,
 4292       -1ULL,
 4293       -1ULL,
 4294       0x4000000000000000ULL
 4295     }
 4296 #endif
 4297   },
 4298   { "ld1s_add", TILEGX_OPC_LD1S_ADD, 0x2, 3, TREG_ZERO, 1,
 4299     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
 4300 #ifndef DISASM_ONLY
 4301     {
 4302       0ULL,
 4303       0xfff8000000000000ULL,
 4304       0ULL,
 4305       0ULL,
 4306       0ULL
 4307     },
 4308     {
 4309       -1ULL,
 4310       0x1838000000000000ULL,
 4311       -1ULL,
 4312       -1ULL,
 4313       -1ULL
 4314     }
 4315 #endif
 4316   },
 4317   { "ld1u", TILEGX_OPC_LD1U, 0x12, 2, TREG_ZERO, 1,
 4318     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
 4319 #ifndef DISASM_ONLY
 4320     {
 4321       0ULL,
 4322       0xfffff80000000000ULL,
 4323       0ULL,
 4324       0ULL,
 4325       0xc200000004000000ULL
 4326     },
 4327     {
 4328       -1ULL,
 4329       0x286a800000000000ULL,
 4330       -1ULL,
 4331       -1ULL,
 4332       0x4000000004000000ULL
 4333     }
 4334 #endif
 4335   },
 4336   { "ld1u_add", TILEGX_OPC_LD1U_ADD, 0x2, 3, TREG_ZERO, 1,
 4337     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
 4338 #ifndef DISASM_ONLY
 4339     {
 4340       0ULL,
 4341       0xfff8000000000000ULL,
 4342       0ULL,
 4343       0ULL,
 4344       0ULL
 4345     },
 4346     {
 4347       -1ULL,
 4348       0x1840000000000000ULL,
 4349       -1ULL,
 4350       -1ULL,
 4351       -1ULL
 4352     }
 4353 #endif
 4354   },
 4355   { "ld2s", TILEGX_OPC_LD2S, 0x12, 2, TREG_ZERO, 1,
 4356     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
 4357 #ifndef DISASM_ONLY
 4358     {
 4359       0ULL,
 4360       0xfffff80000000000ULL,
 4361       0ULL,
 4362       0ULL,
 4363       0xc200000004000000ULL
 4364     },
 4365     {
 4366       -1ULL,
 4367       0x286a880000000000ULL,
 4368       -1ULL,
 4369       -1ULL,
 4370       0x4200000000000000ULL
 4371     }
 4372 #endif
 4373   },
 4374   { "ld2s_add", TILEGX_OPC_LD2S_ADD, 0x2, 3, TREG_ZERO, 1,
 4375     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
 4376 #ifndef DISASM_ONLY
 4377     {
 4378       0ULL,
 4379       0xfff8000000000000ULL,
 4380       0ULL,
 4381       0ULL,
 4382       0ULL
 4383     },
 4384     {
 4385       -1ULL,
 4386       0x1848000000000000ULL,
 4387       -1ULL,
 4388       -1ULL,
 4389       -1ULL
 4390     }
 4391 #endif
 4392   },
 4393   { "ld2u", TILEGX_OPC_LD2U, 0x12, 2, TREG_ZERO, 1,
 4394     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
 4395 #ifndef DISASM_ONLY
 4396     {
 4397       0ULL,
 4398       0xfffff80000000000ULL,
 4399       0ULL,
 4400       0ULL,
 4401       0xc200000004000000ULL
 4402     },
 4403     {
 4404       -1ULL,
 4405       0x286a900000000000ULL,
 4406       -1ULL,
 4407       -1ULL,
 4408       0x4200000004000000ULL
 4409     }
 4410 #endif
 4411   },
 4412   { "ld2u_add", TILEGX_OPC_LD2U_ADD, 0x2, 3, TREG_ZERO, 1,
 4413     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
 4414 #ifndef DISASM_ONLY
 4415     {
 4416       0ULL,
 4417       0xfff8000000000000ULL,
 4418       0ULL,
 4419       0ULL,
 4420       0ULL
 4421     },
 4422     {
 4423       -1ULL,
 4424       0x1850000000000000ULL,
 4425       -1ULL,
 4426       -1ULL,
 4427       -1ULL
 4428     }
 4429 #endif
 4430   },
 4431   { "ld4s", TILEGX_OPC_LD4S, 0x12, 2, TREG_ZERO, 1,
 4432     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
 4433 #ifndef DISASM_ONLY
 4434     {
 4435       0ULL,
 4436       0xfffff80000000000ULL,
 4437       0ULL,
 4438       0ULL,
 4439       0xc200000004000000ULL
 4440     },
 4441     {
 4442       -1ULL,
 4443       0x286a980000000000ULL,
 4444       -1ULL,
 4445       -1ULL,
 4446       0x8000000004000000ULL
 4447     }
 4448 #endif
 4449   },
 4450   { "ld4s_add", TILEGX_OPC_LD4S_ADD, 0x2, 3, TREG_ZERO, 1,
 4451     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
 4452 #ifndef DISASM_ONLY
 4453     {
 4454       0ULL,
 4455       0xfff8000000000000ULL,
 4456       0ULL,
 4457       0ULL,
 4458       0ULL
 4459     },
 4460     {
 4461       -1ULL,
 4462       0x1858000000000000ULL,
 4463       -1ULL,
 4464       -1ULL,
 4465       -1ULL
 4466     }
 4467 #endif
 4468   },
 4469   { "ld4u", TILEGX_OPC_LD4U, 0x12, 2, TREG_ZERO, 1,
 4470     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 26, 14 } },
 4471 #ifndef DISASM_ONLY
 4472     {
 4473       0ULL,
 4474       0xfffff80000000000ULL,
 4475       0ULL,
 4476       0ULL,
 4477       0xc200000004000000ULL
 4478     },
 4479     {
 4480       -1ULL,
 4481       0x286aa00000000000ULL,
 4482       -1ULL,
 4483       -1ULL,
 4484       0x8200000000000000ULL
 4485     }
 4486 #endif
 4487   },
 4488   { "ld4u_add", TILEGX_OPC_LD4U_ADD, 0x2, 3, TREG_ZERO, 1,
 4489     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
 4490 #ifndef DISASM_ONLY
 4491     {
 4492       0ULL,
 4493       0xfff8000000000000ULL,
 4494       0ULL,
 4495       0ULL,
 4496       0ULL
 4497     },
 4498     {
 4499       -1ULL,
 4500       0x1860000000000000ULL,
 4501       -1ULL,
 4502       -1ULL,
 4503       -1ULL
 4504     }
 4505 #endif
 4506   },
 4507   { "ld_add", TILEGX_OPC_LD_ADD, 0x2, 3, TREG_ZERO, 1,
 4508     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
 4509 #ifndef DISASM_ONLY
 4510     {
 4511       0ULL,
 4512       0xfff8000000000000ULL,
 4513       0ULL,
 4514       0ULL,
 4515       0ULL
 4516     },
 4517     {
 4518       -1ULL,
 4519       0x18a0000000000000ULL,
 4520       -1ULL,
 4521       -1ULL,
 4522       -1ULL
 4523     }
 4524 #endif
 4525   },
 4526   { "ldna", TILEGX_OPC_LDNA, 0x2, 2, TREG_ZERO, 1,
 4527     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
 4528 #ifndef DISASM_ONLY
 4529     {
 4530       0ULL,
 4531       0xfffff80000000000ULL,
 4532       0ULL,
 4533       0ULL,
 4534       0ULL
 4535     },
 4536     {
 4537       -1ULL,
 4538       0x286aa80000000000ULL,
 4539       -1ULL,
 4540       -1ULL,
 4541       -1ULL
 4542     }
 4543 #endif
 4544   },
 4545   { "ldna_add", TILEGX_OPC_LDNA_ADD, 0x2, 3, TREG_ZERO, 1,
 4546     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
 4547 #ifndef DISASM_ONLY
 4548     {
 4549       0ULL,
 4550       0xfff8000000000000ULL,
 4551       0ULL,
 4552       0ULL,
 4553       0ULL
 4554     },
 4555     {
 4556       -1ULL,
 4557       0x18a8000000000000ULL,
 4558       -1ULL,
 4559       -1ULL,
 4560       -1ULL
 4561     }
 4562 #endif
 4563   },
 4564   { "ldnt", TILEGX_OPC_LDNT, 0x2, 2, TREG_ZERO, 1,
 4565     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
 4566 #ifndef DISASM_ONLY
 4567     {
 4568       0ULL,
 4569       0xfffff80000000000ULL,
 4570       0ULL,
 4571       0ULL,
 4572       0ULL
 4573     },
 4574     {
 4575       -1ULL,
 4576       0x286ae00000000000ULL,
 4577       -1ULL,
 4578       -1ULL,
 4579       -1ULL
 4580     }
 4581 #endif
 4582   },
 4583   { "ldnt1s", TILEGX_OPC_LDNT1S, 0x2, 2, TREG_ZERO, 1,
 4584     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
 4585 #ifndef DISASM_ONLY
 4586     {
 4587       0ULL,
 4588       0xfffff80000000000ULL,
 4589       0ULL,
 4590       0ULL,
 4591       0ULL
 4592     },
 4593     {
 4594       -1ULL,
 4595       0x286ab00000000000ULL,
 4596       -1ULL,
 4597       -1ULL,
 4598       -1ULL
 4599     }
 4600 #endif
 4601   },
 4602   { "ldnt1s_add", TILEGX_OPC_LDNT1S_ADD, 0x2, 3, TREG_ZERO, 1,
 4603     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
 4604 #ifndef DISASM_ONLY
 4605     {
 4606       0ULL,
 4607       0xfff8000000000000ULL,
 4608       0ULL,
 4609       0ULL,
 4610       0ULL
 4611     },
 4612     {
 4613       -1ULL,
 4614       0x1868000000000000ULL,
 4615       -1ULL,
 4616       -1ULL,
 4617       -1ULL
 4618     }
 4619 #endif
 4620   },
 4621   { "ldnt1u", TILEGX_OPC_LDNT1U, 0x2, 2, TREG_ZERO, 1,
 4622     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
 4623 #ifndef DISASM_ONLY
 4624     {
 4625       0ULL,
 4626       0xfffff80000000000ULL,
 4627       0ULL,
 4628       0ULL,
 4629       0ULL
 4630     },
 4631     {
 4632       -1ULL,
 4633       0x286ab80000000000ULL,
 4634       -1ULL,
 4635       -1ULL,
 4636       -1ULL
 4637     }
 4638 #endif
 4639   },
 4640   { "ldnt1u_add", TILEGX_OPC_LDNT1U_ADD, 0x2, 3, TREG_ZERO, 1,
 4641     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
 4642 #ifndef DISASM_ONLY
 4643     {
 4644       0ULL,
 4645       0xfff8000000000000ULL,
 4646       0ULL,
 4647       0ULL,
 4648       0ULL
 4649     },
 4650     {
 4651       -1ULL,
 4652       0x1870000000000000ULL,
 4653       -1ULL,
 4654       -1ULL,
 4655       -1ULL
 4656     }
 4657 #endif
 4658   },
 4659   { "ldnt2s", TILEGX_OPC_LDNT2S, 0x2, 2, TREG_ZERO, 1,
 4660     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
 4661 #ifndef DISASM_ONLY
 4662     {
 4663       0ULL,
 4664       0xfffff80000000000ULL,
 4665       0ULL,
 4666       0ULL,
 4667       0ULL
 4668     },
 4669     {
 4670       -1ULL,
 4671       0x286ac00000000000ULL,
 4672       -1ULL,
 4673       -1ULL,
 4674       -1ULL
 4675     }
 4676 #endif
 4677   },
 4678   { "ldnt2s_add", TILEGX_OPC_LDNT2S_ADD, 0x2, 3, TREG_ZERO, 1,
 4679     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
 4680 #ifndef DISASM_ONLY
 4681     {
 4682       0ULL,
 4683       0xfff8000000000000ULL,
 4684       0ULL,
 4685       0ULL,
 4686       0ULL
 4687     },
 4688     {
 4689       -1ULL,
 4690       0x1878000000000000ULL,
 4691       -1ULL,
 4692       -1ULL,
 4693       -1ULL
 4694     }
 4695 #endif
 4696   },
 4697   { "ldnt2u", TILEGX_OPC_LDNT2U, 0x2, 2, TREG_ZERO, 1,
 4698     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
 4699 #ifndef DISASM_ONLY
 4700     {
 4701       0ULL,
 4702       0xfffff80000000000ULL,
 4703       0ULL,
 4704       0ULL,
 4705       0ULL
 4706     },
 4707     {
 4708       -1ULL,
 4709       0x286ac80000000000ULL,
 4710       -1ULL,
 4711       -1ULL,
 4712       -1ULL
 4713     }
 4714 #endif
 4715   },
 4716   { "ldnt2u_add", TILEGX_OPC_LDNT2U_ADD, 0x2, 3, TREG_ZERO, 1,
 4717     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
 4718 #ifndef DISASM_ONLY
 4719     {
 4720       0ULL,
 4721       0xfff8000000000000ULL,
 4722       0ULL,
 4723       0ULL,
 4724       0ULL
 4725     },
 4726     {
 4727       -1ULL,
 4728       0x1880000000000000ULL,
 4729       -1ULL,
 4730       -1ULL,
 4731       -1ULL
 4732     }
 4733 #endif
 4734   },
 4735   { "ldnt4s", TILEGX_OPC_LDNT4S, 0x2, 2, TREG_ZERO, 1,
 4736     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
 4737 #ifndef DISASM_ONLY
 4738     {
 4739       0ULL,
 4740       0xfffff80000000000ULL,
 4741       0ULL,
 4742       0ULL,
 4743       0ULL
 4744     },
 4745     {
 4746       -1ULL,
 4747       0x286ad00000000000ULL,
 4748       -1ULL,
 4749       -1ULL,
 4750       -1ULL
 4751     }
 4752 #endif
 4753   },
 4754   { "ldnt4s_add", TILEGX_OPC_LDNT4S_ADD, 0x2, 3, TREG_ZERO, 1,
 4755     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
 4756 #ifndef DISASM_ONLY
 4757     {
 4758       0ULL,
 4759       0xfff8000000000000ULL,
 4760       0ULL,
 4761       0ULL,
 4762       0ULL
 4763     },
 4764     {
 4765       -1ULL,
 4766       0x1888000000000000ULL,
 4767       -1ULL,
 4768       -1ULL,
 4769       -1ULL
 4770     }
 4771 #endif
 4772   },
 4773   { "ldnt4u", TILEGX_OPC_LDNT4U, 0x2, 2, TREG_ZERO, 1,
 4774     { { 0, }, { 6, 7 }, { 0, }, { 0, }, { 0, } },
 4775 #ifndef DISASM_ONLY
 4776     {
 4777       0ULL,
 4778       0xfffff80000000000ULL,
 4779       0ULL,
 4780       0ULL,
 4781       0ULL
 4782     },
 4783     {
 4784       -1ULL,
 4785       0x286ad80000000000ULL,
 4786       -1ULL,
 4787       -1ULL,
 4788       -1ULL
 4789     }
 4790 #endif
 4791   },
 4792   { "ldnt4u_add", TILEGX_OPC_LDNT4U_ADD, 0x2, 3, TREG_ZERO, 1,
 4793     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
 4794 #ifndef DISASM_ONLY
 4795     {
 4796       0ULL,
 4797       0xfff8000000000000ULL,
 4798       0ULL,
 4799       0ULL,
 4800       0ULL
 4801     },
 4802     {
 4803       -1ULL,
 4804       0x1890000000000000ULL,
 4805       -1ULL,
 4806       -1ULL,
 4807       -1ULL
 4808     }
 4809 #endif
 4810   },
 4811   { "ldnt_add", TILEGX_OPC_LDNT_ADD, 0x2, 3, TREG_ZERO, 1,
 4812     { { 0, }, { 6, 15, 1 }, { 0, }, { 0, }, { 0, } },
 4813 #ifndef DISASM_ONLY
 4814     {
 4815       0ULL,
 4816       0xfff8000000000000ULL,
 4817       0ULL,
 4818       0ULL,
 4819       0ULL
 4820     },
 4821     {
 4822       -1ULL,
 4823       0x1898000000000000ULL,
 4824       -1ULL,
 4825       -1ULL,
 4826       -1ULL
 4827     }
 4828 #endif
 4829   },
 4830   { "lnk", TILEGX_OPC_LNK, 0xa, 1, TREG_ZERO, 1,
 4831     { { 0, }, { 6 }, { 0, }, { 12 }, { 0, } },
 4832 #ifndef DISASM_ONLY
 4833     {
 4834       0ULL,
 4835       0xfffff80000000000ULL,
 4836       0ULL,
 4837       0x3c07f80000000000ULL,
 4838       0ULL
 4839     },
 4840     {
 4841       -1ULL,
 4842       0x286af00000000000ULL,
 4843       -1ULL,
 4844       0x1c06700000000000ULL,
 4845       -1ULL
 4846     }
 4847 #endif
 4848   },
 4849   { "mf", TILEGX_OPC_MF, 0x2, 0, TREG_ZERO, 1,
 4850     { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
 4851 #ifndef DISASM_ONLY
 4852     {
 4853       0ULL,
 4854       0xfffff80000000000ULL,
 4855       0ULL,
 4856       0ULL,
 4857       0ULL
 4858     },
 4859     {
 4860       -1ULL,
 4861       0x286af80000000000ULL,
 4862       -1ULL,
 4863       -1ULL,
 4864       -1ULL
 4865     }
 4866 #endif
 4867   },
 4868   { "mfspr", TILEGX_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1,
 4869     { { 0, }, { 6, 27 }, { 0, }, { 0, }, { 0, } },
 4870 #ifndef DISASM_ONLY
 4871     {
 4872       0ULL,
 4873       0xfff8000000000000ULL,
 4874       0ULL,
 4875       0ULL,
 4876       0ULL
 4877     },
 4878     {
 4879       -1ULL,
 4880       0x18b0000000000000ULL,
 4881       -1ULL,
 4882       -1ULL,
 4883       -1ULL
 4884     }
 4885 #endif
 4886   },
 4887   { "mm", TILEGX_OPC_MM, 0x1, 4, TREG_ZERO, 1,
 4888     { { 23, 9, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
 4889 #ifndef DISASM_ONLY
 4890     {
 4891       0xc00000007f000000ULL,
 4892       0ULL,
 4893       0ULL,
 4894       0ULL,
 4895       0ULL
 4896     },
 4897     {
 4898       0x0000000037000000ULL,
 4899       -1ULL,
 4900       -1ULL,
 4901       -1ULL,
 4902       -1ULL
 4903     }
 4904 #endif
 4905   },
 4906   { "mnz", TILEGX_OPC_MNZ, 0xf, 3, TREG_ZERO, 1,
 4907     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
 4908 #ifndef DISASM_ONLY
 4909     {
 4910       0xc00000007ffc0000ULL,
 4911       0xfffe000000000000ULL,
 4912       0x00000000780c0000ULL,
 4913       0x3c06000000000000ULL,
 4914       0ULL
 4915     },
 4916     {
 4917       0x0000000050a00000ULL,
 4918       0x2834000000000000ULL,
 4919       0x0000000048080000ULL,
 4920       0x2804000000000000ULL,
 4921       -1ULL
 4922     }
 4923 #endif
 4924   },
 4925   { "mtspr", TILEGX_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1,
 4926     { { 0, }, { 28, 7 }, { 0, }, { 0, }, { 0, } },
 4927 #ifndef DISASM_ONLY
 4928     {
 4929       0ULL,
 4930       0xfff8000000000000ULL,
 4931       0ULL,
 4932       0ULL,
 4933       0ULL
 4934     },
 4935     {
 4936       -1ULL,
 4937       0x18b8000000000000ULL,
 4938       -1ULL,
 4939       -1ULL,
 4940       -1ULL
 4941     }
 4942 #endif
 4943   },
 4944   { "mul_hs_hs", TILEGX_OPC_MUL_HS_HS, 0x5, 3, TREG_ZERO, 1,
 4945     { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
 4946 #ifndef DISASM_ONLY
 4947     {
 4948       0xc00000007ffc0000ULL,
 4949       0ULL,
 4950       0x00000000780c0000ULL,
 4951       0ULL,
 4952       0ULL
 4953     },
 4954     {
 4955       0x0000000050d40000ULL,
 4956       -1ULL,
 4957       0x0000000068000000ULL,
 4958       -1ULL,
 4959       -1ULL
 4960     }
 4961 #endif
 4962   },
 4963   { "mul_hs_hu", TILEGX_OPC_MUL_HS_HU, 0x1, 3, TREG_ZERO, 1,
 4964     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 4965 #ifndef DISASM_ONLY
 4966     {
 4967       0xc00000007ffc0000ULL,
 4968       0ULL,
 4969       0ULL,
 4970       0ULL,
 4971       0ULL
 4972     },
 4973     {
 4974       0x0000000050d80000ULL,
 4975       -1ULL,
 4976       -1ULL,
 4977       -1ULL,
 4978       -1ULL
 4979     }
 4980 #endif
 4981   },
 4982   { "mul_hs_ls", TILEGX_OPC_MUL_HS_LS, 0x1, 3, TREG_ZERO, 1,
 4983     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 4984 #ifndef DISASM_ONLY
 4985     {
 4986       0xc00000007ffc0000ULL,
 4987       0ULL,
 4988       0ULL,
 4989       0ULL,
 4990       0ULL
 4991     },
 4992     {
 4993       0x0000000050dc0000ULL,
 4994       -1ULL,
 4995       -1ULL,
 4996       -1ULL,
 4997       -1ULL
 4998     }
 4999 #endif
 5000   },
 5001   { "mul_hs_lu", TILEGX_OPC_MUL_HS_LU, 0x1, 3, TREG_ZERO, 1,
 5002     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 5003 #ifndef DISASM_ONLY
 5004     {
 5005       0xc00000007ffc0000ULL,
 5006       0ULL,
 5007       0ULL,
 5008       0ULL,
 5009       0ULL
 5010     },
 5011     {
 5012       0x0000000050e00000ULL,
 5013       -1ULL,
 5014       -1ULL,
 5015       -1ULL,
 5016       -1ULL
 5017     }
 5018 #endif
 5019   },
 5020   { "mul_hu_hu", TILEGX_OPC_MUL_HU_HU, 0x5, 3, TREG_ZERO, 1,
 5021     { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
 5022 #ifndef DISASM_ONLY
 5023     {
 5024       0xc00000007ffc0000ULL,
 5025       0ULL,
 5026       0x00000000780c0000ULL,
 5027       0ULL,
 5028       0ULL
 5029     },
 5030     {
 5031       0x0000000050e40000ULL,
 5032       -1ULL,
 5033       0x0000000068040000ULL,
 5034       -1ULL,
 5035       -1ULL
 5036     }
 5037 #endif
 5038   },
 5039   { "mul_hu_ls", TILEGX_OPC_MUL_HU_LS, 0x1, 3, TREG_ZERO, 1,
 5040     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 5041 #ifndef DISASM_ONLY
 5042     {
 5043       0xc00000007ffc0000ULL,
 5044       0ULL,
 5045       0ULL,
 5046       0ULL,
 5047       0ULL
 5048     },
 5049     {
 5050       0x0000000050e80000ULL,
 5051       -1ULL,
 5052       -1ULL,
 5053       -1ULL,
 5054       -1ULL
 5055     }
 5056 #endif
 5057   },
 5058   { "mul_hu_lu", TILEGX_OPC_MUL_HU_LU, 0x1, 3, TREG_ZERO, 1,
 5059     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 5060 #ifndef DISASM_ONLY
 5061     {
 5062       0xc00000007ffc0000ULL,
 5063       0ULL,
 5064       0ULL,
 5065       0ULL,
 5066       0ULL
 5067     },
 5068     {
 5069       0x0000000050ec0000ULL,
 5070       -1ULL,
 5071       -1ULL,
 5072       -1ULL,
 5073       -1ULL
 5074     }
 5075 #endif
 5076   },
 5077   { "mul_ls_ls", TILEGX_OPC_MUL_LS_LS, 0x5, 3, TREG_ZERO, 1,
 5078     { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
 5079 #ifndef DISASM_ONLY
 5080     {
 5081       0xc00000007ffc0000ULL,
 5082       0ULL,
 5083       0x00000000780c0000ULL,
 5084       0ULL,
 5085       0ULL
 5086     },
 5087     {
 5088       0x0000000050f00000ULL,
 5089       -1ULL,
 5090       0x0000000068080000ULL,
 5091       -1ULL,
 5092       -1ULL
 5093     }
 5094 #endif
 5095   },
 5096   { "mul_ls_lu", TILEGX_OPC_MUL_LS_LU, 0x1, 3, TREG_ZERO, 1,
 5097     { { 8, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 5098 #ifndef DISASM_ONLY
 5099     {
 5100       0xc00000007ffc0000ULL,
 5101       0ULL,
 5102       0ULL,
 5103       0ULL,
 5104       0ULL
 5105     },
 5106     {
 5107       0x0000000050f40000ULL,
 5108       -1ULL,
 5109       -1ULL,
 5110       -1ULL,
 5111       -1ULL
 5112     }
 5113 #endif
 5114   },
 5115   { "mul_lu_lu", TILEGX_OPC_MUL_LU_LU, 0x5, 3, TREG_ZERO, 1,
 5116     { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
 5117 #ifndef DISASM_ONLY
 5118     {
 5119       0xc00000007ffc0000ULL,
 5120       0ULL,
 5121       0x00000000780c0000ULL,
 5122       0ULL,
 5123       0ULL
 5124     },
 5125     {
 5126       0x0000000050f80000ULL,
 5127       -1ULL,
 5128       0x00000000680c0000ULL,
 5129       -1ULL,
 5130       -1ULL
 5131     }
 5132 #endif
 5133   },
 5134   { "mula_hs_hs", TILEGX_OPC_MULA_HS_HS, 0x5, 3, TREG_ZERO, 1,
 5135     { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
 5136 #ifndef DISASM_ONLY
 5137     {
 5138       0xc00000007ffc0000ULL,
 5139       0ULL,
 5140       0x00000000780c0000ULL,
 5141       0ULL,
 5142       0ULL
 5143     },
 5144     {
 5145       0x0000000050a80000ULL,
 5146       -1ULL,
 5147       0x0000000070000000ULL,
 5148       -1ULL,
 5149       -1ULL
 5150     }
 5151 #endif
 5152   },
 5153   { "mula_hs_hu", TILEGX_OPC_MULA_HS_HU, 0x1, 3, TREG_ZERO, 1,
 5154     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 5155 #ifndef DISASM_ONLY
 5156     {
 5157       0xc00000007ffc0000ULL,
 5158       0ULL,
 5159       0ULL,
 5160       0ULL,
 5161       0ULL
 5162     },
 5163     {
 5164       0x0000000050ac0000ULL,
 5165       -1ULL,
 5166       -1ULL,
 5167       -1ULL,
 5168       -1ULL
 5169     }
 5170 #endif
 5171   },
 5172   { "mula_hs_ls", TILEGX_OPC_MULA_HS_LS, 0x1, 3, TREG_ZERO, 1,
 5173     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 5174 #ifndef DISASM_ONLY
 5175     {
 5176       0xc00000007ffc0000ULL,
 5177       0ULL,
 5178       0ULL,
 5179       0ULL,
 5180       0ULL
 5181     },
 5182     {
 5183       0x0000000050b00000ULL,
 5184       -1ULL,
 5185       -1ULL,
 5186       -1ULL,
 5187       -1ULL
 5188     }
 5189 #endif
 5190   },
 5191   { "mula_hs_lu", TILEGX_OPC_MULA_HS_LU, 0x1, 3, TREG_ZERO, 1,
 5192     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 5193 #ifndef DISASM_ONLY
 5194     {
 5195       0xc00000007ffc0000ULL,
 5196       0ULL,
 5197       0ULL,
 5198       0ULL,
 5199       0ULL
 5200     },
 5201     {
 5202       0x0000000050b40000ULL,
 5203       -1ULL,
 5204       -1ULL,
 5205       -1ULL,
 5206       -1ULL
 5207     }
 5208 #endif
 5209   },
 5210   { "mula_hu_hu", TILEGX_OPC_MULA_HU_HU, 0x5, 3, TREG_ZERO, 1,
 5211     { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
 5212 #ifndef DISASM_ONLY
 5213     {
 5214       0xc00000007ffc0000ULL,
 5215       0ULL,
 5216       0x00000000780c0000ULL,
 5217       0ULL,
 5218       0ULL
 5219     },
 5220     {
 5221       0x0000000050b80000ULL,
 5222       -1ULL,
 5223       0x0000000070040000ULL,
 5224       -1ULL,
 5225       -1ULL
 5226     }
 5227 #endif
 5228   },
 5229   { "mula_hu_ls", TILEGX_OPC_MULA_HU_LS, 0x1, 3, TREG_ZERO, 1,
 5230     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 5231 #ifndef DISASM_ONLY
 5232     {
 5233       0xc00000007ffc0000ULL,
 5234       0ULL,
 5235       0ULL,
 5236       0ULL,
 5237       0ULL
 5238     },
 5239     {
 5240       0x0000000050bc0000ULL,
 5241       -1ULL,
 5242       -1ULL,
 5243       -1ULL,
 5244       -1ULL
 5245     }
 5246 #endif
 5247   },
 5248   { "mula_hu_lu", TILEGX_OPC_MULA_HU_LU, 0x1, 3, TREG_ZERO, 1,
 5249     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 5250 #ifndef DISASM_ONLY
 5251     {
 5252       0xc00000007ffc0000ULL,
 5253       0ULL,
 5254       0ULL,
 5255       0ULL,
 5256       0ULL
 5257     },
 5258     {
 5259       0x0000000050c00000ULL,
 5260       -1ULL,
 5261       -1ULL,
 5262       -1ULL,
 5263       -1ULL
 5264     }
 5265 #endif
 5266   },
 5267   { "mula_ls_ls", TILEGX_OPC_MULA_LS_LS, 0x5, 3, TREG_ZERO, 1,
 5268     { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
 5269 #ifndef DISASM_ONLY
 5270     {
 5271       0xc00000007ffc0000ULL,
 5272       0ULL,
 5273       0x00000000780c0000ULL,
 5274       0ULL,
 5275       0ULL
 5276     },
 5277     {
 5278       0x0000000050c40000ULL,
 5279       -1ULL,
 5280       0x0000000070080000ULL,
 5281       -1ULL,
 5282       -1ULL
 5283     }
 5284 #endif
 5285   },
 5286   { "mula_ls_lu", TILEGX_OPC_MULA_LS_LU, 0x1, 3, TREG_ZERO, 1,
 5287     { { 23, 9, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
 5288 #ifndef DISASM_ONLY
 5289     {
 5290       0xc00000007ffc0000ULL,
 5291       0ULL,
 5292       0ULL,
 5293       0ULL,
 5294       0ULL
 5295     },
 5296     {
 5297       0x0000000050c80000ULL,
 5298       -1ULL,
 5299       -1ULL,
 5300       -1ULL,
 5301       -1ULL
 5302     }
 5303 #endif
 5304   },
 5305   { "mula_lu_lu", TILEGX_OPC_MULA_LU_LU, 0x5, 3, TREG_ZERO, 1,
 5306     { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
 5307 #ifndef DISASM_ONLY
 5308     {
 5309       0xc00000007ffc0000ULL,
 5310       0ULL,
 5311       0x00000000780c0000ULL,
 5312       0ULL,
 5313       0ULL
 5314     },
 5315     {
 5316       0x0000000050cc0000ULL,
 5317       -1ULL,
 5318       0x00000000700c0000ULL,
 5319       -1ULL,
 5320       -1ULL
 5321     }
 5322 #endif
 5323   },
 5324   { "mulax", TILEGX_OPC_MULAX, 0x5, 3, TREG_ZERO, 1,
 5325     { { 23, 9, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
 5326 #ifndef DISASM_ONLY
 5327     {
 5328       0xc00000007ffc0000ULL,
 5329       0ULL,
 5330       0x00000000780c0000ULL,
 5331       0ULL,
 5332       0ULL
 5333     },
 5334     {
 5335       0x0000000050a40000ULL,
 5336       -1ULL,
 5337       0x0000000040080000ULL,
 5338       -1ULL,
 5339       -1ULL
 5340     }
 5341 #endif
 5342   },
 5343   { "mulx", TILEGX_OPC_MULX, 0x5, 3, TREG_ZERO, 1,
 5344     { { 8, 9, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
 5345 #ifndef DISASM_ONLY
 5346     {
 5347       0xc00000007ffc0000ULL,
 5348       0ULL,
 5349       0x00000000780c0000ULL,
 5350       0ULL,
 5351       0ULL
 5352     },
 5353     {
 5354       0x0000000050d00000ULL,
 5355       -1ULL,
 5356       0x00000000400c0000ULL,
 5357       -1ULL,
 5358       -1ULL
 5359     }
 5360 #endif
 5361   },
 5362   { "mz", TILEGX_OPC_MZ, 0xf, 3, TREG_ZERO, 1,
 5363     { { 8, 9, 16 }, { 6, 7, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
 5364 #ifndef DISASM_ONLY
 5365     {
 5366       0xc00000007ffc0000ULL,
 5367       0xfffe000000000000ULL,
 5368       0x00000000780c0000ULL,
 5369       0x3c06000000000000ULL,
 5370       0ULL
 5371     },
 5372     {
 5373       0x0000000050fc0000ULL,
 5374       0x2836000000000000ULL,
 5375       0x00000000480c0000ULL,
 5376       0x2806000000000000ULL,
 5377       -1ULL
 5378     }
 5379 #endif
 5380   },
 5381   { "nap", TILEGX_OPC_NAP, 0x2, 0, TREG_ZERO, 0,
 5382     { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
 5383 #ifndef DISASM_ONLY
 5384     {
 5385       0ULL,
 5386       0xfffff80000000000ULL,
 5387       0ULL,
 5388       0ULL,
 5389       0ULL
 5390     },
 5391     {
 5392       -1ULL,
 5393       0x286b000000000000ULL,
 5394       -1ULL,
 5395