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Member "radare2-4.0.0/libr/asm/arch/amd29k/amd29k.c" (28 Oct 2019, 32422 Bytes) of package /linux/privat/radare2-4.0.0.tar.gz:


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    1 #include "amd29k.h"
    2 #include "amd29k_internal.h"
    3 #include <stdio.h>
    4 #include <string.h>
    5 #include <r_anal.h>
    6 
    7 #define CPU_ANY "*"
    8 
    9 #define N_AMD29K_INSTRUCTIONS 207
   10 
   11 #define AMD29K_GET_TYPE(x,i) ((x)->type[(i)])
   12 #define AMD29K_GET_VALUE(x,i) ((x)->operands[(i)])
   13 #define AMD29K_SET_VALUE(x,i,v,t) ((x)->operands[(i)]=(v));((x)->type[(i)]=(t))
   14 #define AMD29K_SET_INVALID(x,i) ((x)->type[(i)]=AMD29K_TYPE_UNK)
   15 #define AMD29K_HAS_BIT(x) (((x)[0] & 1))
   16 // Global registers
   17 #define AMD29K_IS_REG_GR(x) ((x)>=0&&(x)<128)
   18 // Local registers
   19 #define AMD29K_IS_REG_LR(x) ((x)>=128&&(x)<256)
   20 #define AMD29K_REGNAME(x) (AMD29K_IS_REG_GR(x)?"gr":"lr")
   21 #define AMD29K_LR(x) (AMD29K_IS_REG_GR(x)?(x):(x)-127)
   22 
   23 static void decode_ra_rb_rci(amd29k_instr_t* instruction, const ut8* buffer) {
   24     AMD29K_SET_VALUE (instruction, 0, buffer[1], AMD29K_TYPE_REG);
   25     AMD29K_SET_VALUE (instruction, 1, buffer[2], AMD29K_TYPE_REG);
   26     if (AMD29K_HAS_BIT (buffer)) {
   27         AMD29K_SET_VALUE (instruction, 2, buffer[3], AMD29K_TYPE_IMM);
   28     } else {
   29         AMD29K_SET_VALUE (instruction, 2, buffer[3], AMD29K_TYPE_REG);
   30     }
   31     AMD29K_SET_INVALID (instruction, 3);
   32     AMD29K_SET_INVALID (instruction, 4);
   33     AMD29K_SET_INVALID (instruction, 5);
   34 }
   35 
   36 static void decode_ra_rb_rc(amd29k_instr_t* instruction, const ut8* buffer) {
   37     AMD29K_SET_VALUE (instruction, 0, buffer[1], AMD29K_TYPE_REG);
   38     AMD29K_SET_VALUE (instruction, 1, buffer[2], AMD29K_TYPE_REG);
   39     AMD29K_SET_VALUE (instruction, 2, buffer[3], AMD29K_TYPE_REG);
   40     AMD29K_SET_INVALID (instruction, 3);
   41     AMD29K_SET_INVALID (instruction, 4);
   42     AMD29K_SET_INVALID (instruction, 5);
   43 }
   44 
   45 static void decode_ra_imm16(amd29k_instr_t* instruction, const ut8* buffer) {
   46     int word = (buffer[1] << 8) + buffer[3];
   47     AMD29K_SET_VALUE (instruction, 0, buffer[2], AMD29K_TYPE_REG);
   48     AMD29K_SET_VALUE (instruction, 1, word, AMD29K_TYPE_IMM);
   49     AMD29K_SET_INVALID (instruction, 2);
   50     AMD29K_SET_INVALID (instruction, 3);
   51     AMD29K_SET_INVALID (instruction, 4);
   52     AMD29K_SET_INVALID (instruction, 5);
   53 }
   54 
   55 static void decode_ra_i16_sh2(amd29k_instr_t* instruction, const ut8* buffer) {
   56     int word = (buffer[1] << 10) + (buffer[3] << 2);
   57     if (word & 0x20000) {
   58         word = (int)(0xfffc0000 | word);
   59     }
   60     AMD29K_SET_VALUE (instruction, 0, buffer[2], AMD29K_TYPE_REG);
   61     if (AMD29K_HAS_BIT (buffer)) {
   62         AMD29K_SET_VALUE (instruction, 1, word, AMD29K_TYPE_IMM);
   63     } else {
   64         AMD29K_SET_VALUE (instruction, 1, (ut32) word, AMD29K_TYPE_JMP);
   65     }
   66     AMD29K_SET_INVALID (instruction, 2);
   67     AMD29K_SET_INVALID (instruction, 3);
   68     AMD29K_SET_INVALID (instruction, 4);
   69     AMD29K_SET_INVALID (instruction, 5);
   70 }
   71 
   72 static void decode_imm16_sh2(amd29k_instr_t* instruction, const ut8* buffer) {
   73     int word = (buffer[1] << 10) + (buffer[3] << 2);
   74     if (word & 0x20000) {
   75         word = (int)(0xfffc0000 | word);
   76     }
   77     AMD29K_SET_VALUE (instruction, 0, word, AMD29K_HAS_BIT (buffer) ? AMD29K_TYPE_JMP : AMD29K_TYPE_IMM);
   78     AMD29K_SET_INVALID (instruction, 1);
   79     AMD29K_SET_INVALID (instruction, 2);
   80     AMD29K_SET_INVALID (instruction, 3);
   81     AMD29K_SET_INVALID (instruction, 4);
   82     AMD29K_SET_INVALID (instruction, 5);
   83 }
   84 
   85 static void decode_load_store(amd29k_instr_t* instruction, const ut8* buffer) {
   86     AMD29K_SET_VALUE (instruction, 0, ((buffer[1] & 0x80) >> 7), AMD29K_TYPE_IMM);
   87     AMD29K_SET_VALUE (instruction, 1, (buffer[1] & 0x7F), AMD29K_TYPE_IMM);
   88     AMD29K_SET_VALUE (instruction, 2, buffer[2], AMD29K_TYPE_REG);
   89     AMD29K_SET_VALUE (instruction, 3, buffer[3], AMD29K_HAS_BIT (buffer) ? AMD29K_TYPE_IMM : AMD29K_TYPE_REG);
   90     AMD29K_SET_INVALID (instruction, 4);
   91     AMD29K_SET_INVALID (instruction, 5);
   92 }
   93 
   94 static void decode_calli(amd29k_instr_t* instruction, const ut8* buffer) {
   95     AMD29K_SET_VALUE (instruction, 0, buffer[2], AMD29K_TYPE_REG);
   96     AMD29K_SET_VALUE (instruction, 1, buffer[3], AMD29K_TYPE_REG);
   97     AMD29K_SET_INVALID (instruction, 2);
   98     AMD29K_SET_INVALID (instruction, 3);
   99     AMD29K_SET_INVALID (instruction, 4);
  100     AMD29K_SET_INVALID (instruction, 5);
  101 }
  102 
  103 static void decode_rc_ra_imm(amd29k_instr_t* instruction, const ut8* buffer) {
  104     AMD29K_SET_VALUE (instruction, 0, buffer[1], AMD29K_TYPE_REG);
  105     AMD29K_SET_VALUE (instruction, 1, buffer[2], AMD29K_TYPE_REG);
  106     AMD29K_SET_VALUE (instruction, 2, (buffer[3] & 3), AMD29K_TYPE_IMM);
  107     AMD29K_SET_INVALID (instruction, 3);
  108     AMD29K_SET_INVALID (instruction, 4);
  109     AMD29K_SET_INVALID (instruction, 5);
  110 }
  111 
  112 static void decode_clz(amd29k_instr_t* instruction, const ut8* buffer) {
  113     AMD29K_SET_VALUE (instruction, 0, buffer[1], AMD29K_TYPE_REG);
  114     AMD29K_SET_VALUE (instruction, 1, buffer[3], AMD29K_HAS_BIT (buffer) ? AMD29K_TYPE_IMM : AMD29K_TYPE_REG);
  115     AMD29K_SET_INVALID (instruction, 2);
  116     AMD29K_SET_INVALID (instruction, 3);
  117     AMD29K_SET_INVALID (instruction, 4);
  118     AMD29K_SET_INVALID (instruction, 5);
  119 }
  120 
  121 static void decode_convert(amd29k_instr_t* instruction, const ut8* buffer) {
  122     // lambda w,ea: (w >> 24,[decode_byte1(w), decode_byte2(w), ('imm',False,(w&0x80)>>7), ('imm',False,(w&0x70)>>4), ('imm',False,(w&0xC)>>2), ('imm',False, w&3)])
  123     AMD29K_SET_VALUE (instruction, 0, buffer[1], AMD29K_TYPE_REG);
  124     AMD29K_SET_VALUE (instruction, 1, buffer[2], AMD29K_TYPE_REG);
  125     AMD29K_SET_VALUE (instruction, 2, ((buffer[3] & 0x80) >> 7), AMD29K_TYPE_IMM);
  126     AMD29K_SET_VALUE (instruction, 3, ((buffer[3] & 0x70) >> 4), AMD29K_TYPE_IMM);
  127     AMD29K_SET_VALUE (instruction, 4, ((buffer[3] & 0x0c) >> 2), AMD29K_TYPE_IMM);
  128     AMD29K_SET_VALUE (instruction, 5, (buffer[3] & 0x03), AMD29K_TYPE_IMM);
  129 }
  130 
  131 static void decode_rc_ra(amd29k_instr_t* instruction, const ut8* buffer) {
  132     AMD29K_SET_VALUE (instruction, 0, buffer[1], AMD29K_TYPE_REG);
  133     AMD29K_SET_VALUE (instruction, 1, buffer[2], AMD29K_TYPE_REG);
  134     AMD29K_SET_INVALID (instruction, 2);
  135     AMD29K_SET_INVALID (instruction, 3);
  136     AMD29K_SET_INVALID (instruction, 4);
  137     AMD29K_SET_INVALID (instruction, 5);
  138 }
  139 
  140 static void decode_dmac_fmac(amd29k_instr_t* instruction, const ut8* buffer) {
  141     AMD29K_SET_VALUE (instruction, 0, ((buffer[1] & 0x3c) >> 2), AMD29K_TYPE_IMM);
  142     AMD29K_SET_VALUE (instruction, 1, (buffer[1] & 0x03), AMD29K_TYPE_IMM);
  143     AMD29K_SET_VALUE (instruction, 2, buffer[1], AMD29K_TYPE_REG);
  144     AMD29K_SET_VALUE (instruction, 3, buffer[2], AMD29K_TYPE_REG);
  145     AMD29K_SET_INVALID (instruction, 4);
  146     AMD29K_SET_INVALID (instruction, 5);
  147 }
  148 
  149 static void decode_ra_rb(amd29k_instr_t* instruction, const ut8* buffer) {
  150     AMD29K_SET_VALUE (instruction, 0, buffer[1], AMD29K_TYPE_REG);
  151     AMD29K_SET_VALUE (instruction, 1, buffer[3], AMD29K_TYPE_REG);
  152     AMD29K_SET_INVALID (instruction, 2);
  153     AMD29K_SET_INVALID (instruction, 3);
  154     AMD29K_SET_INVALID (instruction, 4);
  155     AMD29K_SET_INVALID (instruction, 5);
  156 }
  157 
  158 static void decode_rb(amd29k_instr_t* instruction, const ut8* buffer) {
  159     AMD29K_SET_VALUE (instruction, 0, buffer[3], AMD29K_TYPE_REG);
  160     AMD29K_SET_INVALID (instruction, 1);
  161     AMD29K_SET_INVALID (instruction, 2);
  162     AMD29K_SET_INVALID (instruction, 3);
  163     AMD29K_SET_INVALID (instruction, 4);
  164     AMD29K_SET_INVALID (instruction, 5);
  165 }
  166 
  167 static void decode_rc_imm(amd29k_instr_t* instruction, const ut8* buffer) {
  168     AMD29K_SET_VALUE (instruction, 0, buffer[1], AMD29K_TYPE_REG);
  169     AMD29K_SET_VALUE (instruction, 1, ((buffer[3] & 0x0c) >> 2), AMD29K_TYPE_IMM);
  170     AMD29K_SET_VALUE (instruction, 2, (buffer[3] & 0x03), AMD29K_TYPE_IMM);
  171     AMD29K_SET_INVALID (instruction, 3);
  172     AMD29K_SET_INVALID (instruction, 4);
  173     AMD29K_SET_INVALID (instruction, 5);
  174 }
  175 
  176 static void decode_ra_imm(amd29k_instr_t* instruction, const ut8* buffer) {
  177     AMD29K_SET_VALUE (instruction, 0, buffer[2], AMD29K_TYPE_REG);
  178     AMD29K_SET_VALUE (instruction, 1, ((buffer[3] & 0x0c) >> 2), AMD29K_TYPE_IMM);
  179     AMD29K_SET_VALUE (instruction, 2, (buffer[3] & 0x03), AMD29K_TYPE_IMM);
  180     AMD29K_SET_INVALID (instruction, 3);
  181     AMD29K_SET_INVALID (instruction, 4);
  182     AMD29K_SET_INVALID (instruction, 5);
  183 }
  184 
  185 static void decode_mfsr(amd29k_instr_t* instruction, const ut8* buffer) {
  186     AMD29K_SET_VALUE (instruction, 0, buffer[1], AMD29K_TYPE_REG);
  187     AMD29K_SET_VALUE (instruction, 1, buffer[2], AMD29K_TYPE_REG);
  188     AMD29K_SET_INVALID (instruction, 2);
  189     AMD29K_SET_INVALID (instruction, 3);
  190     AMD29K_SET_INVALID (instruction, 4);
  191     AMD29K_SET_INVALID (instruction, 5);
  192 }
  193 
  194 static void decode_mtsr(amd29k_instr_t* instruction, const ut8* buffer) {
  195     AMD29K_SET_VALUE (instruction, 0, buffer[2], AMD29K_TYPE_REG);
  196     AMD29K_SET_VALUE (instruction, 1, buffer[3], AMD29K_TYPE_REG);
  197     AMD29K_SET_INVALID (instruction, 2);
  198     AMD29K_SET_INVALID (instruction, 3);
  199     AMD29K_SET_INVALID (instruction, 4);
  200     AMD29K_SET_INVALID (instruction, 5);
  201 }
  202 
  203 static void decode_none(amd29k_instr_t* instruction, const ut8* buffer) {
  204     // lambda w,ea: (w >> 24, None)
  205     AMD29K_SET_INVALID (instruction, 0);
  206     AMD29K_SET_INVALID (instruction, 1);
  207     AMD29K_SET_INVALID (instruction, 2);
  208     AMD29K_SET_INVALID (instruction, 3);
  209     AMD29K_SET_INVALID (instruction, 4);
  210     AMD29K_SET_INVALID (instruction, 5);
  211 }
  212 
  213 const amd29k_instruction_t amd29k_instructions[N_AMD29K_INSTRUCTIONS] = {
  214     { CPU_ANY,   "illegal",   R_ANAL_OP_TYPE_NULL, 0x00 , decode_none       , NULL },
  215     { CPU_ANY,   "add",       R_ANAL_OP_TYPE_ADD,  0x14 , decode_ra_rb_rci  , NULL },
  216     { CPU_ANY,   "add",       R_ANAL_OP_TYPE_ADD,  0x15 , decode_ra_rb_rci  , NULL },
  217     { CPU_ANY,   "addc",      R_ANAL_OP_TYPE_ADD,  0x1C , decode_ra_rb_rci  , NULL },
  218     { CPU_ANY,   "addc",      R_ANAL_OP_TYPE_ADD,  0x1D , decode_ra_rb_rci  , NULL },
  219     { CPU_ANY,   "addcs",     R_ANAL_OP_TYPE_ADD,  0x18 , decode_ra_rb_rci  , NULL },
  220     { CPU_ANY,   "addcs",     R_ANAL_OP_TYPE_ADD,  0x19 , decode_ra_rb_rci  , NULL },
  221     { CPU_ANY,   "addcu",     R_ANAL_OP_TYPE_ADD,  0x1A , decode_ra_rb_rci  , NULL },
  222     { CPU_ANY,   "addcu",     R_ANAL_OP_TYPE_ADD,  0x1B , decode_ra_rb_rci  , NULL },
  223     { CPU_ANY,   "adds",      R_ANAL_OP_TYPE_ADD,  0x10 , decode_ra_rb_rci  , NULL },
  224     { CPU_ANY,   "adds",      R_ANAL_OP_TYPE_ADD,  0x11 , decode_ra_rb_rci  , NULL },
  225     { CPU_ANY,   "addu",      R_ANAL_OP_TYPE_ADD,  0x12 , decode_ra_rb_rci  , NULL },
  226     { CPU_ANY,   "addu",      R_ANAL_OP_TYPE_ADD,  0x13 , decode_ra_rb_rci  , NULL },
  227     { CPU_ANY,   "and",       R_ANAL_OP_TYPE_AND,  0x90 , decode_ra_rb_rci  , NULL },
  228     { CPU_ANY,   "and",       R_ANAL_OP_TYPE_AND,  0x91 , decode_ra_rb_rci  , NULL },
  229     { CPU_ANY,   "andn",      R_ANAL_OP_TYPE_AND,  0x9C , decode_ra_rb_rci  , NULL },
  230     { CPU_ANY,   "andn",      R_ANAL_OP_TYPE_AND,  0x9D , decode_ra_rb_rci  , NULL },
  231     { CPU_ANY,   "aseq",      R_ANAL_OP_TYPE_CMP,  0x70 , decode_ra_rb_rci  , NULL },
  232     { CPU_ANY,   "asge",      R_ANAL_OP_TYPE_CMP,  0x5C , decode_ra_rb_rci  , NULL },
  233     { CPU_ANY,   "asge",      R_ANAL_OP_TYPE_CMP,  0x5D , decode_ra_rb_rci  , NULL },
  234     { CPU_ANY,   "asgeu",     R_ANAL_OP_TYPE_CMP,  0x5E , decode_ra_rb_rci  , NULL },
  235     { CPU_ANY,   "asgeu",     R_ANAL_OP_TYPE_CMP,  0x5F , decode_ra_rb_rci  , NULL },
  236     { CPU_ANY,   "asgt",      R_ANAL_OP_TYPE_CMP,  0x58 , decode_ra_rb_rci  , NULL },
  237     { CPU_ANY,   "asgt",      R_ANAL_OP_TYPE_CMP,  0x59 , decode_ra_rb_rci  , NULL },
  238     { CPU_ANY,   "asgtu",     R_ANAL_OP_TYPE_CMP,  0x5A , decode_ra_rb_rci  , NULL },
  239     { CPU_ANY,   "asgtu",     R_ANAL_OP_TYPE_CMP,  0x5B , decode_ra_rb_rci  , NULL },
  240     { CPU_ANY,   "asle",      R_ANAL_OP_TYPE_CMP,  0x54 , decode_ra_rb_rci  , NULL },
  241     { CPU_ANY,   "asle",      R_ANAL_OP_TYPE_CMP,  0x55 , decode_ra_rb_rci  , NULL },
  242     { CPU_ANY,   "asleu",     R_ANAL_OP_TYPE_CMP,  0x56 , decode_ra_rb_rci  , NULL },
  243     { CPU_ANY,   "asleu",     R_ANAL_OP_TYPE_CMP,  0x57 , decode_ra_rb_rci  , NULL },
  244     { CPU_ANY,   "aslt",      R_ANAL_OP_TYPE_CMP,  0x50 , decode_ra_rb_rci  , NULL },
  245     { CPU_ANY,   "aslt",      R_ANAL_OP_TYPE_CMP,  0x51 , decode_ra_rb_rci  , NULL },
  246     { CPU_ANY,   "asltu",     R_ANAL_OP_TYPE_CMP,  0x52 , decode_ra_rb_rci  , NULL },
  247     { CPU_ANY,   "asltu",     R_ANAL_OP_TYPE_CMP,  0x53 , decode_ra_rb_rci  , NULL },
  248     { CPU_ANY,   "asneq",     R_ANAL_OP_TYPE_CMP,  0x72 , decode_ra_rb_rci  , NULL },
  249     { CPU_ANY,   "asneq",     R_ANAL_OP_TYPE_CMP,  0x73 , decode_ra_rb_rci  , NULL },
  250     { CPU_ANY,   "call",      R_ANAL_OP_TYPE_CALL, 0xA8 , decode_ra_i16_sh2 , NULL },
  251     { CPU_ANY,   "call",      R_ANAL_OP_TYPE_CALL, 0xA9 , decode_ra_i16_sh2 , NULL },
  252     { CPU_ANY,   "calli",    R_ANAL_OP_TYPE_ICALL, 0xC8 , decode_calli      , NULL },
  253     { CPU_29050, "class",     R_ANAL_OP_TYPE_NULL, 0xE6 , decode_rc_ra_imm  , NULL },
  254     { CPU_ANY,   "clz",       R_ANAL_OP_TYPE_NULL, 0x08 , decode_clz        , NULL },
  255     { CPU_ANY,   "clz",       R_ANAL_OP_TYPE_NULL, 0x09 , decode_clz        , NULL },
  256     { CPU_ANY,   "const",     R_ANAL_OP_TYPE_MOV,  0x03 , decode_ra_imm16   , NULL },
  257     { CPU_ANY,   "consth",    R_ANAL_OP_TYPE_MOV,  0x02 , decode_ra_imm16   , NULL },
  258     { CPU_ANY,   "consthz",   R_ANAL_OP_TYPE_MOV,  0x05 , decode_ra_imm16   , NULL },
  259     { CPU_ANY,   "constn",    R_ANAL_OP_TYPE_MOV,  0x01 , decode_ra_imm16   , NULL },
  260     { CPU_29050, "convert",   R_ANAL_OP_TYPE_NULL, 0xE4 , decode_convert    , NULL },
  261     { CPU_ANY,   "cpbyte",    R_ANAL_OP_TYPE_CMP,  0x2E , decode_ra_rb_rci  , NULL },
  262     { CPU_ANY,   "cpbyte",    R_ANAL_OP_TYPE_CMP,  0x2F , decode_ra_rb_rci  , NULL },
  263     { CPU_ANY,   "cpeq",      R_ANAL_OP_TYPE_CMP,  0x60 , decode_ra_rb_rci  , NULL },
  264     { CPU_ANY,   "cpeq",      R_ANAL_OP_TYPE_CMP,  0x61 , decode_ra_rb_rci  , NULL },
  265     { CPU_ANY,   "cpge",      R_ANAL_OP_TYPE_CMP,  0x4C , decode_ra_rb_rci  , NULL },
  266     { CPU_ANY,   "cpge",      R_ANAL_OP_TYPE_CMP,  0x4D , decode_ra_rb_rci  , NULL },
  267     { CPU_ANY,   "cpgeu",     R_ANAL_OP_TYPE_CMP,  0x4E , decode_ra_rb_rci  , NULL },
  268     { CPU_ANY,   "cpgeu",     R_ANAL_OP_TYPE_CMP,  0x4F , decode_ra_rb_rci  , NULL },
  269     { CPU_ANY,   "cpgt",      R_ANAL_OP_TYPE_CMP,  0x48 , decode_ra_rb_rci  , NULL },
  270     { CPU_ANY,   "cpgt",      R_ANAL_OP_TYPE_CMP,  0x49 , decode_ra_rb_rci  , NULL },
  271     { CPU_ANY,   "cpgtu",     R_ANAL_OP_TYPE_CMP,  0x4A , decode_ra_rb_rci  , NULL },
  272     { CPU_ANY,   "cpgtu",     R_ANAL_OP_TYPE_CMP,  0x4B , decode_ra_rb_rci  , NULL },
  273     { CPU_ANY,   "cple",      R_ANAL_OP_TYPE_CMP,  0x44 , decode_ra_rb_rci  , NULL },
  274     { CPU_ANY,   "cple",      R_ANAL_OP_TYPE_CMP,  0x45 , decode_ra_rb_rci  , NULL },
  275     { CPU_ANY,   "cpleu",     R_ANAL_OP_TYPE_CMP,  0x46 , decode_ra_rb_rci  , NULL },
  276     { CPU_ANY,   "cpleu",     R_ANAL_OP_TYPE_CMP,  0x47 , decode_ra_rb_rci  , NULL },
  277     { CPU_ANY,   "cplt",      R_ANAL_OP_TYPE_CMP,  0x40 , decode_ra_rb_rci  , NULL },
  278     { CPU_ANY,   "cplt",      R_ANAL_OP_TYPE_CMP,  0x41 , decode_ra_rb_rci  , NULL },
  279     { CPU_ANY,   "cpltu",     R_ANAL_OP_TYPE_CMP,  0x42 , decode_ra_rb_rci  , NULL },
  280     { CPU_ANY,   "cpltu",     R_ANAL_OP_TYPE_CMP,  0x43 , decode_ra_rb_rci  , NULL },
  281     { CPU_ANY,   "cpneq",     R_ANAL_OP_TYPE_CMP,  0x62 , decode_ra_rb_rci  , NULL },
  282     { CPU_ANY,   "cpneq",     R_ANAL_OP_TYPE_CMP,  0x63 , decode_ra_rb_rci  , NULL },
  283     { CPU_29000, "cvdf",      R_ANAL_OP_TYPE_NULL, 0xE9 , decode_rc_ra      , NULL },
  284     { CPU_29000, "cvdint",    R_ANAL_OP_TYPE_NULL, 0xE7 , decode_rc_ra      , NULL },
  285     { CPU_29000, "cvfd",      R_ANAL_OP_TYPE_NULL, 0xE8 , decode_rc_ra      , NULL },
  286     { CPU_29000, "cvfint",    R_ANAL_OP_TYPE_NULL, 0xE6 , decode_rc_ra      , NULL },
  287     { CPU_29000, "cvintd",    R_ANAL_OP_TYPE_NULL, 0xE5 , decode_rc_ra      , NULL },
  288     { CPU_29000, "cvintf",    R_ANAL_OP_TYPE_NULL, 0xE4 , decode_rc_ra      , NULL },
  289     { CPU_ANY,   "dadd",      R_ANAL_OP_TYPE_NULL, 0xF1 , decode_ra_rb_rc   , NULL },
  290     { CPU_ANY,   "ddiv",      R_ANAL_OP_TYPE_DIV,  0xF7 , decode_ra_rb_rc   , NULL },
  291     { CPU_ANY,   "deq",       R_ANAL_OP_TYPE_CMP,  0xEB , decode_ra_rb_rc   , NULL },
  292     { CPU_29050, "dge",       R_ANAL_OP_TYPE_CMP,  0xEF , decode_ra_rb_rc   , NULL },
  293     { CPU_ANY,   "dgt",       R_ANAL_OP_TYPE_CMP,  0xED , decode_ra_rb_rc   , NULL },
  294     { CPU_ANY,   "div",       R_ANAL_OP_TYPE_DIV,  0x6A , decode_ra_rb_rci  , NULL },
  295     { CPU_ANY,   "div",       R_ANAL_OP_TYPE_DIV,  0x6B , decode_ra_rb_rci  , NULL },
  296     { CPU_ANY,   "div0",      R_ANAL_OP_TYPE_DIV,  0x68 , decode_ra_rb_rci  , NULL },
  297     { CPU_ANY,   "div0",      R_ANAL_OP_TYPE_DIV,  0x69 , decode_ra_rb_rci  , NULL },
  298     { CPU_ANY,   "divide",    R_ANAL_OP_TYPE_DIV,  0xE1 , decode_ra_rb_rc   , NULL },
  299     { CPU_29050, "dividu",    R_ANAL_OP_TYPE_DIV,  0xE3 , decode_ra_rb_rc   , NULL },
  300     { CPU_ANY,   "divl",      R_ANAL_OP_TYPE_DIV,  0x6C , decode_ra_rb_rci  , NULL },
  301     { CPU_ANY,   "divl",      R_ANAL_OP_TYPE_DIV,  0x6D , decode_ra_rb_rci  , NULL },
  302     { CPU_ANY,   "divrem",    R_ANAL_OP_TYPE_DIV,  0x6E , decode_ra_rb_rci  , NULL },
  303     { CPU_ANY,   "divrem",    R_ANAL_OP_TYPE_DIV,  0x6F , decode_ra_rb_rci  , NULL },
  304     { CPU_29000, "dlt",       R_ANAL_OP_TYPE_CMP,  0xEF , decode_ra_rb_rc   , NULL },
  305     { CPU_29050, "dmac",      R_ANAL_OP_TYPE_NULL, 0xD9 , decode_dmac_fmac  , NULL },
  306     { CPU_29050, "dmsm",      R_ANAL_OP_TYPE_NULL, 0xDB , decode_ra_rb_rc   , NULL },
  307     { CPU_ANY,   "dmul",      R_ANAL_OP_TYPE_MUL,  0xF5 , decode_ra_rb_rc   , NULL },
  308     { CPU_ANY,   "dsub",      R_ANAL_OP_TYPE_SUB,  0xF3 , decode_ra_rb_rc   , NULL },
  309     { CPU_ANY,   "emulate",   R_ANAL_OP_TYPE_NULL, 0xF8 , decode_ra_rb_rci  , NULL },
  310     { CPU_ANY,   "exbyte",    R_ANAL_OP_TYPE_NULL, 0x0A , decode_ra_rb_rci  , NULL },
  311     { CPU_ANY,   "exbyte",    R_ANAL_OP_TYPE_NULL, 0x0B , decode_ra_rb_rci  , NULL },
  312     { CPU_ANY,   "exhw",      R_ANAL_OP_TYPE_NULL, 0x7C , decode_ra_rb_rci  , NULL },
  313     { CPU_ANY,   "exhw",      R_ANAL_OP_TYPE_NULL, 0x7D , decode_ra_rb_rci  , NULL },
  314     { CPU_ANY,   "exhws",     R_ANAL_OP_TYPE_NULL, 0x7E , decode_rc_ra      , NULL },
  315     { CPU_ANY,   "extract",   R_ANAL_OP_TYPE_NULL, 0x7A , decode_ra_rb_rci  , NULL },
  316     { CPU_ANY,   "extract",   R_ANAL_OP_TYPE_NULL, 0x7B , decode_ra_rb_rci  , NULL },
  317     { CPU_ANY,   "fadd",      R_ANAL_OP_TYPE_ADD,  0xF0 , decode_ra_rb_rc   , NULL },
  318     { CPU_ANY,   "fdiv",      R_ANAL_OP_TYPE_DIV,  0xF6 , decode_ra_rb_rc   , NULL },
  319     { CPU_29050, "fdmul",     R_ANAL_OP_TYPE_MUL,  0xF9 , decode_ra_rb_rc   , NULL },
  320     { CPU_ANY,   "feq",       R_ANAL_OP_TYPE_CMP,  0xEA , decode_ra_rb_rc   , NULL },
  321     { CPU_29050, "fge",       R_ANAL_OP_TYPE_CMP,  0xEE , decode_ra_rb_rc   , NULL },
  322     { CPU_ANY,   "fgt",       R_ANAL_OP_TYPE_CMP,  0xEC , decode_ra_rb_rc   , NULL },
  323     { CPU_29000, "flt",       R_ANAL_OP_TYPE_CMP,  0xEE , decode_ra_rb_rc   , NULL },
  324     { CPU_29050, "fmac",      R_ANAL_OP_TYPE_NULL, 0xD8 , decode_dmac_fmac  , NULL },
  325     { CPU_29050, "fmsm",      R_ANAL_OP_TYPE_NULL, 0xDA , decode_ra_rb_rc   , NULL },
  326     { CPU_ANY,   "fmul",      R_ANAL_OP_TYPE_MUL,  0xF4 , decode_ra_rb_rc   , NULL },
  327     { CPU_ANY,   "fsub",      R_ANAL_OP_TYPE_SUB,  0xF2 , decode_ra_rb_rc   , NULL },
  328     { CPU_ANY,   "halt",      R_ANAL_OP_TYPE_RET,  0x89 , decode_none       , NULL },
  329     { CPU_ANY,   "inbyte",    R_ANAL_OP_TYPE_NULL, 0x0C , decode_ra_rb_rci  , NULL },
  330     { CPU_ANY,   "inbyte",    R_ANAL_OP_TYPE_NULL, 0x0D , decode_ra_rb_rci  , NULL },
  331     { CPU_ANY,   "inhw",      R_ANAL_OP_TYPE_NULL, 0x78 , decode_ra_rb_rci  , NULL },
  332     { CPU_ANY,   "inhw",      R_ANAL_OP_TYPE_NULL, 0x79 , decode_ra_rb_rci  , NULL },
  333     { CPU_ANY,   "inv",       R_ANAL_OP_TYPE_NULL, 0x9F , decode_none       , NULL },
  334     { CPU_ANY,   "iret",      R_ANAL_OP_TYPE_RET,  0x88 , decode_none       , NULL },
  335     { CPU_ANY,   "iretinv",   R_ANAL_OP_TYPE_RET,  0x8C , decode_none       , NULL },
  336     { CPU_ANY,   "jmp",       R_ANAL_OP_TYPE_JMP,  0xA0 , decode_imm16_sh2  , NULL },
  337     { CPU_ANY,   "jmp",       R_ANAL_OP_TYPE_JMP,  0xA1 , decode_imm16_sh2  , NULL },
  338     { CPU_ANY,   "jmpf",      R_ANAL_OP_TYPE_CJMP, 0xA4 , decode_ra_i16_sh2 , NULL },
  339     { CPU_ANY,   "jmpf",      R_ANAL_OP_TYPE_CJMP, 0xA5 , decode_ra_i16_sh2 , NULL },
  340     { CPU_ANY,   "jmpfdec",   R_ANAL_OP_TYPE_CJMP, 0xB4 , decode_ra_i16_sh2 , NULL },
  341     { CPU_ANY,   "jmpfdec",   R_ANAL_OP_TYPE_CJMP, 0xB5 , decode_ra_i16_sh2 , NULL },
  342     { CPU_ANY,   "jmpfi",    R_ANAL_OP_TYPE_RCJMP, 0xC4 , decode_ra_rb      , NULL },
  343     { CPU_ANY,   "jmpi",      R_ANAL_OP_TYPE_RJMP, 0xC0 , decode_rb         , NULL },
  344     { CPU_ANY,   "jmpt",      R_ANAL_OP_TYPE_CJMP, 0xAC , decode_ra_i16_sh2 , NULL },
  345     { CPU_ANY,   "jmpti",    R_ANAL_OP_TYPE_RCJMP, 0xCC , decode_ra_rb      , NULL },
  346     { CPU_29050, "mfacc",     R_ANAL_OP_TYPE_NULL, 0xE9 , decode_rc_imm     , NULL },
  347     { CPU_29050, "mtacc",     R_ANAL_OP_TYPE_NULL, 0xE8 , decode_ra_imm     , NULL },
  348     { CPU_ANY,   "mfsr",      R_ANAL_OP_TYPE_NULL, 0xC6 , decode_mfsr       , NULL },
  349     { CPU_ANY,   "mftlb",     R_ANAL_OP_TYPE_NULL, 0xB6 , decode_rc_ra      , NULL },
  350     { CPU_ANY,   "mtsr",      R_ANAL_OP_TYPE_NULL, 0xCE , decode_mtsr       , NULL },
  351     { CPU_ANY,   "mtsrim",    R_ANAL_OP_TYPE_NULL, 0x04 , decode_ra_imm16   , NULL },
  352     { CPU_ANY,   "mttlb",     R_ANAL_OP_TYPE_NULL, 0xBE , decode_ra_rb      , NULL },
  353     { CPU_ANY,   "mul",       R_ANAL_OP_TYPE_MUL,  0x64 , decode_ra_rb_rci  , NULL },
  354     { CPU_ANY,   "mul",       R_ANAL_OP_TYPE_MUL,  0x65 , decode_ra_rb_rci  , NULL },
  355     { CPU_ANY,   "mull",      R_ANAL_OP_TYPE_MUL,  0x66 , decode_ra_rb_rci  , NULL },
  356     { CPU_ANY,   "mull",      R_ANAL_OP_TYPE_MUL,  0x67 , decode_ra_rb_rci  , NULL },
  357     { CPU_29050, "multiplu",  R_ANAL_OP_TYPE_MUL,  0xE2 , decode_ra_rb_rc   , NULL },
  358     { CPU_ANY,   "multiply",  R_ANAL_OP_TYPE_MUL,  0xE0 , decode_ra_rb_rc   , NULL },
  359     { CPU_29050, "multm",     R_ANAL_OP_TYPE_MUL,  0xDE , decode_ra_rb_rc   , NULL },
  360     { CPU_29050, "multmu",    R_ANAL_OP_TYPE_MUL,  0xDF , decode_ra_rb_rc   , NULL },
  361     { CPU_ANY,   "mulu",      R_ANAL_OP_TYPE_MUL,  0x74 , decode_ra_rb_rci  , NULL },
  362     { CPU_ANY,   "mulu",      R_ANAL_OP_TYPE_MUL,  0x75 , decode_ra_rb_rci  , NULL },
  363     { CPU_ANY,   "nand",      R_ANAL_OP_TYPE_AND,  0x9A , decode_ra_rb_rci  , NULL },
  364     { CPU_ANY,   "nand",      R_ANAL_OP_TYPE_AND,  0x9B , decode_ra_rb_rci  , NULL },
  365     { CPU_ANY,   "nor",       R_ANAL_OP_TYPE_NOR,  0x98 , decode_ra_rb_rci  , NULL },
  366     { CPU_ANY,   "nor",       R_ANAL_OP_TYPE_NOR,  0x99 , decode_ra_rb_rci  , NULL },
  367     { CPU_ANY,   "or",        R_ANAL_OP_TYPE_OR,   0x92 , decode_ra_rb_rci  , NULL },
  368     { CPU_ANY,   "or",        R_ANAL_OP_TYPE_OR,   0x93 , decode_ra_rb_rci  , NULL },
  369     { CPU_29050, "orn",       R_ANAL_OP_TYPE_OR,   0xAA , decode_ra_rb_rci  , NULL },
  370     { CPU_29050, "orn",       R_ANAL_OP_TYPE_OR,   0xAB , decode_ra_rb_rci  , NULL },
  371     { CPU_ANY,   "setip",     R_ANAL_OP_TYPE_NULL, 0x9E , decode_ra_rb_rc   , NULL },
  372     { CPU_ANY,   "sll",       R_ANAL_OP_TYPE_SHL,  0x80 , decode_ra_rb_rci  , NULL },
  373     { CPU_ANY,   "sll",       R_ANAL_OP_TYPE_SHL,  0x81 , decode_ra_rb_rci  , NULL },
  374     { CPU_29050, "sqrt",      R_ANAL_OP_TYPE_NULL, 0xE5 , decode_rc_ra_imm  , NULL },
  375     { CPU_ANY,   "sra",       R_ANAL_OP_TYPE_SHR,  0x86 , decode_ra_rb_rci  , NULL },
  376     { CPU_ANY,   "sra",       R_ANAL_OP_TYPE_SHR,  0x87 , decode_ra_rb_rci  , NULL },
  377     { CPU_ANY,   "srl",       R_ANAL_OP_TYPE_SAL, 0x82 , decode_ra_rb_rci  , NULL },
  378     { CPU_ANY,   "srl",       R_ANAL_OP_TYPE_SAL, 0x83 , decode_ra_rb_rci  , NULL },
  379     { CPU_ANY,   "load",      R_ANAL_OP_TYPE_LOAD, 0x16 , decode_load_store , NULL },
  380     { CPU_ANY,   "load",      R_ANAL_OP_TYPE_LOAD, 0x17 , decode_load_store , NULL },
  381     { CPU_ANY,   "loadl",     R_ANAL_OP_TYPE_LOAD, 0x06 , decode_load_store , NULL },
  382     { CPU_ANY,   "loadl",     R_ANAL_OP_TYPE_LOAD, 0x07 , decode_load_store , NULL },
  383     { CPU_ANY,   "loadm",     R_ANAL_OP_TYPE_LOAD, 0x36 , decode_load_store , NULL },
  384     { CPU_ANY,   "loadm",     R_ANAL_OP_TYPE_LOAD, 0x37 , decode_load_store , NULL },
  385     { CPU_ANY,   "loadset",   R_ANAL_OP_TYPE_LOAD, 0x26 , decode_load_store , NULL },
  386     { CPU_ANY,   "loadset",   R_ANAL_OP_TYPE_LOAD, 0x27 , decode_load_store , NULL },
  387     { CPU_ANY,   "store",    R_ANAL_OP_TYPE_STORE, 0x1E , decode_load_store , NULL },
  388     { CPU_ANY,   "store",    R_ANAL_OP_TYPE_STORE, 0x1F , decode_load_store , NULL },
  389     { CPU_ANY,   "storel",   R_ANAL_OP_TYPE_STORE, 0x0E , decode_load_store , NULL },
  390     { CPU_ANY,   "storel",   R_ANAL_OP_TYPE_STORE, 0x0F , decode_load_store , NULL },
  391     { CPU_ANY,   "storem",   R_ANAL_OP_TYPE_STORE, 0x3E , decode_load_store , NULL },
  392     { CPU_ANY,   "storem",   R_ANAL_OP_TYPE_STORE, 0x3F , decode_load_store , NULL },
  393     { CPU_ANY,   "sub",       R_ANAL_OP_TYPE_SUB,  0x24 , decode_ra_rb_rci  , NULL },
  394     { CPU_ANY,   "sub",       R_ANAL_OP_TYPE_SUB,  0x25 , decode_ra_rb_rci  , NULL },
  395     { CPU_ANY,   "subc",      R_ANAL_OP_TYPE_SUB,  0x2C , decode_ra_rb_rci  , NULL },
  396     { CPU_ANY,   "subc",      R_ANAL_OP_TYPE_SUB,  0x2D , decode_ra_rb_rci  , NULL },
  397     { CPU_ANY,   "subcs",     R_ANAL_OP_TYPE_SUB,  0x28 , decode_ra_rb_rci  , NULL },
  398     { CPU_ANY,   "subcs",     R_ANAL_OP_TYPE_SUB,  0x29 , decode_ra_rb_rci  , NULL },
  399     { CPU_ANY,   "subcu",     R_ANAL_OP_TYPE_SUB,  0x2A , decode_ra_rb_rci  , NULL },
  400     { CPU_ANY,   "subcu",     R_ANAL_OP_TYPE_SUB,  0x2B , decode_ra_rb_rci  , NULL },
  401     { CPU_ANY,   "subr",      R_ANAL_OP_TYPE_SUB,  0x34 , decode_ra_rb_rci  , NULL },
  402     { CPU_ANY,   "subr",      R_ANAL_OP_TYPE_SUB,  0x35 , decode_ra_rb_rci  , NULL },
  403     { CPU_ANY,   "subrc",     R_ANAL_OP_TYPE_SUB,  0x3C , decode_ra_rb_rci  , NULL },
  404     { CPU_ANY,   "subrc",     R_ANAL_OP_TYPE_SUB,  0x3D , decode_ra_rb_rci  , NULL },
  405     { CPU_ANY,   "subrcs",    R_ANAL_OP_TYPE_SUB,  0x38 , decode_ra_rb_rci  , NULL },
  406     { CPU_ANY,   "subrcs",    R_ANAL_OP_TYPE_SUB,  0x39 , decode_ra_rb_rci  , NULL },
  407     { CPU_ANY,   "subrcu",    R_ANAL_OP_TYPE_SUB,  0x3A , decode_ra_rb_rci  , NULL },
  408     { CPU_ANY,   "subrcu",    R_ANAL_OP_TYPE_SUB,  0x3B , decode_ra_rb_rci  , NULL },
  409     { CPU_ANY,   "subrs",     R_ANAL_OP_TYPE_SUB,  0x30 , decode_ra_rb_rci  , NULL },
  410     { CPU_ANY,   "subrs",     R_ANAL_OP_TYPE_SUB,  0x31 , decode_ra_rb_rci  , NULL },
  411     { CPU_ANY,   "subru",     R_ANAL_OP_TYPE_SUB,  0x32 , decode_ra_rb_rci  , NULL },
  412     { CPU_ANY,   "subru",     R_ANAL_OP_TYPE_SUB,  0x33 , decode_ra_rb_rci  , NULL },
  413     { CPU_ANY,   "subs",      R_ANAL_OP_TYPE_SUB,  0x20 , decode_ra_rb_rci  , NULL },
  414     { CPU_ANY,   "subs",      R_ANAL_OP_TYPE_SUB,  0x21 , decode_ra_rb_rci  , NULL },
  415     { CPU_ANY,   "subu",      R_ANAL_OP_TYPE_SUB,  0x22 , decode_ra_rb_rci  , NULL },
  416     { CPU_ANY,   "subu",      R_ANAL_OP_TYPE_SUB,  0x23 , decode_ra_rb_rci  , NULL },
  417     { CPU_ANY,   "xnor",      R_ANAL_OP_TYPE_XOR,  0x96 , decode_ra_rb_rci  , NULL },
  418     { CPU_ANY,   "xnor",      R_ANAL_OP_TYPE_XOR,  0x97 , decode_ra_rb_rci  , NULL },
  419     { CPU_ANY,   "xor",       R_ANAL_OP_TYPE_XOR,  0x94 , decode_ra_rb_rci  , NULL },
  420     { CPU_ANY,   "xor",       R_ANAL_OP_TYPE_XOR,  0x95 , decode_ra_rb_rci  , NULL },
  421 };
  422 
  423 bool amd29k_instr_decode(const ut8* buffer, const ut32 buffer_size, amd29k_instr_t* instruction, const char* cpu) {
  424     if (!buffer || buffer_size < 4 || !instruction || (cpu && strlen (cpu) < 5)) {
  425         return false;
  426     }
  427     if (!cpu) {
  428         cpu = CPU_29000;
  429     }
  430     if (buffer[0] == 0x70 && buffer[1] == 0x40 && buffer[2] == 0x01 && buffer[3] == 0x01) {
  431         decode_none (instruction, buffer);
  432         instruction->mnemonic = "nop";
  433         instruction->op_type = R_ANAL_OP_TYPE_NOP;
  434         return true;
  435     }
  436     int i;
  437     for (i = 0; i < N_AMD29K_INSTRUCTIONS; i++) {
  438         const amd29k_instruction_t *in = &amd29k_instructions[i];
  439         if (in->cpu[0] == '*' && in->mask == buffer[0]) {
  440             in->decode (instruction, buffer);
  441             instruction->mnemonic = in->mnemonic;
  442             instruction->op_type = in->op_type;
  443             return true;
  444         } else if (in->cpu[0] != '*' && in->cpu[3] == '0' && in->mask == buffer[0]) {
  445             in->decode (instruction, buffer);
  446             instruction->mnemonic = in->mnemonic;
  447             instruction->op_type = in->op_type;
  448             return true;
  449         } else if (in->cpu[0] != '*' && in->cpu[3] == '5' && in->mask == buffer[0]) {
  450             in->decode (instruction, buffer);
  451             instruction->mnemonic = in->mnemonic;
  452             instruction->op_type = in->op_type;
  453             return true;
  454         }
  455     }
  456     return false;
  457 }
  458 
  459 #define AMD29K_IS_6(a,b,c,d,e,f) (t0==(a)&&t1==(b)&&t2==(c)&&t3==(d)&&t4==(e)&&t5==(f))
  460 #define AMD29K_IS_1(a) AMD29K_IS_6(a,(AMD29K_TYPE_UNK),(AMD29K_TYPE_UNK),(AMD29K_TYPE_UNK),(AMD29K_TYPE_UNK),(AMD29K_TYPE_UNK))
  461 #define AMD29K_IS_2(a,b) AMD29K_IS_6(a,b,(AMD29K_TYPE_UNK),(AMD29K_TYPE_UNK),(AMD29K_TYPE_UNK),(AMD29K_TYPE_UNK))
  462 #define AMD29K_IS_3(a,b,c) AMD29K_IS_6(a,b,c,(AMD29K_TYPE_UNK),(AMD29K_TYPE_UNK),(AMD29K_TYPE_UNK))
  463 #define AMD29K_IS_4(a,b,c,d) AMD29K_IS_6(a,b,c,d,(AMD29K_TYPE_UNK),(AMD29K_TYPE_UNK))
  464 #define AMD29K_IS_5(a,b,c,d,e) AMD29K_IS_6(a,b,c,d,e,(AMD29K_TYPE_UNK))
  465 
  466 bool amd29k_instr_is_ret(amd29k_instr_t* instruction) {
  467     if (instruction && !strcmp (instruction->mnemonic, "calli") && instruction->operands[0] == 128 && instruction->operands[1] == 128) {
  468         return true;
  469     }
  470     return false;
  471 }
  472 
  473 
  474 ut64 amd29k_instr_jump(ut64 address, amd29k_instr_t* instruction) {
  475     if (!instruction) {
  476         return UT64_MAX;
  477     }
  478     int t0 = AMD29K_GET_TYPE (instruction, 0);
  479     int t1 = AMD29K_GET_TYPE (instruction, 1);
  480     int t2 = AMD29K_GET_TYPE (instruction, 2);
  481     int t3 = AMD29K_GET_TYPE (instruction, 3);
  482     int t4 = AMD29K_GET_TYPE (instruction, 4);
  483     int t5 = AMD29K_GET_TYPE (instruction, 5);
  484 
  485     int v0 = AMD29K_GET_VALUE (instruction, 0);
  486     int v1 = AMD29K_GET_VALUE (instruction, 1);
  487     if (AMD29K_IS_1 (AMD29K_TYPE_JMP)) {
  488         return address + ((int) v0);
  489     } else if (AMD29K_IS_2 (AMD29K_TYPE_REG, AMD29K_TYPE_JMP)) {
  490         return address + ((int) v1);
  491     }
  492     return UT64_MAX;
  493 }
  494 
  495 void amd29k_instr_print(char* string, int string_size, ut64 address, amd29k_instr_t* instruction) {
  496     if (!string || string_size < 0 || !instruction) {
  497         return;
  498     }
  499     int t0 = AMD29K_GET_TYPE (instruction, 0);
  500     int t1 = AMD29K_GET_TYPE (instruction, 1);
  501     int t2 = AMD29K_GET_TYPE (instruction, 2);
  502     int t3 = AMD29K_GET_TYPE (instruction, 3);
  503     int t4 = AMD29K_GET_TYPE (instruction, 4);
  504     int t5 = AMD29K_GET_TYPE (instruction, 5);
  505 
  506     int v0 = AMD29K_GET_VALUE (instruction, 0);
  507     int v1 = AMD29K_GET_VALUE (instruction, 1);
  508     int v2 = AMD29K_GET_VALUE (instruction, 2);
  509     int v3 = AMD29K_GET_VALUE (instruction, 3);
  510     int v4 = AMD29K_GET_VALUE (instruction, 4);
  511     int v5 = AMD29K_GET_VALUE (instruction, 5);
  512 
  513     if (AMD29K_IS_1 (AMD29K_TYPE_REG)) {
  514         const char* p0 = AMD29K_REGNAME (v0);
  515         snprintf(string, string_size, "%s %s%d", instruction->mnemonic, p0, AMD29K_LR (v0));
  516 
  517     } else if (AMD29K_IS_1 (AMD29K_TYPE_IMM)) {
  518         if (v0 >= 0) {
  519             snprintf(string, string_size, "%s 0x%x", instruction->mnemonic, v0);
  520         } else {
  521             v0 = 0 - v0;
  522             snprintf(string, string_size, "%s -0x%x", instruction->mnemonic, v0);
  523         }
  524 
  525     } else if (AMD29K_IS_1 (AMD29K_TYPE_JMP)) {
  526         ut64 ptr = address + ((int) v0);
  527         snprintf(string, string_size, "%s 0x%" PFMT64x, instruction->mnemonic, ptr);
  528 
  529     } else if (AMD29K_IS_2 (AMD29K_TYPE_REG, AMD29K_TYPE_REG)) {
  530         const char* p0 = AMD29K_REGNAME (v0);
  531         const char* p1 = AMD29K_REGNAME (v1);
  532         snprintf(string, string_size, "%s %s%d %s%d", instruction->mnemonic, p0, AMD29K_LR (v0), p1, AMD29K_LR (v1));
  533 
  534     } else if (AMD29K_IS_2 (AMD29K_TYPE_REG, AMD29K_TYPE_IMM)) {
  535         const char* p0 = AMD29K_REGNAME (v0);
  536         if (v1 >= 0) {
  537             snprintf(string, string_size, "%s %s%d 0x%x", instruction->mnemonic, p0, AMD29K_LR (v0), v1);
  538         } else {
  539             v1 = 0 - v1;
  540             snprintf(string, string_size, "%s %s%d -0x%x", instruction->mnemonic, p0, AMD29K_LR (v0), v1);
  541         }
  542 
  543     } else if (AMD29K_IS_2 (AMD29K_TYPE_REG, AMD29K_TYPE_JMP)) {
  544         const char* p0 = AMD29K_REGNAME (v0);
  545         ut64 ptr = address + ((int) v1);
  546         snprintf(string, string_size, "%s %s%d 0x%" PFMT64x, instruction->mnemonic, p0, AMD29K_LR (v0), ptr);
  547 
  548     } else if (AMD29K_IS_3 (AMD29K_TYPE_REG, AMD29K_TYPE_REG, AMD29K_TYPE_REG)) {
  549         const char* p0 = AMD29K_REGNAME (v0);
  550         const char* p1 = AMD29K_REGNAME (v1);
  551         const char* p2 = AMD29K_REGNAME (v2);
  552         snprintf(string, string_size, "%s %s%d %s%d %s%d", instruction->mnemonic, p0, AMD29K_LR (v0), p1, AMD29K_LR (v1), p2, AMD29K_LR (v2));
  553 
  554     } else if (AMD29K_IS_3 (AMD29K_TYPE_REG, AMD29K_TYPE_REG, AMD29K_TYPE_IMM)) {
  555         const char* p0 = AMD29K_REGNAME (v0);
  556         const char* p1 = AMD29K_REGNAME (v1);
  557         if (v2 >= 0) {
  558             snprintf(string, string_size, "%s %s%d %s%d 0x%x", instruction->mnemonic, p0, AMD29K_LR (v0), p1, AMD29K_LR (v1), v2);
  559         } else {
  560             v2 = 0 - v2;
  561             snprintf(string, string_size, "%s %s%d %s%d -0x%x", instruction->mnemonic, p0, AMD29K_LR (v0), p1, AMD29K_LR (v1), v2);
  562         }
  563 
  564     } else if (AMD29K_IS_4 (AMD29K_TYPE_IMM, AMD29K_TYPE_IMM, AMD29K_TYPE_REG, AMD29K_TYPE_REG)) {
  565         const char* p2 = AMD29K_REGNAME (v2);
  566         const char* p3 = AMD29K_REGNAME (v3);
  567         snprintf(string, string_size, "%s %d %d %s%d %s%d", instruction->mnemonic, v0, v1, p2, AMD29K_LR (v2), p3, AMD29K_LR (v3));
  568 
  569     } else if (AMD29K_IS_6 (AMD29K_TYPE_REG, AMD29K_TYPE_REG, AMD29K_TYPE_IMM, AMD29K_TYPE_IMM, AMD29K_TYPE_IMM, AMD29K_TYPE_IMM)) {
  570         const char* p0 = AMD29K_REGNAME (v0);
  571         const char* p1 = AMD29K_REGNAME (v1);
  572         snprintf(string, string_size, "%s %s%d %s%d %d %d %d %d", instruction->mnemonic, p0, AMD29K_LR (v0), p1, AMD29K_LR (v1), v2, v3, v4, v5);
  573 
  574     } else {
  575         snprintf(string, string_size, "%s", instruction->mnemonic);
  576     }
  577     return;
  578 }
  579 
  580 #undef AMD29K_IS_6
  581 #undef AMD29K_IS_1
  582 #undef AMD29K_IS_2
  583 #undef AMD29K_IS_3
  584 #undef AMD29K_IS_4
  585 #undef AMD29K_IS_5