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    1 // SPDX-License-Identifier: GPL-2.0+
    2 /*
    3  * board.c
    4  *
    5  * Board functions for TI AM335X based boards
    6  *
    7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
    8  */
    9 
   10 #include <common.h>
   11 #include <dm.h>
   12 #include <env.h>
   13 #include <errno.h>
   14 #include <image.h>
   15 #include <init.h>
   16 #include <malloc.h>
   17 #include <net.h>
   18 #include <spl.h>
   19 #include <serial.h>
   20 #include <asm/arch/cpu.h>
   21 #include <asm/arch/hardware.h>
   22 #include <asm/arch/omap.h>
   23 #include <asm/arch/ddr_defs.h>
   24 #include <asm/arch/clock.h>
   25 #include <asm/arch/clk_synthesizer.h>
   26 #include <asm/arch/gpio.h>
   27 #include <asm/arch/mmc_host_def.h>
   28 #include <asm/arch/sys_proto.h>
   29 #include <asm/arch/mem.h>
   30 #include <asm/global_data.h>
   31 #include <asm/io.h>
   32 #include <asm/emif.h>
   33 #include <asm/gpio.h>
   34 #include <asm/omap_common.h>
   35 #include <asm/omap_sec_common.h>
   36 #include <asm/omap_mmc.h>
   37 #include <i2c.h>
   38 #include <miiphy.h>
   39 #include <cpsw.h>
   40 #include <linux/bitops.h>
   41 #include <linux/delay.h>
   42 #include <power/tps65217.h>
   43 #include <power/tps65910.h>
   44 #include <env_internal.h>
   45 #include <watchdog.h>
   46 #include "../common/board_detect.h"
   47 #include "../common/cape_detect.h"
   48 #include "board.h"
   49 
   50 DECLARE_GLOBAL_DATA_PTR;
   51 
   52 /* GPIO that controls power to DDR on EVM-SK */
   53 #define GPIO_TO_PIN(bank, gpio)     (32 * (bank) + (gpio))
   54 #define GPIO_DDR_VTT_EN     GPIO_TO_PIN(0, 7)
   55 #define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18)
   56 #define GPIO_PR1_MII_CTRL   GPIO_TO_PIN(3, 4)
   57 #define GPIO_MUX_MII_CTRL   GPIO_TO_PIN(3, 10)
   58 #define GPIO_FET_SWITCH_CTRL    GPIO_TO_PIN(0, 7)
   59 #define GPIO_PHY_RESET      GPIO_TO_PIN(2, 5)
   60 #define GPIO_ETH0_MODE      GPIO_TO_PIN(0, 11)
   61 #define GPIO_ETH1_MODE      GPIO_TO_PIN(1, 26)
   62 
   63 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
   64 
   65 #define GPIO0_RISINGDETECT  (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
   66 #define GPIO1_RISINGDETECT  (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
   67 
   68 #define GPIO0_IRQSTATUS1    (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
   69 #define GPIO1_IRQSTATUS1    (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
   70 
   71 #define GPIO0_IRQSTATUSRAW  (AM33XX_GPIO0_BASE + 0x024)
   72 #define GPIO1_IRQSTATUSRAW  (AM33XX_GPIO1_BASE + 0x024)
   73 
   74 /*
   75  * Read header information from EEPROM into global structure.
   76  */
   77 #ifdef CONFIG_TI_I2C_BOARD_DETECT
   78 void do_board_detect(void)
   79 {
   80     enable_i2c0_pin_mux();
   81     enable_i2c2_pin_mux();
   82 #if !CONFIG_IS_ENABLED(DM_I2C)
   83     i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
   84     i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED2, CONFIG_SYS_OMAP24_I2C_SLAVE2);
   85 #endif
   86     if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
   87                  CONFIG_EEPROM_CHIP_ADDRESS))
   88         printf("ti_i2c_eeprom_init failed\n");
   89 }
   90 #endif
   91 
   92 #ifndef CONFIG_DM_SERIAL
   93 struct serial_device *default_serial_console(void)
   94 {
   95     if (board_is_icev2())
   96         return &eserial4_device;
   97     else
   98         return &eserial1_device;
   99 }
  100 #endif
  101 
  102 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  103 static const struct ddr_data ddr2_data = {
  104     .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  105     .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  106     .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  107 };
  108 
  109 static const struct cmd_control ddr2_cmd_ctrl_data = {
  110     .cmd0csratio = MT47H128M16RT25E_RATIO,
  111 
  112     .cmd1csratio = MT47H128M16RT25E_RATIO,
  113 
  114     .cmd2csratio = MT47H128M16RT25E_RATIO,
  115 };
  116 
  117 static const struct emif_regs ddr2_emif_reg_data = {
  118     .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
  119     .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
  120     .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
  121     .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
  122     .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
  123     .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
  124 };
  125 
  126 static const struct emif_regs ddr2_evm_emif_reg_data = {
  127     .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
  128     .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
  129     .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
  130     .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
  131     .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
  132     .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
  133     .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
  134 };
  135 
  136 static const struct ddr_data ddr3_data = {
  137     .datardsratio0 = MT41J128MJT125_RD_DQS,
  138     .datawdsratio0 = MT41J128MJT125_WR_DQS,
  139     .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
  140     .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
  141 };
  142 
  143 static const struct ddr_data ddr3_beagleblack_data = {
  144     .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  145     .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  146     .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  147     .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  148 };
  149 
  150 static const struct ddr_data ddr3_evm_data = {
  151     .datardsratio0 = MT41J512M8RH125_RD_DQS,
  152     .datawdsratio0 = MT41J512M8RH125_WR_DQS,
  153     .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
  154     .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
  155 };
  156 
  157 static const struct ddr_data ddr3_icev2_data = {
  158     .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
  159     .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
  160     .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
  161     .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
  162 };
  163 
  164 static const struct cmd_control ddr3_cmd_ctrl_data = {
  165     .cmd0csratio = MT41J128MJT125_RATIO,
  166     .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
  167 
  168     .cmd1csratio = MT41J128MJT125_RATIO,
  169     .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
  170 
  171     .cmd2csratio = MT41J128MJT125_RATIO,
  172     .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
  173 };
  174 
  175 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
  176     .cmd0csratio = MT41K256M16HA125E_RATIO,
  177     .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  178 
  179     .cmd1csratio = MT41K256M16HA125E_RATIO,
  180     .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  181 
  182     .cmd2csratio = MT41K256M16HA125E_RATIO,
  183     .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  184 };
  185 
  186 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
  187     .cmd0csratio = MT41J512M8RH125_RATIO,
  188     .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
  189 
  190     .cmd1csratio = MT41J512M8RH125_RATIO,
  191     .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
  192 
  193     .cmd2csratio = MT41J512M8RH125_RATIO,
  194     .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
  195 };
  196 
  197 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
  198     .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
  199     .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
  200 
  201     .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
  202     .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
  203 
  204     .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
  205     .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
  206 };
  207 
  208 static struct emif_regs ddr3_emif_reg_data = {
  209     .sdram_config = MT41J128MJT125_EMIF_SDCFG,
  210     .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
  211     .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
  212     .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
  213     .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
  214     .zq_config = MT41J128MJT125_ZQ_CFG,
  215     .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
  216                 PHY_EN_DYN_PWRDN,
  217 };
  218 
  219 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
  220     .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  221     .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  222     .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  223     .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  224     .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  225     .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
  226     .zq_config = MT41K256M16HA125E_ZQ_CFG,
  227     .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  228 };
  229 
  230 static struct emif_regs ddr3_evm_emif_reg_data = {
  231     .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
  232     .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
  233     .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
  234     .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
  235     .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
  236     .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
  237     .zq_config = MT41J512M8RH125_ZQ_CFG,
  238     .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
  239                 PHY_EN_DYN_PWRDN,
  240 };
  241 
  242 static struct emif_regs ddr3_icev2_emif_reg_data = {
  243     .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
  244     .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
  245     .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
  246     .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
  247     .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
  248     .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
  249     .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
  250                 PHY_EN_DYN_PWRDN,
  251 };
  252 
  253 #ifdef CONFIG_SPL_OS_BOOT
  254 int spl_start_uboot(void)
  255 {
  256 #ifdef CONFIG_SPL_SERIAL_SUPPORT
  257     /* break into full u-boot on 'c' */
  258     if (serial_tstc() && serial_getc() == 'c')
  259         return 1;
  260 #endif
  261 
  262 #ifdef CONFIG_SPL_ENV_SUPPORT
  263     env_init();
  264     env_load();
  265     if (env_get_yesno("boot_os") != 1)
  266         return 1;
  267 #endif
  268 
  269     return 0;
  270 }
  271 #endif
  272 
  273 const struct dpll_params *get_dpll_ddr_params(void)
  274 {
  275     int ind = get_sys_clk_index();
  276 
  277     if (board_is_evm_sk())
  278         return &dpll_ddr3_303MHz[ind];
  279     else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
  280         return &dpll_ddr3_400MHz[ind];
  281     else if (board_is_evm_15_or_later())
  282         return &dpll_ddr3_303MHz[ind];
  283     else
  284         return &dpll_ddr2_266MHz[ind];
  285 }
  286 
  287 static u8 bone_not_connected_to_ac_power(void)
  288 {
  289     if (board_is_bone()) {
  290         uchar pmic_status_reg;
  291         if (tps65217_reg_read(TPS65217_STATUS,
  292                       &pmic_status_reg))
  293             return 1;
  294         if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
  295             puts("No AC power, switching to default OPP\n");
  296             return 1;
  297         }
  298     }
  299     return 0;
  300 }
  301 
  302 const struct dpll_params *get_dpll_mpu_params(void)
  303 {
  304     int ind = get_sys_clk_index();
  305     int freq = am335x_get_efuse_mpu_max_freq(cdev);
  306 
  307     if (bone_not_connected_to_ac_power())
  308         freq = MPUPLL_M_600;
  309 
  310     if (board_is_pb() || board_is_bone_lt())
  311         freq = MPUPLL_M_1000;
  312 
  313     switch (freq) {
  314     case MPUPLL_M_1000:
  315         return &dpll_mpu_opp[ind][5];
  316     case MPUPLL_M_800:
  317         return &dpll_mpu_opp[ind][4];
  318     case MPUPLL_M_720:
  319         return &dpll_mpu_opp[ind][3];
  320     case MPUPLL_M_600:
  321         return &dpll_mpu_opp[ind][2];
  322     case MPUPLL_M_500:
  323         return &dpll_mpu_opp100;
  324     case MPUPLL_M_300:
  325         return &dpll_mpu_opp[ind][0];
  326     }
  327 
  328     return &dpll_mpu_opp[ind][0];
  329 }
  330 
  331 static void scale_vcores_bone(int freq)
  332 {
  333     int usb_cur_lim, mpu_vdd;
  334 
  335     /*
  336      * Only perform PMIC configurations if board rev > A1
  337      * on Beaglebone White
  338      */
  339     if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
  340         return;
  341 
  342 #if !CONFIG_IS_ENABLED(DM_I2C)
  343     if (i2c_probe(TPS65217_CHIP_PM))
  344         return;
  345 #else
  346     if (power_tps65217_init(0))
  347         return;
  348 #endif
  349 
  350 
  351     /*
  352      * On Beaglebone White we need to ensure we have AC power
  353      * before increasing the frequency.
  354      */
  355     if (bone_not_connected_to_ac_power())
  356         freq = MPUPLL_M_600;
  357 
  358     /*
  359      * Override what we have detected since we know if we have
  360      * a Beaglebone Black it supports 1GHz.
  361      */
  362     if (board_is_pb() || board_is_bone_lt())
  363         freq = MPUPLL_M_1000;
  364 
  365     switch (freq) {
  366     case MPUPLL_M_1000:
  367         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  368         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
  369         break;
  370     case MPUPLL_M_800:
  371         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  372         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  373         break;
  374     case MPUPLL_M_720:
  375         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
  376         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  377         break;
  378     case MPUPLL_M_600:
  379     case MPUPLL_M_500:
  380     case MPUPLL_M_300:
  381     default:
  382         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
  383         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  384         break;
  385     }
  386 
  387     if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
  388                    TPS65217_POWER_PATH,
  389                    usb_cur_lim,
  390                    TPS65217_USB_INPUT_CUR_LIMIT_MASK))
  391         puts("tps65217_reg_write failure\n");
  392 
  393     /* Set DCDC3 (CORE) voltage to 1.10V */
  394     if (tps65217_voltage_update(TPS65217_DEFDCDC3,
  395                     TPS65217_DCDC_VOLT_SEL_1100MV)) {
  396         puts("tps65217_voltage_update failure\n");
  397         return;
  398     }
  399 
  400     /* Set DCDC2 (MPU) voltage */
  401     if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
  402         puts("tps65217_voltage_update failure\n");
  403         return;
  404     }
  405 
  406     /*
  407      * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
  408      * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
  409      */
  410     if (board_is_bone()) {
  411         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  412                        TPS65217_DEFLS1,
  413                        TPS65217_LDO_VOLTAGE_OUT_3_3,
  414                        TPS65217_LDO_MASK))
  415             puts("tps65217_reg_write failure\n");
  416     } else {
  417         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  418                        TPS65217_DEFLS1,
  419                        TPS65217_LDO_VOLTAGE_OUT_1_8,
  420                        TPS65217_LDO_MASK))
  421             puts("tps65217_reg_write failure\n");
  422     }
  423 
  424     if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  425                    TPS65217_DEFLS2,
  426                    TPS65217_LDO_VOLTAGE_OUT_3_3,
  427                    TPS65217_LDO_MASK))
  428         puts("tps65217_reg_write failure\n");
  429 }
  430 
  431 void scale_vcores_generic(int freq)
  432 {
  433     int sil_rev, mpu_vdd;
  434 
  435     /*
  436      * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
  437      * MPU frequencies we support we use a CORE voltage of
  438      * 1.10V.  For MPU voltage we need to switch based on
  439      * the frequency we are running at.
  440      */
  441 #if !CONFIG_IS_ENABLED(DM_I2C)
  442     if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
  443         return;
  444 #else
  445     if (power_tps65910_init(0))
  446         return;
  447 #endif
  448     /*
  449      * Depending on MPU clock and PG we will need a different
  450      * VDD to drive at that speed.
  451      */
  452     sil_rev = readl(&cdev->deviceid) >> 28;
  453     mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
  454 
  455     /* Tell the TPS65910 to use i2c */
  456     tps65910_set_i2c_control();
  457 
  458     /* First update MPU voltage. */
  459     if (tps65910_voltage_update(MPU, mpu_vdd))
  460         return;
  461 
  462     /* Second, update the CORE voltage. */
  463     if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
  464         return;
  465 
  466 }
  467 
  468 void gpi2c_init(void)
  469 {
  470     /* When needed to be invoked prior to BSS initialization */
  471     static bool first_time = true;
  472 
  473     if (first_time) {
  474         enable_i2c0_pin_mux();
  475 #if !CONFIG_IS_ENABLED(DM_I2C)
  476         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
  477              CONFIG_SYS_OMAP24_I2C_SLAVE);
  478 #endif
  479         first_time = false;
  480     }
  481 }
  482 
  483 void scale_vcores(void)
  484 {
  485     int freq;
  486 
  487     gpi2c_init();
  488     freq = am335x_get_efuse_mpu_max_freq(cdev);
  489 
  490     if (board_is_beaglebonex())
  491         scale_vcores_bone(freq);
  492     else
  493         scale_vcores_generic(freq);
  494 }
  495 
  496 void set_uart_mux_conf(void)
  497 {
  498 #if CONFIG_CONS_INDEX == 1
  499     enable_uart0_pin_mux();
  500 #elif CONFIG_CONS_INDEX == 2
  501     enable_uart1_pin_mux();
  502 #elif CONFIG_CONS_INDEX == 3
  503     enable_uart2_pin_mux();
  504 #elif CONFIG_CONS_INDEX == 4
  505     enable_uart3_pin_mux();
  506 #elif CONFIG_CONS_INDEX == 5
  507     enable_uart4_pin_mux();
  508 #elif CONFIG_CONS_INDEX == 6
  509     enable_uart5_pin_mux();
  510 #endif
  511 }
  512 
  513 void set_mux_conf_regs(void)
  514 {
  515     enable_board_pin_mux();
  516 }
  517 
  518 const struct ctrl_ioregs ioregs_evmsk = {
  519     .cm0ioctl       = MT41J128MJT125_IOCTRL_VALUE,
  520     .cm1ioctl       = MT41J128MJT125_IOCTRL_VALUE,
  521     .cm2ioctl       = MT41J128MJT125_IOCTRL_VALUE,
  522     .dt0ioctl       = MT41J128MJT125_IOCTRL_VALUE,
  523     .dt1ioctl       = MT41J128MJT125_IOCTRL_VALUE,
  524 };
  525 
  526 const struct ctrl_ioregs ioregs_bonelt = {
  527     .cm0ioctl       = MT41K256M16HA125E_IOCTRL_VALUE,
  528     .cm1ioctl       = MT41K256M16HA125E_IOCTRL_VALUE,
  529     .cm2ioctl       = MT41K256M16HA125E_IOCTRL_VALUE,
  530     .dt0ioctl       = MT41K256M16HA125E_IOCTRL_VALUE,
  531     .dt1ioctl       = MT41K256M16HA125E_IOCTRL_VALUE,
  532 };
  533 
  534 const struct ctrl_ioregs ioregs_evm15 = {
  535     .cm0ioctl       = MT41J512M8RH125_IOCTRL_VALUE,
  536     .cm1ioctl       = MT41J512M8RH125_IOCTRL_VALUE,
  537     .cm2ioctl       = MT41J512M8RH125_IOCTRL_VALUE,
  538     .dt0ioctl       = MT41J512M8RH125_IOCTRL_VALUE,
  539     .dt1ioctl       = MT41J512M8RH125_IOCTRL_VALUE,
  540 };
  541 
  542 const struct ctrl_ioregs ioregs = {
  543     .cm0ioctl       = MT47H128M16RT25E_IOCTRL_VALUE,
  544     .cm1ioctl       = MT47H128M16RT25E_IOCTRL_VALUE,
  545     .cm2ioctl       = MT47H128M16RT25E_IOCTRL_VALUE,
  546     .dt0ioctl       = MT47H128M16RT25E_IOCTRL_VALUE,
  547     .dt1ioctl       = MT47H128M16RT25E_IOCTRL_VALUE,
  548 };
  549 
  550 void sdram_init(void)
  551 {
  552     if (board_is_evm_sk()) {
  553         /*
  554          * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
  555          * This is safe enough to do on older revs.
  556          */
  557         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
  558         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
  559     }
  560 
  561     if (board_is_icev2()) {
  562         gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
  563         gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
  564     }
  565 
  566     if (board_is_evm_sk())
  567         config_ddr(303, &ioregs_evmsk, &ddr3_data,
  568                &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
  569     else if (board_is_pb() || board_is_bone_lt())
  570         config_ddr(400, &ioregs_bonelt,
  571                &ddr3_beagleblack_data,
  572                &ddr3_beagleblack_cmd_ctrl_data,
  573                &ddr3_beagleblack_emif_reg_data, 0);
  574     else if (board_is_evm_15_or_later())
  575         config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
  576                &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
  577     else if (board_is_icev2())
  578         config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
  579                &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
  580                0);
  581     else if (board_is_gp_evm())
  582         config_ddr(266, &ioregs, &ddr2_data,
  583                &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
  584     else
  585         config_ddr(266, &ioregs, &ddr2_data,
  586                &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
  587 }
  588 #endif
  589 
  590 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
  591     (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
  592 static void request_and_set_gpio(int gpio, char *name, int val)
  593 {
  594     int ret;
  595 
  596     ret = gpio_request(gpio, name);
  597     if (ret < 0) {
  598         printf("%s: Unable to request %s\n", __func__, name);
  599         return;
  600     }
  601 
  602     ret = gpio_direction_output(gpio, 0);
  603     if (ret < 0) {
  604         printf("%s: Unable to set %s  as output\n", __func__, name);
  605         goto err_free_gpio;
  606     }
  607 
  608     gpio_set_value(gpio, val);
  609 
  610     return;
  611 
  612 err_free_gpio:
  613     gpio_free(gpio);
  614 }
  615 
  616 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
  617 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
  618 
  619 /**
  620  * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
  621  * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
  622  * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
  623  * give 50MHz output for Eth0 and 1.
  624  */
  625 static struct clk_synth cdce913_data = {
  626     .id = 0x81,
  627     .capacitor = 0x90,
  628     .mux = 0x6d,
  629     .pdiv2 = 0x2,
  630     .pdiv3 = 0x2,
  631 };
  632 #endif
  633 
  634 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
  635     defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
  636 
  637 #define MAX_CPSW_SLAVES 2
  638 
  639 /* At the moment, we do not want to stop booting for any failures here */
  640 int ft_board_setup(void *fdt, struct bd_info *bd)
  641 {
  642     const char *slave_path, *enet_name;
  643     int enetnode, slavenode, phynode;
  644     struct udevice *ethdev;
  645     char alias[16];
  646     u32 phy_id[2];
  647     int phy_addr;
  648     int i, ret;
  649 
  650     /* phy address fixup needed only on beagle bone family */
  651     if (!board_is_beaglebonex())
  652         goto done;
  653 
  654     for (i = 0; i < MAX_CPSW_SLAVES; i++) {
  655         sprintf(alias, "ethernet%d", i);
  656 
  657         slave_path = fdt_get_alias(fdt, alias);
  658         if (!slave_path)
  659             continue;
  660 
  661         slavenode = fdt_path_offset(fdt, slave_path);
  662         if (slavenode < 0)
  663             continue;
  664 
  665         enetnode = fdt_parent_offset(fdt, slavenode);
  666         enet_name = fdt_get_name(fdt, enetnode, NULL);
  667 
  668         ethdev = eth_get_dev_by_name(enet_name);
  669         if (!ethdev)
  670             continue;
  671 
  672         phy_addr = cpsw_get_slave_phy_addr(ethdev, i);
  673 
  674         /* check for phy_id as well as phy-handle properties */
  675         ret = fdtdec_get_int_array_count(fdt, slavenode, "phy_id",
  676                          phy_id, 2);
  677         if (ret == 2) {
  678             if (phy_id[1] != phy_addr) {
  679                 printf("fixing up phy_id for %s, old: %d, new: %d\n",
  680                        alias, phy_id[1], phy_addr);
  681 
  682                 phy_id[0] = cpu_to_fdt32(phy_id[0]);
  683                 phy_id[1] = cpu_to_fdt32(phy_addr);
  684                 do_fixup_by_path(fdt, slave_path, "phy_id",
  685                          phy_id, sizeof(phy_id), 0);
  686             }
  687         } else {
  688             phynode = fdtdec_lookup_phandle(fdt, slavenode,
  689                             "phy-handle");
  690             if (phynode < 0)
  691                 continue;
  692 
  693             ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT);
  694             if (ret < 0)
  695                 continue;
  696 
  697             if (ret != phy_addr) {
  698                 printf("fixing up phy-handle for %s, old: %d, new: %d\n",
  699                        alias, ret, phy_addr);
  700 
  701                 fdt_setprop_u32(fdt, phynode, "reg",
  702                         cpu_to_fdt32(phy_addr));
  703             }
  704         }
  705     }
  706 
  707 done:
  708     return 0;
  709 }
  710 #endif
  711 
  712 /*
  713  * Basic board specific setup.  Pinmux has been handled already.
  714  */
  715 int board_init(void)
  716 {
  717 #if defined(CONFIG_HW_WATCHDOG)
  718     hw_watchdog_init();
  719 #endif
  720 
  721     gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  722 #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
  723     gpmc_init();
  724 #endif
  725 
  726 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
  727     (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
  728     if (board_is_icev2()) {
  729         int rv;
  730         u32 reg;
  731 
  732         REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
  733         /* Make J19 status available on GPIO1_26 */
  734         REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
  735 
  736         REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
  737         /*
  738          * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
  739          * jumpers near the port. Read the jumper value and set
  740          * the pinmux, external mux and PHY clock accordingly.
  741          * As jumper line is overridden by PHY RX_DV pin immediately
  742          * after bootstrap (power-up/reset), we need to sample
  743          * it during PHY reset using GPIO rising edge detection.
  744          */
  745         REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
  746         /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
  747         reg = readl(GPIO0_RISINGDETECT) | BIT(11);
  748         writel(reg, GPIO0_RISINGDETECT);
  749         reg = readl(GPIO1_RISINGDETECT) | BIT(26);
  750         writel(reg, GPIO1_RISINGDETECT);
  751         /* Reset PHYs to capture the Jumper setting */
  752         gpio_set_value(GPIO_PHY_RESET, 0);
  753         udelay(2);  /* PHY datasheet states 1uS min. */
  754         gpio_set_value(GPIO_PHY_RESET, 1);
  755 
  756         reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
  757         if (reg) {
  758             writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
  759             /* RMII mode */
  760             printf("ETH0, CPSW\n");
  761         } else {
  762             /* MII mode */
  763             printf("ETH0, PRU\n");
  764             cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
  765         }
  766 
  767         reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
  768         if (reg) {
  769             writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
  770             /* RMII mode */
  771             printf("ETH1, CPSW\n");
  772             gpio_set_value(GPIO_MUX_MII_CTRL, 1);
  773         } else {
  774             /* MII mode */
  775             printf("ETH1, PRU\n");
  776             cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
  777         }
  778 
  779         /* disable rising edge IRQs */
  780         reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
  781         writel(reg, GPIO0_RISINGDETECT);
  782         reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
  783         writel(reg, GPIO1_RISINGDETECT);
  784 
  785         rv = setup_clock_synthesizer(&cdce913_data);
  786         if (rv) {
  787             printf("Clock synthesizer setup failed %d\n", rv);
  788             return rv;
  789         }
  790 
  791         /* reset PHYs */
  792         gpio_set_value(GPIO_PHY_RESET, 0);
  793         udelay(2);  /* PHY datasheet states 1uS min. */
  794         gpio_set_value(GPIO_PHY_RESET, 1);
  795     }
  796 #endif
  797 
  798     return 0;
  799 }
  800 
  801 #ifdef CONFIG_BOARD_LATE_INIT
  802 int board_late_init(void)
  803 {
  804     struct udevice *dev;
  805 #if !defined(CONFIG_SPL_BUILD)
  806     uint8_t mac_addr[6];
  807     uint32_t mac_hi, mac_lo;
  808 #endif
  809 
  810 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  811     char *name = NULL;
  812 
  813     if (board_is_bone_lt()) {
  814         /* BeagleBoard.org BeagleBone Black Wireless: */
  815         if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
  816             name = "BBBW";
  817         }
  818         /* SeeedStudio BeagleBone Green Wireless */
  819         if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
  820             name = "BBGW";
  821         }
  822         /* BeagleBoard.org BeagleBone Blue */
  823         if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
  824             name = "BBBL";
  825         }
  826     }
  827 
  828     if (board_is_bbg1())
  829         name = "BBG1";
  830     if (board_is_bben())
  831         name = "BBEN";
  832     set_board_info_env(name);
  833 
  834     /*
  835      * Default FIT boot on HS devices. Non FIT images are not allowed
  836      * on HS devices.
  837      */
  838     if (get_device_type() == HS_DEVICE)
  839         env_set("boot_fit", "1");
  840 #endif
  841 
  842 #if !defined(CONFIG_SPL_BUILD)
  843     /* try reading mac address from efuse */
  844     mac_lo = readl(&cdev->macid0l);
  845     mac_hi = readl(&cdev->macid0h);
  846     mac_addr[0] = mac_hi & 0xFF;
  847     mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  848     mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  849     mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  850     mac_addr[4] = mac_lo & 0xFF;
  851     mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  852 
  853     if (!env_get("ethaddr")) {
  854         printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  855 
  856         if (is_valid_ethaddr(mac_addr))
  857             eth_env_set_enetaddr("ethaddr", mac_addr);
  858     }
  859 
  860     mac_lo = readl(&cdev->macid1l);
  861     mac_hi = readl(&cdev->macid1h);
  862     mac_addr[0] = mac_hi & 0xFF;
  863     mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  864     mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  865     mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  866     mac_addr[4] = mac_lo & 0xFF;
  867     mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  868 
  869     if (!env_get("eth1addr")) {
  870         if (is_valid_ethaddr(mac_addr))
  871             eth_env_set_enetaddr("eth1addr", mac_addr);
  872     }
  873 #endif
  874 
  875     if (!env_get("serial#")) {
  876         char *board_serial = env_get("board_serial");
  877         char *ethaddr = env_get("ethaddr");
  878 
  879         if (!board_serial || !strncmp(board_serial, "unknown", 7))
  880             env_set("serial#", ethaddr);
  881         else
  882             env_set("serial#", board_serial);
  883     }
  884 
  885     /* Just probe the potentially supported cdce913 device */
  886     uclass_get_device_by_name(UCLASS_CLK, "cdce913@65", &dev);
  887 
  888     return 0;
  889 }
  890 #endif
  891 
  892 /* CPSW plat */
  893 #if !CONFIG_IS_ENABLED(OF_CONTROL)
  894 struct cpsw_slave_data slave_data[] = {
  895     {
  896         .slave_reg_ofs  = CPSW_SLAVE0_OFFSET,
  897         .sliver_reg_ofs = CPSW_SLIVER0_OFFSET,
  898         .phy_addr       = 0,
  899     },
  900     {
  901         .slave_reg_ofs  = CPSW_SLAVE1_OFFSET,
  902         .sliver_reg_ofs = CPSW_SLIVER1_OFFSET,
  903         .phy_addr       = 1,
  904     },
  905 };
  906 
  907 struct cpsw_platform_data am335_eth_data = {
  908     .cpsw_base      = CPSW_BASE,
  909     .version        = CPSW_CTRL_VERSION_2,
  910     .bd_ram_ofs     = CPSW_BD_OFFSET,
  911     .ale_reg_ofs        = CPSW_ALE_OFFSET,
  912     .cpdma_reg_ofs      = CPSW_CPDMA_OFFSET,
  913     .mdio_div       = CPSW_MDIO_DIV,
  914     .host_port_reg_ofs  = CPSW_HOST_PORT_OFFSET,
  915     .channels       = 8,
  916     .slaves         = 2,
  917     .slave_data     = slave_data,
  918     .ale_entries        = 1024,
  919     .mac_control        = 0x20,
  920     .active_slave       = 0,
  921     .mdio_base      = 0x4a101000,
  922     .gmii_sel       = 0x44e10650,
  923     .phy_sel_compat     = "ti,am3352-cpsw-phy-sel",
  924     .syscon_addr        = 0x44e10630,
  925     .macid_sel_compat   = "cpsw,am33xx",
  926 };
  927 
  928 struct eth_pdata cpsw_pdata = {
  929     .iobase = 0x4a100000,
  930     .phy_interface = 0,
  931     .priv_pdata = &am335_eth_data,
  932 };
  933 
  934 U_BOOT_DRVINFO(am335x_eth) = {
  935     .name = "eth_cpsw",
  936     .plat = &cpsw_pdata,
  937 };
  938 #endif
  939 
  940 #ifdef CONFIG_SPL_LOAD_FIT
  941 int board_fit_config_name_match(const char *name)
  942 {
  943     if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
  944         return 0;
  945     else if (board_is_bone() && !strcmp(name, "am335x-bone"))
  946         return 0;
  947     else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
  948         return 0;
  949     else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
  950         return 0;
  951     else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
  952         return 0;
  953     else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
  954         return 0;
  955     else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
  956         return 0;
  957     else
  958         return -1;
  959 }
  960 #endif
  961 
  962 #ifdef CONFIG_TI_SECURE_DEVICE
  963 void board_fit_image_post_process(void **p_image, size_t *p_size)
  964 {
  965     secure_boot_verify_image(p_image, p_size);
  966 }
  967 #endif
  968 
  969 #if !CONFIG_IS_ENABLED(OF_CONTROL)
  970 static const struct omap_hsmmc_plat am335x_mmc0_plat = {
  971     .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
  972     .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
  973     .cfg.f_min = 400000,
  974     .cfg.f_max = 52000000,
  975     .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
  976     .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  977 };
  978 
  979 U_BOOT_DRVINFO(am335x_mmc0) = {
  980     .name = "omap_hsmmc",
  981     .plat = &am335x_mmc0_plat,
  982 };
  983 
  984 static const struct omap_hsmmc_plat am335x_mmc1_plat = {
  985     .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
  986     .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
  987     .cfg.f_min = 400000,
  988     .cfg.f_max = 52000000,
  989     .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
  990     .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  991 };
  992 
  993 U_BOOT_DRVINFO(am335x_mmc1) = {
  994     .name = "omap_hsmmc",
  995     .plat = &am335x_mmc1_plat,
  996 };
  997 #endif