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Member "openpa-1.0.4/src/primitives/opa_gcc_intel_32_64_p3barrier.h" (5 Dec 2012, 1472 Bytes) of package /linux/misc/openpa-1.0.4.tar.gz:


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    1 /* -*- Mode: C; c-basic-offset:4 ; indent-tabs-mode:nil ; -*- */
    2 /*
    3  *  (C) 2008 by Argonne National Laboratory.
    4  *      See COPYRIGHT in top-level directory.
    5  */
    6 
    7 #ifndef OPA_GCC_INTEL_32_64_P3BARRIER_H_INCLUDED
    8 #define OPA_GCC_INTEL_32_64_P3BARRIER_H_INCLUDED
    9 
   10 #define OPA_compiler_barrier() __asm__ __volatile__ ( "" ::: "memory" )
   11 
   12 /* For all regular memory (write-back cacheable, not driver/graphics
   13  * memory), there is only one general ordering relaxation permitted by
   14  * x86/x86_64 processors: earlier stores may be retired after later
   15  * stores.  The "clflush" and "movnt*" instructions also don't follow
   16  * general ordering constraints, although any code using these
   17  * instructions should be responsible for ensuring proper ordering
   18  * itself.  So our read and write barriers may be implemented as simple
   19  * compiler barriers. */
   20 #define OPA_write_barrier() OPA_compiler_barrier()
   21 #define OPA_read_barrier()  OPA_compiler_barrier()
   22 
   23 /* Some Pentium III and earlier processors have store barriers
   24    (sfence), but no full barrier or load barriers.  Some other very
   25    recent x86-like processors don't seem to have sfence either.  A
   26    lock-prefixed atomic instruction (operating on any memory) behaves as
   27    a full memory barrier, so we use that here. */
   28 static inline void OPA_read_write_barrier(void)
   29 {
   30     int a = 0;
   31     __asm__ __volatile__ ("lock orl $0, %0" : "+m" (a) : /*no outputs*/ : "memory");
   32 }
   33 
   34 #endif /* OPA_GCC_INTEL_32_64_P3BARRIER_H_INCLUDED */