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Member "openpa-1.0.4/src/primitives/opa_gcc_intel_32_64_ops.h" (5 Dec 2012, 4809 Bytes) of package /linux/misc/openpa-1.0.4.tar.gz:


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    1 /* -*- Mode: C; c-basic-offset:4 ; indent-tabs-mode:nil ; -*- */
    2 /*
    3  *  (C) 2008 by Argonne National Laboratory.
    4  *      See COPYRIGHT in top-level directory.
    5  */
    6 
    7 #ifndef OPA_GCC_INTEL_32_64_OPS_H_INCLUDED
    8 #define OPA_GCC_INTEL_32_64_OPS_H_INCLUDED
    9 
   10 #ifndef OPA_SIZEOF_INT
   11 #error OPA_SIZEOF_INT is not defined
   12 #endif
   13 
   14 /* Set OPA_SS (Size Suffix) which is to be appended to asm ops for
   15    specifying 4 or 8 byte operands */
   16 #if OPA_SIZEOF_INT == 4
   17 #define OPA_SS "l"
   18 #elif OPA_SIZEOF_INT == 8
   19 #define OPA_SS "q"
   20 #else
   21 #error OPA_SIZEOF_INT is not 4 or 8
   22 #endif
   23 
   24 /* XXX DJG FIXME do we need to align these? */
   25 typedef struct { volatile int v;    } OPA_int_t;
   26 typedef struct { void * volatile v; } OPA_ptr_t;
   27 
   28 #define OPA_INT_T_INITIALIZER(val_) { (val_) }
   29 #define OPA_PTR_T_INITIALIZER(val_) { (val_) }
   30 
   31 /* Aligned loads and stores are atomic on x86(-64). */
   32 static _opa_inline int OPA_load_int(_opa_const OPA_int_t *ptr)
   33 {
   34     return ptr->v;
   35 }
   36 
   37 /* Aligned loads and stores are atomic on x86(-64). */
   38 static _opa_inline void OPA_store_int(OPA_int_t *ptr, int val)
   39 {
   40     ptr->v = val;
   41 }
   42 
   43 /* Aligned loads and stores are atomic on x86(-64). */
   44 static _opa_inline void *OPA_load_ptr(_opa_const OPA_ptr_t *ptr)
   45 {
   46     return ptr->v;
   47 }
   48 
   49 /* Aligned loads and stores are atomic on x86(-64). */
   50 static _opa_inline void OPA_store_ptr(OPA_ptr_t *ptr, void *val)
   51 {
   52     ptr->v = val;
   53 }
   54 
   55 /* NOTE-X86-1 x86 and x86_64 processors execute instructions such that their
   56  * effects are visible in issue order, with one exception:  earlier stores may
   57  * pass later loads.  Also, non-temporal stores (with the "movnt*" instructions)
   58  * do not follow these ordering constraints.  So all normal load/store
   59  * instructions on x86(_64) already have acquire/release semantics.  We just
   60  * have to make sure that the compiler does not reorder the instructions. */
   61 
   62 static _opa_inline int OPA_load_acquire_int(_opa_const OPA_int_t *ptr)
   63 {
   64     int tmp;
   65     tmp = ptr->v;
   66     OPA_compiler_barrier(); /* NOTE-X86-1 */
   67     return tmp;
   68 }
   69 
   70 static _opa_inline void OPA_store_release_int(OPA_int_t *ptr, int val)
   71 {
   72     OPA_compiler_barrier(); /* NOTE-X86-1 */
   73     ptr->v = val;
   74 }
   75 
   76 static _opa_inline void *OPA_load_acquire_ptr(_opa_const OPA_ptr_t *ptr)
   77 {
   78     void *tmp;
   79     tmp = ptr->v;
   80     OPA_compiler_barrier(); /* NOTE-X86-1 */
   81     return tmp;
   82 }
   83 
   84 static _opa_inline void OPA_store_release_ptr(OPA_ptr_t *ptr, void *val)
   85 {
   86     OPA_compiler_barrier(); /* NOTE-X86-1 */
   87     ptr->v = val;
   88 }
   89 
   90 
   91 static _opa_inline void OPA_add_int(OPA_int_t *ptr, int val)
   92 {
   93     __asm__ __volatile__ ("lock ; add"OPA_SS" %1,%0"
   94                           :"=m" (ptr->v)
   95                           :"ir" (val), "m" (ptr->v));
   96     return;
   97 }
   98 
   99 static _opa_inline void OPA_incr_int(OPA_int_t *ptr)
  100 {
  101     __asm__ __volatile__ ("lock ; inc"OPA_SS" %0"
  102                           :"=m" (ptr->v)
  103                           :"m" (ptr->v));
  104     return;
  105 }
  106 
  107 static _opa_inline void OPA_decr_int(OPA_int_t *ptr)
  108 {
  109     __asm__ __volatile__ ("lock ; dec"OPA_SS" %0"
  110                           :"=m" (ptr->v)
  111                           :"m" (ptr->v));
  112     return;
  113 }
  114 
  115 
  116 static _opa_inline int OPA_decr_and_test_int(OPA_int_t *ptr)
  117 {
  118     char result;
  119     __asm__ __volatile__ ("lock ; dec"OPA_SS" %0; setz %1"
  120                           :"=m" (ptr->v), "=q" (result)
  121                           :"m" (ptr->v));
  122     return result;
  123 }
  124 
  125 static _opa_inline int OPA_fetch_and_add_int(OPA_int_t *ptr, int val)
  126 {
  127     __asm__ __volatile__ ("lock ; xadd %0,%1"
  128                           : "=r" (val), "=m" (ptr->v)
  129                           :  "0" (val),  "m" (ptr->v));
  130     return val;
  131 }
  132 
  133 #define OPA_fetch_and_incr_int_by_faa OPA_fetch_and_incr_int
  134 #define OPA_fetch_and_decr_int_by_faa OPA_fetch_and_decr_int
  135 
  136 
  137 static _opa_inline void *OPA_cas_ptr(OPA_ptr_t *ptr, void *oldv, void *newv)
  138 {
  139     void *prev;
  140     __asm__ __volatile__ ("lock ; cmpxchg %3,%4"
  141                           : "=a" (prev), "=m" (ptr->v)
  142                           : "0" (oldv), "q" (newv), "m" (ptr->v));
  143     return prev;
  144 }
  145 
  146 static _opa_inline int OPA_cas_int(OPA_int_t *ptr, int oldv, int newv)
  147 {
  148     int prev;
  149     __asm__ __volatile__ ("lock ; cmpxchg %3,%4"
  150                           : "=a" (prev), "=m" (ptr->v)
  151                           : "0" (oldv), "q" (newv), "m" (ptr->v));
  152     return prev;
  153 }
  154 
  155 static _opa_inline void *OPA_swap_ptr(OPA_ptr_t *ptr, void *val)
  156 {
  157     __asm__ __volatile__ ("xchg %0,%1"
  158                           :"=r" (val), "=m" (ptr->v)
  159                           : "0" (val),  "m" (ptr->v));
  160     return val;
  161 }
  162 
  163 static _opa_inline int OPA_swap_int(OPA_int_t *ptr, int val)
  164 {
  165     __asm__ __volatile__ ("xchg %0,%1"
  166                           :"=r" (val), "=m" (ptr->v)
  167                           : "0" (val),  "m" (ptr->v));
  168     return val;
  169 }
  170 
  171 #undef OPA_SS
  172 
  173 #endif /* OPA_GCC_INTEL_32_64_OPS_H_INCLUDED */