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Member "bind-9.11.23/lib/isc/powerpc/include/isc/atomic.h" (7 Sep 2020, 3336 Bytes) of package /linux/misc/dns/bind9/9.11.23/bind-9.11.23.tar.gz:


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    1 /*
    2  * Copyright (C) Internet Systems Consortium, Inc. ("ISC")
    3  *
    4  * This Source Code Form is subject to the terms of the Mozilla Public
    5  * License, v. 2.0. If a copy of the MPL was not distributed with this
    6  * file, You can obtain one at http://mozilla.org/MPL/2.0/.
    7  *
    8  * See the COPYRIGHT file distributed with this work for additional
    9  * information regarding copyright ownership.
   10  */
   11 
   12 
   13 #ifndef ISC_ATOMIC_H
   14 #define ISC_ATOMIC_H 1
   15 
   16 #include <inttypes.h>
   17 
   18 #include <isc/platform.h>
   19 #include <isc/types.h>
   20 
   21 /*!\file
   22  * static inline int32_t
   23  * isc_atomic_xadd(int32_t *p, int32_t val);
   24  *
   25  * This routine atomically increments the value stored in 'p' by 'val', and
   26  * returns the previous value.
   27  *
   28  * static inline void
   29  * isc_atomic_store(void *p, int32_t val);
   30  *
   31  * This routine atomically stores the value 'val' in 'p'.
   32  *
   33  * static inline int32_t
   34  * isc_atomic_cmpxchg(int32_t *p, int32_t cmpval, int32_t val);
   35  *
   36  * This routine atomically replaces the value in 'p' with 'val', if the
   37  * original value is equal to 'cmpval'.  The original value is returned in any
   38  * case.
   39  */
   40 
   41 #if defined(_AIX)
   42 
   43 #include <sys/atomic_op.h>
   44 
   45 #define isc_atomic_store(p, v) _clear_lock(p, v)
   46 
   47 #ifdef __GNUC__
   48 static inline int32_t
   49 #else
   50 static int32_t
   51 #endif
   52 isc_atomic_xadd(int32_t *p, int32_t val) {
   53     int ret;
   54 
   55 #ifdef __GNUC__
   56     asm("ics");
   57 #else
   58      __isync();
   59 #endif
   60 
   61     ret = fetch_and_add((atomic_p)p, (int)val);
   62 
   63 #ifdef __GNUC__
   64     asm("ics");
   65 #else
   66      __isync();
   67 #endif
   68 
   69      return (ret);
   70 }
   71 
   72 #ifdef __GNUC__
   73 static inline int
   74 #else
   75 static int
   76 #endif
   77 isc_atomic_cmpxchg(atomic_p p, int old, int replacement) {
   78     int orig = old;
   79 
   80 #ifdef __GNUC__
   81     asm("ics");
   82 #else
   83      __isync();
   84 #endif
   85     if (compare_and_swap(p, &orig, replacement))
   86         orig = old;
   87 
   88 #ifdef __GNUC__
   89     asm("ics");
   90 #else
   91      __isync();
   92 #endif
   93 
   94     return (orig);
   95 }
   96 
   97 #elif defined(ISC_PLATFORM_USEGCCASM) || defined(ISC_PLATFORM_USEMACASM)
   98 static inline int32_t
   99 isc_atomic_xadd(int32_t *p, int32_t val) {
  100     int32_t orig;
  101 
  102     __asm__ volatile (
  103 #ifdef ISC_PLATFORM_USEMACASM
  104         "1:"
  105         "lwarx r6, 0, %1\n"
  106         "mr %0, r6\n"
  107         "add r6, r6, %2\n"
  108         "stwcx. r6, 0, %1\n"
  109         "bne- 1b\n"
  110         "sync"
  111 #else
  112         "1:"
  113         "lwarx 6, 0, %1\n"
  114         "mr %0, 6\n"
  115         "add 6, 6, %2\n"
  116         "stwcx. 6, 0, %1\n"
  117         "bne- 1b\n"
  118         "sync"
  119 #endif
  120         : "=&r"(orig)
  121         : "r"(p), "r"(val)
  122         : "r6", "memory"
  123         );
  124 
  125     return (orig);
  126 }
  127 
  128 static inline void
  129 isc_atomic_store(void *p, int32_t val) {
  130     __asm__ volatile (
  131 #ifdef ISC_PLATFORM_USEMACASM
  132         "1:"
  133         "lwarx r6, 0, %0\n"
  134         "lwz r6, %1\n"
  135         "stwcx. r6, 0, %0\n"
  136         "bne- 1b\n"
  137         "sync"
  138 #else
  139         "1:"
  140         "lwarx 6, 0, %0\n"
  141         "lwz 6, %1\n"
  142         "stwcx. 6, 0, %0\n"
  143         "bne- 1b\n"
  144         "sync"
  145 #endif
  146         :
  147         : "r"(p), "m"(val)
  148         : "r6", "memory"
  149         );
  150 }
  151 
  152 static inline int32_t
  153 isc_atomic_cmpxchg(int32_t *p, int32_t cmpval, int32_t val) {
  154     int32_t orig;
  155 
  156     __asm__ volatile (
  157 #ifdef ISC_PLATFORM_USEMACASM
  158         "1:"
  159         "lwarx r6, 0, %1\n"
  160         "mr %0,r6\n"
  161         "cmpw r6, %2\n"
  162         "bne 2f\n"
  163         "mr r6, %3\n"
  164         "stwcx. r6, 0, %1\n"
  165         "bne- 1b\n"
  166         "2:\n"
  167         "sync"
  168 #else
  169         "1:"
  170         "lwarx 6, 0, %1\n"
  171         "mr %0,6\n"
  172         "cmpw 6, %2\n"
  173         "bne 2f\n"
  174         "mr 6, %3\n"
  175         "stwcx. 6, 0, %1\n"
  176         "bne- 1b\n"
  177         "2:\n"
  178         "sync"
  179 #endif
  180         : "=&r" (orig)
  181         : "r"(p), "r"(cmpval), "r"(val)
  182         : "r6", "memory"
  183         );
  184 
  185     return (orig);
  186 }
  187 
  188 #else
  189 
  190 #error "unsupported compiler.  disable atomic ops by --disable-atomic"
  191 
  192 #endif
  193 #endif /* ISC_ATOMIC_H */