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Member "mesa-20.1.8/src/gallium/drivers/radeonsi/si_shaderlib_tgsi.c" (16 Sep 2020, 37821 Bytes) of package /linux/misc/mesa-20.1.8.tar.xz:


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    1 /*
    2  * Copyright 2018 Advanced Micro Devices, Inc.
    3  * All Rights Reserved.
    4  *
    5  * Permission is hereby granted, free of charge, to any person obtaining a
    6  * copy of this software and associated documentation files (the "Software"),
    7  * to deal in the Software without restriction, including without limitation
    8  * on the rights to use, copy, modify, merge, publish, distribute, sub
    9  * license, and/or sell copies of the Software, and to permit persons to whom
   10  * the Software is furnished to do so, subject to the following conditions:
   11  *
   12  * The above copyright notice and this permission notice (including the next
   13  * paragraph) shall be included in all copies or substantial portions of the
   14  * Software.
   15  *
   16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
   19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
   20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
   21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
   22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
   23  */
   24 
   25 #include "si_pipe.h"
   26 #include "tgsi/tgsi_text.h"
   27 #include "tgsi/tgsi_ureg.h"
   28 
   29 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type, unsigned num_layers)
   30 {
   31    unsigned vs_blit_property;
   32    void **vs;
   33 
   34    switch (type) {
   35    case UTIL_BLITTER_ATTRIB_NONE:
   36       vs = num_layers > 1 ? &sctx->vs_blit_pos_layered : &sctx->vs_blit_pos;
   37       vs_blit_property = SI_VS_BLIT_SGPRS_POS;
   38       break;
   39    case UTIL_BLITTER_ATTRIB_COLOR:
   40       vs = num_layers > 1 ? &sctx->vs_blit_color_layered : &sctx->vs_blit_color;
   41       vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR;
   42       break;
   43    case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
   44    case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
   45       assert(num_layers == 1);
   46       vs = &sctx->vs_blit_texcoord;
   47       vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD;
   48       break;
   49    default:
   50       assert(0);
   51       return NULL;
   52    }
   53    if (*vs)
   54       return *vs;
   55 
   56    struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX);
   57    if (!ureg)
   58       return NULL;
   59 
   60    /* Tell the shader to load VS inputs from SGPRs: */
   61    ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS_AMD, vs_blit_property);
   62    ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true);
   63 
   64    /* This is just a pass-through shader with 1-3 MOV instructions. */
   65    ureg_MOV(ureg, ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0), ureg_DECL_vs_input(ureg, 0));
   66 
   67    if (type != UTIL_BLITTER_ATTRIB_NONE) {
   68       ureg_MOV(ureg, ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0), ureg_DECL_vs_input(ureg, 1));
   69    }
   70 
   71    if (num_layers > 1) {
   72       struct ureg_src instance_id = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0);
   73       struct ureg_dst layer = ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
   74 
   75       ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X),
   76                ureg_scalar(instance_id, TGSI_SWIZZLE_X));
   77    }
   78    ureg_END(ureg);
   79 
   80    *vs = ureg_create_shader_and_destroy(ureg, &sctx->b);
   81    return *vs;
   82 }
   83 
   84 /**
   85  * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
   86  * VS passes its outputs to TES directly, so the fixed-function shader only
   87  * has to write TESSOUTER and TESSINNER.
   88  */
   89 void *si_create_fixed_func_tcs(struct si_context *sctx)
   90 {
   91    struct ureg_src outer, inner;
   92    struct ureg_dst tessouter, tessinner;
   93    struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
   94 
   95    if (!ureg)
   96       return NULL;
   97 
   98    outer = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL, 0);
   99    inner = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL, 0);
  100 
  101    tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
  102    tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
  103 
  104    ureg_MOV(ureg, tessouter, outer);
  105    ureg_MOV(ureg, tessinner, inner);
  106    ureg_END(ureg);
  107 
  108    return ureg_create_shader_and_destroy(ureg, &sctx->b);
  109 }
  110 
  111 /* Create a compute shader implementing clear_buffer or copy_buffer. */
  112 void *si_create_dma_compute_shader(struct pipe_context *ctx, unsigned num_dwords_per_thread,
  113                                    bool dst_stream_cache_policy, bool is_copy)
  114 {
  115    struct si_screen *sscreen = (struct si_screen *)ctx->screen;
  116    assert(util_is_power_of_two_nonzero(num_dwords_per_thread));
  117 
  118    unsigned store_qualifier = TGSI_MEMORY_COHERENT | TGSI_MEMORY_RESTRICT;
  119    if (dst_stream_cache_policy)
  120       store_qualifier |= TGSI_MEMORY_STREAM_CACHE_POLICY;
  121 
  122    /* Don't cache loads, because there is no reuse. */
  123    unsigned load_qualifier = store_qualifier | TGSI_MEMORY_STREAM_CACHE_POLICY;
  124 
  125    unsigned num_mem_ops = MAX2(1, num_dwords_per_thread / 4);
  126    unsigned *inst_dwords = alloca(num_mem_ops * sizeof(unsigned));
  127 
  128    for (unsigned i = 0; i < num_mem_ops; i++) {
  129       if (i * 4 < num_dwords_per_thread)
  130          inst_dwords[i] = MIN2(4, num_dwords_per_thread - i * 4);
  131    }
  132 
  133    struct ureg_program *ureg = ureg_create(PIPE_SHADER_COMPUTE);
  134    if (!ureg)
  135       return NULL;
  136 
  137    ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH, sscreen->compute_wave_size);
  138    ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT, 1);
  139    ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH, 1);
  140 
  141    struct ureg_src value;
  142    if (!is_copy) {
  143       ureg_property(ureg, TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD, inst_dwords[0]);
  144       value = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_CS_USER_DATA_AMD, 0);
  145    }
  146 
  147    struct ureg_src tid = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_THREAD_ID, 0);
  148    struct ureg_src blk = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_BLOCK_ID, 0);
  149    struct ureg_dst store_addr = ureg_writemask(ureg_DECL_temporary(ureg), TGSI_WRITEMASK_X);
  150    struct ureg_dst load_addr = ureg_writemask(ureg_DECL_temporary(ureg), TGSI_WRITEMASK_X);
  151    struct ureg_dst dstbuf = ureg_dst(ureg_DECL_buffer(ureg, 0, false));
  152    struct ureg_src srcbuf;
  153    struct ureg_src *values = NULL;
  154 
  155    if (is_copy) {
  156       srcbuf = ureg_DECL_buffer(ureg, 1, false);
  157       values = malloc(num_mem_ops * sizeof(struct ureg_src));
  158    }
  159 
  160    /* If there are multiple stores, the first store writes into 0*wavesize+tid,
  161     * the 2nd store writes into 1*wavesize+tid, the 3rd store writes into 2*wavesize+tid, etc.
  162     */
  163    ureg_UMAD(ureg, store_addr, blk, ureg_imm1u(ureg, sscreen->compute_wave_size * num_mem_ops),
  164              tid);
  165    /* Convert from a "store size unit" into bytes. */
  166    ureg_UMUL(ureg, store_addr, ureg_src(store_addr), ureg_imm1u(ureg, 4 * inst_dwords[0]));
  167    ureg_MOV(ureg, load_addr, ureg_src(store_addr));
  168 
  169    /* Distance between a load and a store for latency hiding. */
  170    unsigned load_store_distance = is_copy ? 8 : 0;
  171 
  172    for (unsigned i = 0; i < num_mem_ops + load_store_distance; i++) {
  173       int d = i - load_store_distance;
  174 
  175       if (is_copy && i < num_mem_ops) {
  176          if (i) {
  177             ureg_UADD(ureg, load_addr, ureg_src(load_addr),
  178                       ureg_imm1u(ureg, 4 * inst_dwords[i] * sscreen->compute_wave_size));
  179          }
  180 
  181          values[i] = ureg_src(ureg_DECL_temporary(ureg));
  182          struct ureg_dst dst =
  183             ureg_writemask(ureg_dst(values[i]), u_bit_consecutive(0, inst_dwords[i]));
  184          struct ureg_src srcs[] = {srcbuf, ureg_src(load_addr)};
  185          ureg_memory_insn(ureg, TGSI_OPCODE_LOAD, &dst, 1, srcs, 2, load_qualifier,
  186                           TGSI_TEXTURE_BUFFER, 0);
  187       }
  188 
  189       if (d >= 0) {
  190          if (d) {
  191             ureg_UADD(ureg, store_addr, ureg_src(store_addr),
  192                       ureg_imm1u(ureg, 4 * inst_dwords[d] * sscreen->compute_wave_size));
  193          }
  194 
  195          struct ureg_dst dst = ureg_writemask(dstbuf, u_bit_consecutive(0, inst_dwords[d]));
  196          struct ureg_src srcs[] = {ureg_src(store_addr), is_copy ? values[d] : value};
  197          ureg_memory_insn(ureg, TGSI_OPCODE_STORE, &dst, 1, srcs, 2, store_qualifier,
  198                           TGSI_TEXTURE_BUFFER, 0);
  199       }
  200    }
  201    ureg_END(ureg);
  202 
  203    struct pipe_compute_state state = {};
  204    state.ir_type = PIPE_SHADER_IR_TGSI;
  205    state.prog = ureg_get_tokens(ureg, NULL);
  206 
  207    void *cs = ctx->create_compute_state(ctx, &state);
  208    ureg_destroy(ureg);
  209    ureg_free_tokens(state.prog);
  210 
  211    free(values);
  212    return cs;
  213 }
  214 
  215 /* Create a compute shader that copies DCC from one buffer to another
  216  * where each DCC buffer has a different layout.
  217  *
  218  * image[0]: offset remap table (pairs of <src_offset, dst_offset>),
  219  *           2 pairs are read
  220  * image[1]: DCC source buffer, typed r8_uint
  221  * image[2]: DCC destination buffer, typed r8_uint
  222  */
  223 void *si_create_dcc_retile_cs(struct pipe_context *ctx)
  224 {
  225    struct ureg_program *ureg = ureg_create(PIPE_SHADER_COMPUTE);
  226    if (!ureg)
  227       return NULL;
  228 
  229    ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH, 64);
  230    ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT, 1);
  231    ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH, 1);
  232 
  233    /* Compute the global thread ID (in idx). */
  234    struct ureg_src tid = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_THREAD_ID, 0);
  235    struct ureg_src blk = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_BLOCK_ID, 0);
  236    struct ureg_dst idx = ureg_writemask(ureg_DECL_temporary(ureg), TGSI_WRITEMASK_X);
  237    ureg_UMAD(ureg, idx, blk, ureg_imm1u(ureg, 64), tid);
  238 
  239    /* Load 2 pairs of offsets for DCC load & store. */
  240    struct ureg_src map = ureg_DECL_image(ureg, 0, TGSI_TEXTURE_BUFFER, 0, false, false);
  241    struct ureg_dst offsets = ureg_DECL_temporary(ureg);
  242    struct ureg_src map_load_args[] = {map, ureg_src(idx)};
  243 
  244    ureg_memory_insn(ureg, TGSI_OPCODE_LOAD, &offsets, 1, map_load_args, 2, TGSI_MEMORY_RESTRICT,
  245                     TGSI_TEXTURE_BUFFER, 0);
  246 
  247    struct ureg_src dcc_src = ureg_DECL_image(ureg, 1, TGSI_TEXTURE_BUFFER, 0, false, false);
  248    struct ureg_dst dcc_dst =
  249       ureg_dst(ureg_DECL_image(ureg, 2, TGSI_TEXTURE_BUFFER, 0, true, false));
  250    struct ureg_dst dcc_value[2];
  251 
  252    /* Copy DCC values:
  253     *   dst[offsets.y] = src[offsets.x];
  254     *   dst[offsets.w] = src[offsets.z];
  255     */
  256    for (unsigned i = 0; i < 2; i++) {
  257       dcc_value[i] = ureg_writemask(ureg_DECL_temporary(ureg), TGSI_WRITEMASK_X);
  258 
  259       struct ureg_src load_args[] = {dcc_src,
  260                                      ureg_scalar(ureg_src(offsets), TGSI_SWIZZLE_X + i * 2)};
  261       ureg_memory_insn(ureg, TGSI_OPCODE_LOAD, &dcc_value[i], 1, load_args, 2, TGSI_MEMORY_RESTRICT,
  262                        TGSI_TEXTURE_BUFFER, 0);
  263    }
  264 
  265    dcc_dst = ureg_writemask(dcc_dst, TGSI_WRITEMASK_X);
  266 
  267    for (unsigned i = 0; i < 2; i++) {
  268       struct ureg_src store_args[] = {ureg_scalar(ureg_src(offsets), TGSI_SWIZZLE_Y + i * 2),
  269                                       ureg_src(dcc_value[i])};
  270       ureg_memory_insn(ureg, TGSI_OPCODE_STORE, &dcc_dst, 1, store_args, 2, TGSI_MEMORY_RESTRICT,
  271                        TGSI_TEXTURE_BUFFER, 0);
  272    }
  273    ureg_END(ureg);
  274 
  275    struct pipe_compute_state state = {};
  276    state.ir_type = PIPE_SHADER_IR_TGSI;
  277    state.prog = ureg_get_tokens(ureg, NULL);
  278 
  279    void *cs = ctx->create_compute_state(ctx, &state);
  280    ureg_destroy(ureg);
  281    return cs;
  282 }
  283 
  284 /* Create the compute shader that is used to collect the results.
  285  *
  286  * One compute grid with a single thread is launched for every query result
  287  * buffer. The thread (optionally) reads a previous summary buffer, then
  288  * accumulates data from the query result buffer, and writes the result either
  289  * to a summary buffer to be consumed by the next grid invocation or to the
  290  * user-supplied buffer.
  291  *
  292  * Data layout:
  293  *
  294  * CONST
  295  *  0.x = end_offset
  296  *  0.y = result_stride
  297  *  0.z = result_count
  298  *  0.w = bit field:
  299  *          1: read previously accumulated values
  300  *          2: write accumulated values for chaining
  301  *          4: write result available
  302  *          8: convert result to boolean (0/1)
  303  *         16: only read one dword and use that as result
  304  *         32: apply timestamp conversion
  305  *         64: store full 64 bits result
  306  *        128: store signed 32 bits result
  307  *        256: SO_OVERFLOW mode: take the difference of two successive half-pairs
  308  *  1.x = fence_offset
  309  *  1.y = pair_stride
  310  *  1.z = pair_count
  311  *
  312  * BUFFER[0] = query result buffer
  313  * BUFFER[1] = previous summary buffer
  314  * BUFFER[2] = next summary buffer or user-supplied buffer
  315  */
  316 void *si_create_query_result_cs(struct si_context *sctx)
  317 {
  318    /* TEMP[0].xy = accumulated result so far
  319     * TEMP[0].z = result not available
  320     *
  321     * TEMP[1].x = current result index
  322     * TEMP[1].y = current pair index
  323     */
  324    static const char text_tmpl[] =
  325       "COMP\n"
  326       "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
  327       "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
  328       "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
  329       "DCL BUFFER[0]\n"
  330       "DCL BUFFER[1]\n"
  331       "DCL BUFFER[2]\n"
  332       "DCL CONST[0][0..1]\n"
  333       "DCL TEMP[0..5]\n"
  334       "IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n"
  335       "IMM[1] UINT32 {1, 2, 4, 8}\n"
  336       "IMM[2] UINT32 {16, 32, 64, 128}\n"
  337       "IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp conversion */
  338       "IMM[4] UINT32 {256, 0, 0, 0}\n"
  339 
  340       "AND TEMP[5], CONST[0][0].wwww, IMM[2].xxxx\n"
  341       "UIF TEMP[5]\n"
  342       /* Check result availability. */
  343       "LOAD TEMP[1].x, BUFFER[0], CONST[0][1].xxxx\n"
  344       "ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n"
  345       "MOV TEMP[1], TEMP[0].zzzz\n"
  346       "NOT TEMP[0].z, TEMP[0].zzzz\n"
  347 
  348       /* Load result if available. */
  349       "UIF TEMP[1]\n"
  350       "LOAD TEMP[0].xy, BUFFER[0], IMM[0].xxxx\n"
  351       "ENDIF\n"
  352       "ELSE\n"
  353       /* Load previously accumulated result if requested. */
  354       "MOV TEMP[0], IMM[0].xxxx\n"
  355       "AND TEMP[4], CONST[0][0].wwww, IMM[1].xxxx\n"
  356       "UIF TEMP[4]\n"
  357       "LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n"
  358       "ENDIF\n"
  359 
  360       "MOV TEMP[1].x, IMM[0].xxxx\n"
  361       "BGNLOOP\n"
  362       /* Break if accumulated result so far is not available. */
  363       "UIF TEMP[0].zzzz\n"
  364       "BRK\n"
  365       "ENDIF\n"
  366 
  367       /* Break if result_index >= result_count. */
  368       "USGE TEMP[5], TEMP[1].xxxx, CONST[0][0].zzzz\n"
  369       "UIF TEMP[5]\n"
  370       "BRK\n"
  371       "ENDIF\n"
  372 
  373       /* Load fence and check result availability */
  374       "UMAD TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy, CONST[0][1].xxxx\n"
  375       "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
  376       "ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n"
  377       "NOT TEMP[0].z, TEMP[0].zzzz\n"
  378       "UIF TEMP[0].zzzz\n"
  379       "BRK\n"
  380       "ENDIF\n"
  381 
  382       "MOV TEMP[1].y, IMM[0].xxxx\n"
  383       "BGNLOOP\n"
  384       /* Load start and end. */
  385       "UMUL TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy\n"
  386       "UMAD TEMP[5].x, TEMP[1].yyyy, CONST[0][1].yyyy, TEMP[5].xxxx\n"
  387       "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
  388 
  389       "UADD TEMP[5].y, TEMP[5].xxxx, CONST[0][0].xxxx\n"
  390       "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
  391 
  392       "U64ADD TEMP[4].xy, TEMP[3], -TEMP[2]\n"
  393 
  394       "AND TEMP[5].z, CONST[0][0].wwww, IMM[4].xxxx\n"
  395       "UIF TEMP[5].zzzz\n"
  396       /* Load second start/end half-pair and
  397        * take the difference
  398        */
  399       "UADD TEMP[5].xy, TEMP[5], IMM[1].wwww\n"
  400       "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
  401       "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
  402 
  403       "U64ADD TEMP[3].xy, TEMP[3], -TEMP[2]\n"
  404       "U64ADD TEMP[4].xy, TEMP[4], -TEMP[3]\n"
  405       "ENDIF\n"
  406 
  407       "U64ADD TEMP[0].xy, TEMP[0], TEMP[4]\n"
  408 
  409       /* Increment pair index */
  410       "UADD TEMP[1].y, TEMP[1].yyyy, IMM[1].xxxx\n"
  411       "USGE TEMP[5], TEMP[1].yyyy, CONST[0][1].zzzz\n"
  412       "UIF TEMP[5]\n"
  413       "BRK\n"
  414       "ENDIF\n"
  415       "ENDLOOP\n"
  416 
  417       /* Increment result index */
  418       "UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx\n"
  419       "ENDLOOP\n"
  420       "ENDIF\n"
  421 
  422       "AND TEMP[4], CONST[0][0].wwww, IMM[1].yyyy\n"
  423       "UIF TEMP[4]\n"
  424       /* Store accumulated data for chaining. */
  425       "STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n"
  426       "ELSE\n"
  427       "AND TEMP[4], CONST[0][0].wwww, IMM[1].zzzz\n"
  428       "UIF TEMP[4]\n"
  429       /* Store result availability. */
  430       "NOT TEMP[0].z, TEMP[0]\n"
  431       "AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n"
  432       "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n"
  433 
  434       "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
  435       "UIF TEMP[4]\n"
  436       "STORE BUFFER[2].y, IMM[0].xxxx, IMM[0].xxxx\n"
  437       "ENDIF\n"
  438       "ELSE\n"
  439       /* Store result if it is available. */
  440       "NOT TEMP[4], TEMP[0].zzzz\n"
  441       "UIF TEMP[4]\n"
  442       /* Apply timestamp conversion */
  443       "AND TEMP[4], CONST[0][0].wwww, IMM[2].yyyy\n"
  444       "UIF TEMP[4]\n"
  445       "U64MUL TEMP[0].xy, TEMP[0], IMM[3].xyxy\n"
  446       "U64DIV TEMP[0].xy, TEMP[0], IMM[3].zwzw\n"
  447       "ENDIF\n"
  448 
  449       /* Convert to boolean */
  450       "AND TEMP[4], CONST[0][0].wwww, IMM[1].wwww\n"
  451       "UIF TEMP[4]\n"
  452       "U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[4].zwzw\n"
  453       "AND TEMP[0].x, TEMP[0].xxxx, IMM[1].xxxx\n"
  454       "MOV TEMP[0].y, IMM[0].xxxx\n"
  455       "ENDIF\n"
  456 
  457       "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
  458       "UIF TEMP[4]\n"
  459       "STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0].xyxy\n"
  460       "ELSE\n"
  461       /* Clamping */
  462       "UIF TEMP[0].yyyy\n"
  463       "MOV TEMP[0].x, IMM[0].wwww\n"
  464       "ENDIF\n"
  465 
  466       "AND TEMP[4], CONST[0][0].wwww, IMM[2].wwww\n"
  467       "UIF TEMP[4]\n"
  468       "UMIN TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz\n"
  469       "ENDIF\n"
  470 
  471       "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n"
  472       "ENDIF\n"
  473       "ENDIF\n"
  474       "ENDIF\n"
  475       "ENDIF\n"
  476 
  477       "END\n";
  478 
  479    char text[sizeof(text_tmpl) + 32];
  480    struct tgsi_token tokens[1024];
  481    struct pipe_compute_state state = {};
  482 
  483    /* Hard code the frequency into the shader so that the backend can
  484     * use the full range of optimizations for divide-by-constant.
  485     */
  486    snprintf(text, sizeof(text), text_tmpl, sctx->screen->info.clock_crystal_freq);
  487 
  488    if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
  489       assert(false);
  490       return NULL;
  491    }
  492 
  493    state.ir_type = PIPE_SHADER_IR_TGSI;
  494    state.prog = tokens;
  495 
  496    return sctx->b.create_compute_state(&sctx->b, &state);
  497 }
  498 
  499 /* Create a compute shader implementing copy_image.
  500  * Luckily, this works with all texture targets except 1D_ARRAY.
  501  */
  502 void *si_create_copy_image_compute_shader(struct pipe_context *ctx)
  503 {
  504    static const char text[] =
  505       "COMP\n"
  506       "PROPERTY CS_FIXED_BLOCK_WIDTH 8\n"
  507       "PROPERTY CS_FIXED_BLOCK_HEIGHT 8\n"
  508       "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
  509       "DCL SV[0], THREAD_ID\n"
  510       "DCL SV[1], BLOCK_ID\n"
  511       "DCL IMAGE[0], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
  512       "DCL IMAGE[1], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
  513       "DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw
  514       "DCL TEMP[0..4], LOCAL\n"
  515       "IMM[0] UINT32 {8, 1, 0, 0}\n"
  516       "MOV TEMP[0].xyz, CONST[0][0].xyzw\n"
  517       "UMAD TEMP[1].xyz, SV[1].xyzz, IMM[0].xxyy, SV[0].xyzz\n"
  518       "UADD TEMP[2].xyz, TEMP[1].xyzx, TEMP[0].xyzx\n"
  519       "LOAD TEMP[3], IMAGE[0], TEMP[2].xyzx, 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
  520       "MOV TEMP[4].xyz, CONST[0][1].xyzw\n"
  521       "UADD TEMP[2].xyz, TEMP[1].xyzx, TEMP[4].xyzx\n"
  522       "STORE IMAGE[1], TEMP[2].xyzz, TEMP[3], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
  523       "END\n";
  524 
  525    struct tgsi_token tokens[1024];
  526    struct pipe_compute_state state = {0};
  527 
  528    if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
  529       assert(false);
  530       return NULL;
  531    }
  532 
  533    state.ir_type = PIPE_SHADER_IR_TGSI;
  534    state.prog = tokens;
  535 
  536    return ctx->create_compute_state(ctx, &state);
  537 }
  538 
  539 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx)
  540 {
  541    static const char text[] =
  542       "COMP\n"
  543       "PROPERTY CS_FIXED_BLOCK_WIDTH 64\n"
  544       "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
  545       "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
  546       "DCL SV[0], THREAD_ID\n"
  547       "DCL SV[1], BLOCK_ID\n"
  548       "DCL IMAGE[0], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
  549       "DCL IMAGE[1], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
  550       "DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw
  551       "DCL TEMP[0..4], LOCAL\n"
  552       "IMM[0] UINT32 {64, 1, 0, 0}\n"
  553       "MOV TEMP[0].xy, CONST[0][0].xzzw\n"
  554       "UMAD TEMP[1].xy, SV[1].xyzz, IMM[0].xyyy, SV[0].xyzz\n"
  555       "UADD TEMP[2].xy, TEMP[1].xyzx, TEMP[0].xyzx\n"
  556       "LOAD TEMP[3], IMAGE[0], TEMP[2].xyzx, 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
  557       "MOV TEMP[4].xy, CONST[0][1].xzzw\n"
  558       "UADD TEMP[2].xy, TEMP[1].xyzx, TEMP[4].xyzx\n"
  559       "STORE IMAGE[1], TEMP[2].xyzz, TEMP[3], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
  560       "END\n";
  561 
  562    struct tgsi_token tokens[1024];
  563    struct pipe_compute_state state = {0};
  564 
  565    if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
  566       assert(false);
  567       return NULL;
  568    }
  569 
  570    state.ir_type = PIPE_SHADER_IR_TGSI;
  571    state.prog = tokens;
  572 
  573    return ctx->create_compute_state(ctx, &state);
  574 }
  575 
  576 void *si_clear_render_target_shader(struct pipe_context *ctx)
  577 {
  578    static const char text[] =
  579       "COMP\n"
  580       "PROPERTY CS_FIXED_BLOCK_WIDTH 8\n"
  581       "PROPERTY CS_FIXED_BLOCK_HEIGHT 8\n"
  582       "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
  583       "DCL SV[0], THREAD_ID\n"
  584       "DCL SV[1], BLOCK_ID\n"
  585       "DCL IMAGE[0], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
  586       "DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw
  587       "DCL TEMP[0..3], LOCAL\n"
  588       "IMM[0] UINT32 {8, 1, 0, 0}\n"
  589       "MOV TEMP[0].xyz, CONST[0][0].xyzw\n"
  590       "UMAD TEMP[1].xyz, SV[1].xyzz, IMM[0].xxyy, SV[0].xyzz\n"
  591       "UADD TEMP[2].xyz, TEMP[1].xyzx, TEMP[0].xyzx\n"
  592       "MOV TEMP[3].xyzw, CONST[0][1].xyzw\n"
  593       "STORE IMAGE[0], TEMP[2].xyzz, TEMP[3], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
  594       "END\n";
  595 
  596    struct tgsi_token tokens[1024];
  597    struct pipe_compute_state state = {0};
  598 
  599    if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
  600       assert(false);
  601       return NULL;
  602    }
  603 
  604    state.ir_type = PIPE_SHADER_IR_TGSI;
  605    state.prog = tokens;
  606 
  607    return ctx->create_compute_state(ctx, &state);
  608 }
  609 
  610 /* TODO: Didn't really test 1D_ARRAY */
  611 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx)
  612 {
  613    static const char text[] =
  614       "COMP\n"
  615       "PROPERTY CS_FIXED_BLOCK_WIDTH 64\n"
  616       "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
  617       "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
  618       "DCL SV[0], THREAD_ID\n"
  619       "DCL SV[1], BLOCK_ID\n"
  620       "DCL IMAGE[0], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
  621       "DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw
  622       "DCL TEMP[0..3], LOCAL\n"
  623       "IMM[0] UINT32 {64, 1, 0, 0}\n"
  624       "MOV TEMP[0].xy, CONST[0][0].xzzw\n"
  625       "UMAD TEMP[1].xy, SV[1].xyzz, IMM[0].xyyy, SV[0].xyzz\n"
  626       "UADD TEMP[2].xy, TEMP[1].xyzx, TEMP[0].xyzx\n"
  627       "MOV TEMP[3].xyzw, CONST[0][1].xyzw\n"
  628       "STORE IMAGE[0], TEMP[2].xyzz, TEMP[3], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
  629       "END\n";
  630 
  631    struct tgsi_token tokens[1024];
  632    struct pipe_compute_state state = {0};
  633 
  634    if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
  635       assert(false);
  636       return NULL;
  637    }
  638 
  639    state.ir_type = PIPE_SHADER_IR_TGSI;
  640    state.prog = tokens;
  641 
  642    return ctx->create_compute_state(ctx, &state);
  643 }
  644 
  645 void *si_clear_12bytes_buffer_shader(struct pipe_context *ctx)
  646 {
  647    static const char text[] = "COMP\n"
  648                               "PROPERTY CS_FIXED_BLOCK_WIDTH 64\n"
  649                               "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
  650                               "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
  651                               "DCL SV[0], THREAD_ID\n"
  652                               "DCL SV[1], BLOCK_ID\n"
  653                               "DCL BUFFER[0]\n"
  654                               "DCL CONST[0][0..0]\n" // 0:xyzw
  655                               "DCL TEMP[0..0]\n"
  656                               "IMM[0] UINT32 {64, 1, 12, 0}\n"
  657                               "UMAD TEMP[0].x, SV[1].xyzz, IMM[0].xyyy, SV[0].xyzz\n"
  658                               "UMUL TEMP[0].x, TEMP[0].xyzz, IMM[0].zzzz\n" // 12 bytes
  659                               "STORE BUFFER[0].xyz, TEMP[0].xxxx, CONST[0][0].xyzw\n"
  660                               "END\n";
  661 
  662    struct tgsi_token tokens[1024];
  663    struct pipe_compute_state state = {0};
  664 
  665    if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
  666       assert(false);
  667       return NULL;
  668    }
  669 
  670    state.ir_type = PIPE_SHADER_IR_TGSI;
  671    state.prog = tokens;
  672 
  673    return ctx->create_compute_state(ctx, &state);
  674 }
  675 
  676 /* Load samples from the image, and copy them to the same image. This looks like
  677  * a no-op, but it's not. Loads use FMASK, while stores don't, so samples are
  678  * reordered to match expanded FMASK.
  679  *
  680  * After the shader finishes, FMASK should be cleared to identity.
  681  */
  682 void *si_create_fmask_expand_cs(struct pipe_context *ctx, unsigned num_samples, bool is_array)
  683 {
  684    enum tgsi_texture_type target = is_array ? TGSI_TEXTURE_2D_ARRAY_MSAA : TGSI_TEXTURE_2D_MSAA;
  685    struct ureg_program *ureg = ureg_create(PIPE_SHADER_COMPUTE);
  686    if (!ureg)
  687       return NULL;
  688 
  689    ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH, 8);
  690    ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT, 8);
  691    ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH, 1);
  692 
  693    /* Compute the image coordinates. */
  694    struct ureg_src image = ureg_DECL_image(ureg, 0, target, 0, true, false);
  695    struct ureg_src tid = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_THREAD_ID, 0);
  696    struct ureg_src blk = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_BLOCK_ID, 0);
  697    struct ureg_dst coord = ureg_writemask(ureg_DECL_temporary(ureg), TGSI_WRITEMASK_XYZW);
  698    ureg_UMAD(ureg, ureg_writemask(coord, TGSI_WRITEMASK_XY), ureg_swizzle(blk, 0, 1, 1, 1),
  699              ureg_imm2u(ureg, 8, 8), ureg_swizzle(tid, 0, 1, 1, 1));
  700    if (is_array) {
  701       ureg_MOV(ureg, ureg_writemask(coord, TGSI_WRITEMASK_Z), ureg_scalar(blk, TGSI_SWIZZLE_Z));
  702    }
  703 
  704    /* Load samples, resolving FMASK. */
  705    struct ureg_dst sample[8];
  706    assert(num_samples <= ARRAY_SIZE(sample));
  707 
  708    for (unsigned i = 0; i < num_samples; i++) {
  709       sample[i] = ureg_DECL_temporary(ureg);
  710 
  711       ureg_MOV(ureg, ureg_writemask(coord, TGSI_WRITEMASK_W), ureg_imm1u(ureg, i));
  712 
  713       struct ureg_src srcs[] = {image, ureg_src(coord)};
  714       ureg_memory_insn(ureg, TGSI_OPCODE_LOAD, &sample[i], 1, srcs, 2, TGSI_MEMORY_RESTRICT, target,
  715                        0);
  716    }
  717 
  718    /* Store samples, ignoring FMASK. */
  719    for (unsigned i = 0; i < num_samples; i++) {
  720       ureg_MOV(ureg, ureg_writemask(coord, TGSI_WRITEMASK_W), ureg_imm1u(ureg, i));
  721 
  722       struct ureg_dst dst_image = ureg_dst(image);
  723       struct ureg_src srcs[] = {ureg_src(coord), ureg_src(sample[i])};
  724       ureg_memory_insn(ureg, TGSI_OPCODE_STORE, &dst_image, 1, srcs, 2, TGSI_MEMORY_RESTRICT,
  725                        target, 0);
  726    }
  727    ureg_END(ureg);
  728 
  729    struct pipe_compute_state state = {};
  730    state.ir_type = PIPE_SHADER_IR_TGSI;
  731    state.prog = ureg_get_tokens(ureg, NULL);
  732 
  733    void *cs = ctx->create_compute_state(ctx, &state);
  734    ureg_destroy(ureg);
  735    return cs;
  736 }
  737 
  738 /* Create the compute shader that is used to collect the results of gfx10+
  739  * shader queries.
  740  *
  741  * One compute grid with a single thread is launched for every query result
  742  * buffer. The thread (optionally) reads a previous summary buffer, then
  743  * accumulates data from the query result buffer, and writes the result either
  744  * to a summary buffer to be consumed by the next grid invocation or to the
  745  * user-supplied buffer.
  746  *
  747  * Data layout:
  748  *
  749  * BUFFER[0] = query result buffer (layout is defined by gfx10_sh_query_buffer_mem)
  750  * BUFFER[1] = previous summary buffer
  751  * BUFFER[2] = next summary buffer or user-supplied buffer
  752  *
  753  * CONST
  754  *  0.x = config; the low 3 bits indicate the mode:
  755  *          0: sum up counts
  756  *          1: determine result availability and write it as a boolean
  757  *          2: SO_OVERFLOW
  758  *          3: SO_ANY_OVERFLOW
  759  *        the remaining bits form a bitfield:
  760  *          8: write result as a 64-bit value
  761  *  0.y = offset in bytes to counts or stream for SO_OVERFLOW mode
  762  *  0.z = chain bit field:
  763  *          1: have previous summary buffer
  764  *          2: write next summary buffer
  765  *  0.w = result_count
  766  */
  767 void *gfx10_create_sh_query_result_cs(struct si_context *sctx)
  768 {
  769    /* TEMP[0].x = accumulated result so far
  770     * TEMP[0].y = result missing
  771     * TEMP[0].z = whether we're in overflow mode
  772     */
  773    static const char text_tmpl[] = "COMP\n"
  774                                    "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
  775                                    "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
  776                                    "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
  777                                    "DCL BUFFER[0]\n"
  778                                    "DCL BUFFER[1]\n"
  779                                    "DCL BUFFER[2]\n"
  780                                    "DCL CONST[0][0..0]\n"
  781                                    "DCL TEMP[0..5]\n"
  782                                    "IMM[0] UINT32 {0, 7, 0, 4294967295}\n"
  783                                    "IMM[1] UINT32 {1, 2, 4, 8}\n"
  784                                    "IMM[2] UINT32 {16, 32, 64, 128}\n"
  785 
  786                                    /*
  787                                    acc_result = 0;
  788                                    acc_missing = 0;
  789                                    if (chain & 1) {
  790                                            acc_result = buffer[1][0];
  791                                            acc_missing = buffer[1][1];
  792                                    }
  793                                    */
  794                                    "MOV TEMP[0].xy, IMM[0].xxxx\n"
  795                                    "AND TEMP[5], CONST[0][0].zzzz, IMM[1].xxxx\n"
  796                                    "UIF TEMP[5]\n"
  797                                    "LOAD TEMP[0].xy, BUFFER[1], IMM[0].xxxx\n"
  798                                    "ENDIF\n"
  799 
  800                                    /*
  801                                    is_overflow (TEMP[0].z) = (config & 7) >= 2;
  802                                    result_remaining (TEMP[1].x) = (is_overflow && acc_result) ? 0 :
  803                                    result_count; base_offset (TEMP[1].y) = 0; for (;;) { if
  804                                    (!result_remaining) break; result_remaining--;
  805                                    */
  806                                    "AND TEMP[5].x, CONST[0][0].xxxx, IMM[0].yyyy\n"
  807                                    "USGE TEMP[0].z, TEMP[5].xxxx, IMM[1].yyyy\n"
  808 
  809                                    "AND TEMP[5].x, TEMP[0].zzzz, TEMP[0].xxxx\n"
  810                                    "UCMP TEMP[1].x, TEMP[5].xxxx, IMM[0].xxxx, CONST[0][0].wwww\n"
  811                                    "MOV TEMP[1].y, IMM[0].xxxx\n"
  812 
  813                                    "BGNLOOP\n"
  814                                    "USEQ TEMP[5], TEMP[1].xxxx, IMM[0].xxxx\n"
  815                                    "UIF TEMP[5]\n"
  816                                    "BRK\n"
  817                                    "ENDIF\n"
  818                                    "UADD TEMP[1].x, TEMP[1].xxxx, IMM[0].wwww\n"
  819 
  820                                    /*
  821                                    fence = buffer[0]@(base_offset + 32);
  822                                    if (!fence) {
  823                                            acc_missing = ~0u;
  824                                            break;
  825                                    }
  826                                    */
  827                                    "UADD TEMP[5].x, TEMP[1].yyyy, IMM[2].yyyy\n"
  828                                    "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
  829                                    "USEQ TEMP[5], TEMP[5].xxxx, IMM[0].xxxx\n"
  830                                    "UIF TEMP[5]\n"
  831                                    "MOV TEMP[0].y, TEMP[5].xxxx\n"
  832                                    "BRK\n"
  833                                    "ENDIF\n"
  834 
  835                                    /*
  836                                    stream_offset (TEMP[2].x) = base_offset + offset;
  837 
  838                                    if (!(config & 7)) {
  839                                            acc_result += buffer[0]@stream_offset;
  840                                    }
  841                                    */
  842                                    "UADD TEMP[2].x, TEMP[1].yyyy, CONST[0][0].yyyy\n"
  843 
  844                                    "AND TEMP[5].x, CONST[0][0].xxxx, IMM[0].yyyy\n"
  845                                    "USEQ TEMP[5], TEMP[5].xxxx, IMM[0].xxxx\n"
  846                                    "UIF TEMP[5]\n"
  847                                    "LOAD TEMP[5].x, BUFFER[0], TEMP[2].xxxx\n"
  848                                    "UADD TEMP[0].x, TEMP[0].xxxx, TEMP[5].xxxx\n"
  849                                    "ENDIF\n"
  850 
  851                                    /*
  852                                    if ((config & 7) >= 2) {
  853                                            count (TEMP[2].y) = (config & 1) ? 4 : 1;
  854                                    */
  855                                    "AND TEMP[5].x, CONST[0][0].xxxx, IMM[0].yyyy\n"
  856                                    "USGE TEMP[5], TEMP[5].xxxx, IMM[1].yyyy\n"
  857                                    "UIF TEMP[5]\n"
  858                                    "AND TEMP[5].x, CONST[0][0].xxxx, IMM[1].xxxx\n"
  859                                    "UCMP TEMP[2].y, TEMP[5].xxxx, IMM[1].zzzz, IMM[1].xxxx\n"
  860 
  861                                    /*
  862                                    do {
  863                                            generated = buffer[0]@stream_offset;
  864                                            emitted = buffer[0]@(stream_offset + 16);
  865                                            if (generated != emitted) {
  866                                                    acc_result = 1;
  867                                                    result_remaining = 0;
  868                                                    break;
  869                                            }
  870 
  871                                            stream_offset += 4;
  872                                    } while (--count);
  873                                    */
  874                                    "BGNLOOP\n"
  875                                    "UADD TEMP[5].x, TEMP[2].xxxx, IMM[2].xxxx\n"
  876                                    "LOAD TEMP[4].x, BUFFER[0], TEMP[2].xxxx\n"
  877                                    "LOAD TEMP[4].y, BUFFER[0], TEMP[5].xxxx\n"
  878                                    "USNE TEMP[5], TEMP[4].xxxx, TEMP[4].yyyy\n"
  879                                    "UIF TEMP[5]\n"
  880                                    "MOV TEMP[0].x, IMM[1].xxxx\n"
  881                                    "MOV TEMP[1].y, IMM[0].xxxx\n"
  882                                    "BRK\n"
  883                                    "ENDIF\n"
  884 
  885                                    "UADD TEMP[2].y, TEMP[2].yyyy, IMM[0].wwww\n"
  886                                    "USEQ TEMP[5], TEMP[2].yyyy, IMM[0].xxxx\n"
  887                                    "UIF TEMP[5]\n"
  888                                    "BRK\n"
  889                                    "ENDIF\n"
  890                                    "UADD TEMP[2].x, TEMP[2].xxxx, IMM[1].zzzz\n"
  891                                    "ENDLOOP\n"
  892                                    "ENDIF\n"
  893 
  894                                    /*
  895                                            base_offset += 64;
  896                                    } // end outer loop
  897                                    */
  898                                    "UADD TEMP[1].y, TEMP[1].yyyy, IMM[2].zzzz\n"
  899                                    "ENDLOOP\n"
  900 
  901                                    /*
  902                                    if (chain & 2) {
  903                                            buffer[2][0] = acc_result;
  904                                            buffer[2][1] = acc_missing;
  905                                    } else {
  906                                    */
  907                                    "AND TEMP[5], CONST[0][0].zzzz, IMM[1].yyyy\n"
  908                                    "UIF TEMP[5]\n"
  909                                    "STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0]\n"
  910                                    "ELSE\n"
  911 
  912                                    /*
  913                                    if ((config & 7) == 1) {
  914                                            acc_result = acc_missing ? 0 : 1;
  915                                            acc_missing = 0;
  916                                    }
  917                                    */
  918                                    "AND TEMP[5], CONST[0][0].xxxx, IMM[0].yyyy\n"
  919                                    "USEQ TEMP[5], TEMP[5].xxxx, IMM[1].xxxx\n"
  920                                    "UIF TEMP[5]\n"
  921                                    "UCMP TEMP[0].x, TEMP[0].yyyy, IMM[0].xxxx, IMM[1].xxxx\n"
  922                                    "MOV TEMP[0].y, IMM[0].xxxx\n"
  923                                    "ENDIF\n"
  924 
  925                                    /*
  926                                    if (!acc_missing) {
  927                                            buffer[2][0] = acc_result;
  928                                            if (config & 8)
  929                                                    buffer[2][1] = 0;
  930                                    }
  931                                    */
  932                                    "USEQ TEMP[5], TEMP[0].yyyy, IMM[0].xxxx\n"
  933                                    "UIF TEMP[5]\n"
  934                                    "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n"
  935 
  936                                    "AND TEMP[5], CONST[0][0].xxxx, IMM[1].wwww\n"
  937                                    "UIF TEMP[5]\n"
  938                                    "STORE BUFFER[2].x, IMM[1].zzzz, TEMP[0].yyyy\n"
  939                                    "ENDIF\n"
  940                                    "ENDIF\n"
  941                                    "ENDIF\n"
  942 
  943                                    "END\n";
  944 
  945    struct tgsi_token tokens[1024];
  946    struct pipe_compute_state state = {};
  947 
  948    if (!tgsi_text_translate(text_tmpl, tokens, ARRAY_SIZE(tokens))) {
  949       assert(false);
  950       return NULL;
  951    }
  952 
  953    state.ir_type = PIPE_SHADER_IR_TGSI;
  954    state.prog = tokens;
  955 
  956    return sctx->b.create_compute_state(&sctx->b, &state);
  957 }