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Member "mesa-20.1.8/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c" (16 Sep 2020, 49623 Bytes) of package /linux/misc/mesa-20.1.8.tar.xz:


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    1 /**************************************************************************
    2  *
    3  * Copyright 2017 Advanced Micro Devices, Inc.
    4  * All Rights Reserved.
    5  *
    6  * Permission is hereby granted, free of charge, to any person obtaining a
    7  * copy of this software and associated documentation files (the
    8  * "Software"), to deal in the Software without restriction, including
    9  * without limitation the rights to use, copy, modify, merge, publish,
   10  * distribute, sub license, and/or sell copies of the Software, and to
   11  * permit persons to whom the Software is furnished to do so, subject to
   12  * the following conditions:
   13  *
   14  * The above copyright notice and this permission notice (including the
   15  * next paragraph) shall be included in all copies or substantial portions
   16  * of the Software.
   17  *
   18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
   19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
   20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
   21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
   22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
   23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
   24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
   25  *
   26  **************************************************************************/
   27 
   28 #include "pipe/p_video_codec.h"
   29 #include "radeon_vcn_enc.h"
   30 #include "radeon_video.h"
   31 #include "si_pipe.h"
   32 #include "util/u_video.h"
   33 
   34 #include <stdio.h>
   35 
   36 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
   37 #define RENCODE_FW_INTERFACE_MINOR_VERSION 2
   38 
   39 #define RENCODE_IB_PARAM_SESSION_INFO              0x00000001
   40 #define RENCODE_IB_PARAM_TASK_INFO                 0x00000002
   41 #define RENCODE_IB_PARAM_SESSION_INIT              0x00000003
   42 #define RENCODE_IB_PARAM_LAYER_CONTROL             0x00000004
   43 #define RENCODE_IB_PARAM_LAYER_SELECT              0x00000005
   44 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
   45 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT   0x00000007
   46 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE  0x00000008
   47 #define RENCODE_IB_PARAM_QUALITY_PARAMS            0x00000009
   48 #define RENCODE_IB_PARAM_SLICE_HEADER              0x0000000a
   49 #define RENCODE_IB_PARAM_ENCODE_PARAMS             0x0000000b
   50 #define RENCODE_IB_PARAM_INTRA_REFRESH             0x0000000c
   51 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER     0x0000000d
   52 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER    0x0000000e
   53 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER           0x00000010
   54 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU        0x00000020
   55 
   56 #define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL     0x00100001
   57 #define RENCODE_HEVC_IB_PARAM_SPEC_MISC         0x00100002
   58 #define RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER 0x00100003
   59 
   60 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL     0x00200001
   61 #define RENCODE_H264_IB_PARAM_SPEC_MISC         0x00200002
   62 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS     0x00200003
   63 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004
   64 
   65 static void radeon_enc_session_info(struct radeon_encoder *enc)
   66 {
   67    RADEON_ENC_BEGIN(enc->cmd.session_info);
   68    RADEON_ENC_CS(enc->enc_pic.session_info.interface_version);
   69    RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0);
   70    RADEON_ENC_CS(RENCODE_ENGINE_TYPE_ENCODE);
   71    RADEON_ENC_END();
   72 }
   73 
   74 static void radeon_enc_task_info(struct radeon_encoder *enc, bool need_feedback)
   75 {
   76    enc->enc_pic.task_info.task_id++;
   77 
   78    if (need_feedback)
   79       enc->enc_pic.task_info.allowed_max_num_feedbacks = 1;
   80    else
   81       enc->enc_pic.task_info.allowed_max_num_feedbacks = 0;
   82 
   83    RADEON_ENC_BEGIN(enc->cmd.task_info);
   84    enc->p_task_size = &enc->cs->current.buf[enc->cs->current.cdw++];
   85    RADEON_ENC_CS(enc->enc_pic.task_info.task_id);
   86    RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks);
   87    RADEON_ENC_END();
   88 }
   89 
   90 static void radeon_enc_session_init(struct radeon_encoder *enc)
   91 {
   92    enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
   93    enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16);
   94    enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
   95    enc->enc_pic.session_init.padding_width =
   96       enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
   97    enc->enc_pic.session_init.padding_height =
   98       enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
   99    enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
  100    enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
  101 
  102    RADEON_ENC_BEGIN(enc->cmd.session_init);
  103    RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
  104    RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
  105    RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
  106    RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
  107    RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
  108    RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
  109    RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
  110    RADEON_ENC_END();
  111 }
  112 
  113 static void radeon_enc_session_init_hevc(struct radeon_encoder *enc)
  114 {
  115    enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC;
  116    enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
  117    enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
  118    enc->enc_pic.session_init.padding_width =
  119       enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
  120    enc->enc_pic.session_init.padding_height =
  121       enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
  122    enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
  123    enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
  124 
  125    RADEON_ENC_BEGIN(enc->cmd.session_init);
  126    RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
  127    RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
  128    RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
  129    RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
  130    RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
  131    RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
  132    RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
  133    RADEON_ENC_END();
  134 }
  135 
  136 static void radeon_enc_layer_control(struct radeon_encoder *enc)
  137 {
  138    enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
  139    enc->enc_pic.layer_ctrl.num_temporal_layers = 1;
  140 
  141    RADEON_ENC_BEGIN(enc->cmd.layer_control);
  142    RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
  143    RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
  144    RADEON_ENC_END();
  145 }
  146 
  147 static void radeon_enc_layer_select(struct radeon_encoder *enc)
  148 {
  149    enc->enc_pic.layer_sel.temporal_layer_index = 0;
  150 
  151    RADEON_ENC_BEGIN(enc->cmd.layer_select);
  152    RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index);
  153    RADEON_ENC_END();
  154 }
  155 
  156 static void radeon_enc_slice_control(struct radeon_encoder *enc)
  157 {
  158    enc->enc_pic.slice_ctrl.slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS;
  159    enc->enc_pic.slice_ctrl.num_mbs_per_slice =
  160       align(enc->base.width, 16) / 16 * align(enc->base.height, 16) / 16;
  161 
  162    RADEON_ENC_BEGIN(enc->cmd.slice_control_h264);
  163    RADEON_ENC_CS(enc->enc_pic.slice_ctrl.slice_control_mode);
  164    RADEON_ENC_CS(enc->enc_pic.slice_ctrl.num_mbs_per_slice);
  165    RADEON_ENC_END();
  166 }
  167 
  168 static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc)
  169 {
  170    enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
  171    enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice =
  172       align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
  173    enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment =
  174       enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
  175 
  176    RADEON_ENC_BEGIN(enc->cmd.slice_control_hevc);
  177    RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
  178    RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
  179    RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
  180    RADEON_ENC_END();
  181 }
  182 
  183 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
  184 {
  185    enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
  186    enc->enc_pic.spec_misc.cabac_enable = 0;
  187    enc->enc_pic.spec_misc.cabac_init_idc = 0;
  188    enc->enc_pic.spec_misc.half_pel_enabled = 1;
  189    enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
  190    enc->enc_pic.spec_misc.profile_idc = u_get_h264_profile_idc(enc->base.profile);
  191    enc->enc_pic.spec_misc.level_idc = enc->base.level;
  192 
  193    RADEON_ENC_BEGIN(enc->cmd.spec_misc_h264);
  194    RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag);
  195    RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable);
  196    RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc);
  197    RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled);
  198    RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled);
  199    RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc);
  200    RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc);
  201    RADEON_ENC_END();
  202 }
  203 
  204 static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc)
  205 {
  206    RADEON_ENC_BEGIN(enc->cmd.spec_misc_hevc);
  207    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
  208    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
  209    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
  210    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
  211    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
  212    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
  213    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
  214    RADEON_ENC_END();
  215 }
  216 
  217 static void radeon_enc_rc_session_init(struct radeon_encoder *enc)
  218 {
  219    RADEON_ENC_BEGIN(enc->cmd.rc_session_init);
  220    RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method);
  221    RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level);
  222    RADEON_ENC_END();
  223 }
  224 
  225 static void radeon_enc_rc_layer_init(struct radeon_encoder *enc)
  226 {
  227    RADEON_ENC_BEGIN(enc->cmd.rc_layer_init);
  228    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.target_bit_rate);
  229    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bit_rate);
  230    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_num);
  231    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_den);
  232    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.vbv_buffer_size);
  233    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.avg_target_bits_per_picture);
  234    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer);
  235    RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional);
  236    RADEON_ENC_END();
  237 }
  238 
  239 static void radeon_enc_deblocking_filter_h264(struct radeon_encoder *enc)
  240 {
  241    enc->enc_pic.h264_deblock.disable_deblocking_filter_idc = 0;
  242    enc->enc_pic.h264_deblock.alpha_c0_offset_div2 = 0;
  243    enc->enc_pic.h264_deblock.beta_offset_div2 = 0;
  244    enc->enc_pic.h264_deblock.cb_qp_offset = 0;
  245    enc->enc_pic.h264_deblock.cr_qp_offset = 0;
  246 
  247    RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_h264);
  248    RADEON_ENC_CS(enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
  249    RADEON_ENC_CS(enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
  250    RADEON_ENC_CS(enc->enc_pic.h264_deblock.beta_offset_div2);
  251    RADEON_ENC_CS(enc->enc_pic.h264_deblock.cb_qp_offset);
  252    RADEON_ENC_CS(enc->enc_pic.h264_deblock.cr_qp_offset);
  253    RADEON_ENC_END();
  254 }
  255 
  256 static void radeon_enc_deblocking_filter_hevc(struct radeon_encoder *enc)
  257 {
  258    RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc);
  259    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
  260    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
  261    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
  262    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
  263    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
  264    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
  265    RADEON_ENC_END();
  266 }
  267 
  268 static void radeon_enc_quality_params(struct radeon_encoder *enc)
  269 {
  270    enc->enc_pic.quality_params.vbaq_mode = 0;
  271    enc->enc_pic.quality_params.scene_change_sensitivity = 0;
  272    enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
  273 
  274    RADEON_ENC_BEGIN(enc->cmd.quality_params);
  275    RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
  276    RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
  277    RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
  278    RADEON_ENC_END();
  279 }
  280 
  281 static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
  282 {
  283    RADEON_ENC_BEGIN(enc->cmd.nalu);
  284    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
  285    uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
  286    radeon_enc_reset(enc);
  287    radeon_enc_set_emulation_prevention(enc, false);
  288    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
  289    radeon_enc_code_fixed_bits(enc, 0x67, 8);
  290    radeon_enc_byte_align(enc);
  291    radeon_enc_set_emulation_prevention(enc, true);
  292    radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.profile_idc, 8);
  293    radeon_enc_code_fixed_bits(enc, 0x44, 8); // hardcode to constrained baseline
  294    radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.level_idc, 8);
  295    radeon_enc_code_ue(enc, 0x0);
  296 
  297    if (enc->enc_pic.spec_misc.profile_idc == 100 || enc->enc_pic.spec_misc.profile_idc == 110 ||
  298        enc->enc_pic.spec_misc.profile_idc == 122 || enc->enc_pic.spec_misc.profile_idc == 244 ||
  299        enc->enc_pic.spec_misc.profile_idc == 44 || enc->enc_pic.spec_misc.profile_idc == 83 ||
  300        enc->enc_pic.spec_misc.profile_idc == 86 || enc->enc_pic.spec_misc.profile_idc == 118 ||
  301        enc->enc_pic.spec_misc.profile_idc == 128 || enc->enc_pic.spec_misc.profile_idc == 138) {
  302       radeon_enc_code_ue(enc, 0x1);
  303       radeon_enc_code_ue(enc, 0x0);
  304       radeon_enc_code_ue(enc, 0x0);
  305       radeon_enc_code_fixed_bits(enc, 0x0, 2);
  306    }
  307 
  308    radeon_enc_code_ue(enc, 1);
  309    radeon_enc_code_ue(enc, enc->enc_pic.pic_order_cnt_type);
  310 
  311    if (enc->enc_pic.pic_order_cnt_type == 0)
  312       radeon_enc_code_ue(enc, 1);
  313 
  314    radeon_enc_code_ue(enc, (enc->base.max_references + 1));
  315    radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0,
  316                               1);
  317    radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_width / 16 - 1));
  318    radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_height / 16 - 1));
  319    bool progressive_only = true;
  320    radeon_enc_code_fixed_bits(enc, progressive_only ? 0x1 : 0x0, 1);
  321 
  322    if (!progressive_only)
  323       radeon_enc_code_fixed_bits(enc, 0x0, 1);
  324 
  325    radeon_enc_code_fixed_bits(enc, 0x1, 1);
  326 
  327    if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) ||
  328        (enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) {
  329       radeon_enc_code_fixed_bits(enc, 0x1, 1);
  330       radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
  331       radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
  332       radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
  333       radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
  334    } else
  335       radeon_enc_code_fixed_bits(enc, 0x0, 1);
  336 
  337    radeon_enc_code_fixed_bits(enc, 0x1, 1);
  338    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  339    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  340    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  341    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  342    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  343    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  344    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  345    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  346    radeon_enc_code_fixed_bits(enc, 0x1, 1);
  347    radeon_enc_code_fixed_bits(enc, 0x1, 1);
  348    radeon_enc_code_ue(enc, 0x0);
  349    radeon_enc_code_ue(enc, 0x0);
  350    radeon_enc_code_ue(enc, 16);
  351    radeon_enc_code_ue(enc, 16);
  352    radeon_enc_code_ue(enc, 0x0);
  353    radeon_enc_code_ue(enc, (enc->base.max_references + 1));
  354 
  355    radeon_enc_code_fixed_bits(enc, 0x1, 1);
  356 
  357    radeon_enc_byte_align(enc);
  358    radeon_enc_flush_headers(enc);
  359    *size_in_bytes = (enc->bits_output + 7) / 8;
  360    RADEON_ENC_END();
  361 }
  362 
  363 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
  364 {
  365    RADEON_ENC_BEGIN(enc->cmd.nalu);
  366    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
  367    uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
  368    int i;
  369 
  370    radeon_enc_reset(enc);
  371    radeon_enc_set_emulation_prevention(enc, false);
  372    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
  373    radeon_enc_code_fixed_bits(enc, 0x4201, 16);
  374    radeon_enc_byte_align(enc);
  375    radeon_enc_set_emulation_prevention(enc, true);
  376    radeon_enc_code_fixed_bits(enc, 0x0, 4);
  377    radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
  378    radeon_enc_code_fixed_bits(enc, 0x1, 1);
  379    radeon_enc_code_fixed_bits(enc, 0x0, 2);
  380    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
  381    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
  382    radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
  383    radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
  384    radeon_enc_code_fixed_bits(enc, 0x0, 16);
  385    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
  386 
  387    for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
  388       radeon_enc_code_fixed_bits(enc, 0x0, 2);
  389 
  390    if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
  391       for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
  392          radeon_enc_code_fixed_bits(enc, 0x0, 2);
  393    }
  394 
  395    radeon_enc_code_ue(enc, 0x0);
  396    radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
  397    radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
  398    radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
  399    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  400    radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
  401    radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
  402    radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
  403    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  404    radeon_enc_code_ue(enc, 1);
  405    radeon_enc_code_ue(enc, 0x0);
  406    radeon_enc_code_ue(enc, 0x0);
  407    radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
  408    // Only support CTBSize 64
  409    radeon_enc_code_ue(enc,
  410                       6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
  411    radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
  412    radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
  413    radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
  414    radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
  415 
  416    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  417    radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
  418    radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
  419    radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
  420 
  421    radeon_enc_code_ue(enc, 1);
  422    radeon_enc_code_ue(enc, 1);
  423    radeon_enc_code_ue(enc, 0);
  424    radeon_enc_code_ue(enc, 0);
  425    radeon_enc_code_fixed_bits(enc, 0x1, 1);
  426 
  427    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  428 
  429    radeon_enc_code_fixed_bits(enc, 0, 1);
  430    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
  431 
  432    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  433 
  434    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  435 
  436    radeon_enc_code_fixed_bits(enc, 0x1, 1);
  437 
  438    radeon_enc_byte_align(enc);
  439    radeon_enc_flush_headers(enc);
  440    *size_in_bytes = (enc->bits_output + 7) / 8;
  441    RADEON_ENC_END();
  442 }
  443 
  444 static void radeon_enc_nalu_pps(struct radeon_encoder *enc)
  445 {
  446    RADEON_ENC_BEGIN(enc->cmd.nalu);
  447    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
  448    uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
  449    radeon_enc_reset(enc);
  450    radeon_enc_set_emulation_prevention(enc, false);
  451    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
  452    radeon_enc_code_fixed_bits(enc, 0x68, 8);
  453    radeon_enc_byte_align(enc);
  454    radeon_enc_set_emulation_prevention(enc, true);
  455    radeon_enc_code_ue(enc, 0x0);
  456    radeon_enc_code_ue(enc, 0x0);
  457    radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1);
  458    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  459    radeon_enc_code_ue(enc, 0x0);
  460    radeon_enc_code_ue(enc, 0x0);
  461    radeon_enc_code_ue(enc, 0x0);
  462    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  463    radeon_enc_code_fixed_bits(enc, 0x0, 2);
  464    radeon_enc_code_se(enc, 0x0);
  465    radeon_enc_code_se(enc, 0x0);
  466    radeon_enc_code_se(enc, 0x0);
  467    radeon_enc_code_fixed_bits(enc, 0x1, 1);
  468    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  469    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  470 
  471    radeon_enc_code_fixed_bits(enc, 0x1, 1);
  472 
  473    radeon_enc_byte_align(enc);
  474    radeon_enc_flush_headers(enc);
  475    *size_in_bytes = (enc->bits_output + 7) / 8;
  476    RADEON_ENC_END();
  477 }
  478 
  479 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
  480 {
  481    RADEON_ENC_BEGIN(enc->cmd.nalu);
  482    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
  483    uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
  484    radeon_enc_reset(enc);
  485    radeon_enc_set_emulation_prevention(enc, false);
  486    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
  487    radeon_enc_code_fixed_bits(enc, 0x4401, 16);
  488    radeon_enc_byte_align(enc);
  489    radeon_enc_set_emulation_prevention(enc, true);
  490    radeon_enc_code_ue(enc, 0x0);
  491    radeon_enc_code_ue(enc, 0x0);
  492    radeon_enc_code_fixed_bits(enc, 0x1, 1);
  493    radeon_enc_code_fixed_bits(enc, 0x0, 4);
  494    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  495    radeon_enc_code_fixed_bits(enc, 0x1, 1);
  496    radeon_enc_code_ue(enc, 0x0);
  497    radeon_enc_code_ue(enc, 0x0);
  498    radeon_enc_code_se(enc, 0x0);
  499    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
  500    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  501    if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE)
  502       radeon_enc_code_fixed_bits(enc, 0x0, 1);
  503    else {
  504       radeon_enc_code_fixed_bits(enc, 0x1, 1);
  505       radeon_enc_code_ue(enc, 0x0);
  506    }
  507    radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
  508    radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
  509    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  510    radeon_enc_code_fixed_bits(enc, 0x0, 2);
  511    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  512    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  513    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  514    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
  515    radeon_enc_code_fixed_bits(enc, 0x1, 1);
  516    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  517    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
  518 
  519    if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
  520       radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
  521       radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
  522    }
  523 
  524    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  525    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  526    radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
  527    radeon_enc_code_fixed_bits(enc, 0x0, 2);
  528 
  529    radeon_enc_code_fixed_bits(enc, 0x1, 1);
  530 
  531    radeon_enc_byte_align(enc);
  532    radeon_enc_flush_headers(enc);
  533    *size_in_bytes = (enc->bits_output + 7) / 8;
  534    RADEON_ENC_END();
  535 }
  536 
  537 static void radeon_enc_nalu_vps(struct radeon_encoder *enc)
  538 {
  539    RADEON_ENC_BEGIN(enc->cmd.nalu);
  540    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS);
  541    uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
  542    int i;
  543 
  544    radeon_enc_reset(enc);
  545    radeon_enc_set_emulation_prevention(enc, false);
  546    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
  547    radeon_enc_code_fixed_bits(enc, 0x4001, 16);
  548    radeon_enc_byte_align(enc);
  549    radeon_enc_set_emulation_prevention(enc, true);
  550 
  551    radeon_enc_code_fixed_bits(enc, 0x0, 4);
  552    radeon_enc_code_fixed_bits(enc, 0x3, 2);
  553    radeon_enc_code_fixed_bits(enc, 0x0, 6);
  554    radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
  555    radeon_enc_code_fixed_bits(enc, 0x1, 1);
  556    radeon_enc_code_fixed_bits(enc, 0xffff, 16);
  557    radeon_enc_code_fixed_bits(enc, 0x0, 2);
  558    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
  559    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
  560    radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
  561    radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
  562    radeon_enc_code_fixed_bits(enc, 0x0, 16);
  563    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
  564 
  565    for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
  566       radeon_enc_code_fixed_bits(enc, 0x0, 2);
  567 
  568    if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
  569       for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
  570          radeon_enc_code_fixed_bits(enc, 0x0, 2);
  571    }
  572 
  573    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  574    radeon_enc_code_ue(enc, 0x1);
  575    radeon_enc_code_ue(enc, 0x0);
  576    radeon_enc_code_ue(enc, 0x0);
  577 
  578    radeon_enc_code_fixed_bits(enc, 0x0, 6);
  579    radeon_enc_code_ue(enc, 0x0);
  580    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  581    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  582 
  583    radeon_enc_code_fixed_bits(enc, 0x1, 1);
  584 
  585    radeon_enc_byte_align(enc);
  586    radeon_enc_flush_headers(enc);
  587    *size_in_bytes = (enc->bits_output + 7) / 8;
  588    RADEON_ENC_END();
  589 }
  590 
  591 static void radeon_enc_nalu_aud_hevc(struct radeon_encoder *enc)
  592 {
  593    RADEON_ENC_BEGIN(enc->cmd.nalu);
  594    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD);
  595    uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
  596    radeon_enc_reset(enc);
  597    radeon_enc_set_emulation_prevention(enc, false);
  598    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
  599    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  600    radeon_enc_code_fixed_bits(enc, 35, 6);
  601    radeon_enc_code_fixed_bits(enc, 0x0, 6);
  602    radeon_enc_code_fixed_bits(enc, 0x1, 3);
  603    radeon_enc_byte_align(enc);
  604    radeon_enc_set_emulation_prevention(enc, true);
  605    switch (enc->enc_pic.picture_type) {
  606    case PIPE_H265_ENC_PICTURE_TYPE_I:
  607    case PIPE_H265_ENC_PICTURE_TYPE_IDR:
  608       radeon_enc_code_fixed_bits(enc, 0x00, 3);
  609       break;
  610    case PIPE_H265_ENC_PICTURE_TYPE_P:
  611       radeon_enc_code_fixed_bits(enc, 0x01, 3);
  612       break;
  613    case PIPE_H265_ENC_PICTURE_TYPE_B:
  614       radeon_enc_code_fixed_bits(enc, 0x02, 3);
  615       break;
  616    default:
  617       radeon_enc_code_fixed_bits(enc, 0x02, 3);
  618    }
  619 
  620    radeon_enc_code_fixed_bits(enc, 0x1, 1);
  621 
  622    radeon_enc_byte_align(enc);
  623    radeon_enc_flush_headers(enc);
  624    *size_in_bytes = (enc->bits_output + 7) / 8;
  625    RADEON_ENC_END();
  626 }
  627 
  628 static void radeon_enc_slice_header(struct radeon_encoder *enc)
  629 {
  630    uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
  631    uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
  632    unsigned int inst_index = 0;
  633    unsigned int bit_index = 0;
  634    unsigned int bits_copied = 0;
  635    RADEON_ENC_BEGIN(enc->cmd.slice_header);
  636    radeon_enc_reset(enc);
  637    radeon_enc_set_emulation_prevention(enc, false);
  638 
  639    if (enc->enc_pic.is_idr)
  640       radeon_enc_code_fixed_bits(enc, 0x65, 8);
  641    else if (enc->enc_pic.not_referenced)
  642       radeon_enc_code_fixed_bits(enc, 0x01, 8);
  643    else
  644       radeon_enc_code_fixed_bits(enc, 0x41, 8);
  645 
  646    radeon_enc_flush_headers(enc);
  647    bit_index++;
  648    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
  649    num_bits[inst_index] = enc->bits_output - bits_copied;
  650    bits_copied = enc->bits_output;
  651    inst_index++;
  652 
  653    instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB;
  654    inst_index++;
  655 
  656    switch (enc->enc_pic.picture_type) {
  657    case PIPE_H264_ENC_PICTURE_TYPE_I:
  658    case PIPE_H264_ENC_PICTURE_TYPE_IDR:
  659       radeon_enc_code_fixed_bits(enc, 0x08, 7);
  660       break;
  661    case PIPE_H264_ENC_PICTURE_TYPE_P:
  662    case PIPE_H264_ENC_PICTURE_TYPE_SKIP:
  663       radeon_enc_code_fixed_bits(enc, 0x06, 5);
  664       break;
  665    case PIPE_H264_ENC_PICTURE_TYPE_B:
  666       radeon_enc_code_fixed_bits(enc, 0x07, 5);
  667       break;
  668    default:
  669       radeon_enc_code_fixed_bits(enc, 0x08, 7);
  670    }
  671 
  672    radeon_enc_code_ue(enc, 0x0);
  673    radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 32, 5);
  674 
  675    if (enc->enc_pic.h264_enc_params.input_picture_structure !=
  676        RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
  677       radeon_enc_code_fixed_bits(enc, 0x1, 1);
  678       radeon_enc_code_fixed_bits(enc,
  679                                  enc->enc_pic.h264_enc_params.input_picture_structure ==
  680                                        RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD
  681                                     ? 1
  682                                     : 0,
  683                                  1);
  684    }
  685 
  686    if (enc->enc_pic.is_idr)
  687       radeon_enc_code_ue(enc, enc->enc_pic.is_even_frame);
  688 
  689    enc->enc_pic.is_even_frame = !enc->enc_pic.is_even_frame;
  690 
  691    if (enc->enc_pic.pic_order_cnt_type == 0)
  692       radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt % 32, 5);
  693 
  694    if (enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) {
  695       radeon_enc_code_fixed_bits(enc, 0x0, 1);
  696 
  697       if (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 > 1) {
  698          radeon_enc_code_fixed_bits(enc, 0x1, 1);
  699          radeon_enc_code_ue(enc, 0x0);
  700          radeon_enc_code_ue(enc, (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 - 1));
  701          radeon_enc_code_ue(enc, 0x3);
  702       } else
  703          radeon_enc_code_fixed_bits(enc, 0x0, 1);
  704    }
  705 
  706    if (enc->enc_pic.is_idr) {
  707       radeon_enc_code_fixed_bits(enc, 0x0, 1);
  708       radeon_enc_code_fixed_bits(enc, 0x0, 1);
  709    } else
  710       radeon_enc_code_fixed_bits(enc, 0x0, 1);
  711 
  712    if ((enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) &&
  713        (enc->enc_pic.spec_misc.cabac_enable))
  714       radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc);
  715 
  716    radeon_enc_flush_headers(enc);
  717    bit_index++;
  718    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
  719    num_bits[inst_index] = enc->bits_output - bits_copied;
  720    bits_copied = enc->bits_output;
  721    inst_index++;
  722 
  723    instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
  724    inst_index++;
  725 
  726    radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc ? 1 : 0);
  727 
  728    if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) {
  729       radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
  730       radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2);
  731    }
  732 
  733    radeon_enc_flush_headers(enc);
  734    bit_index++;
  735    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
  736    num_bits[inst_index] = enc->bits_output - bits_copied;
  737    bits_copied = enc->bits_output;
  738    inst_index++;
  739 
  740    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
  741 
  742    for (int i = bit_index; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
  743       RADEON_ENC_CS(0x00000000);
  744 
  745    for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
  746       RADEON_ENC_CS(instruction[j]);
  747       RADEON_ENC_CS(num_bits[j]);
  748    }
  749 
  750    RADEON_ENC_END();
  751 }
  752 
  753 static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
  754 {
  755    uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
  756    uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
  757    unsigned int inst_index = 0;
  758    unsigned int bit_index = 0;
  759    unsigned int bits_copied = 0;
  760    RADEON_ENC_BEGIN(enc->cmd.slice_header);
  761    radeon_enc_reset(enc);
  762    radeon_enc_set_emulation_prevention(enc, false);
  763 
  764    radeon_enc_code_fixed_bits(enc, 0x0, 1);
  765    radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
  766    radeon_enc_code_fixed_bits(enc, 0x0, 6);
  767    radeon_enc_code_fixed_bits(enc, 0x1, 3);
  768 
  769    radeon_enc_flush_headers(enc);
  770    bit_index++;
  771    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
  772    num_bits[inst_index] = enc->bits_output - bits_copied;
  773    bits_copied = enc->bits_output;
  774    inst_index++;
  775 
  776    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
  777    inst_index++;
  778 
  779    if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
  780       radeon_enc_code_fixed_bits(enc, 0x0, 1);
  781 
  782    radeon_enc_code_ue(enc, 0x0);
  783 
  784    radeon_enc_flush_headers(enc);
  785    bit_index++;
  786    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
  787    num_bits[inst_index] = enc->bits_output - bits_copied;
  788    bits_copied = enc->bits_output;
  789    inst_index++;
  790 
  791    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
  792    inst_index++;
  793 
  794    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
  795    inst_index++;
  796 
  797    switch (enc->enc_pic.picture_type) {
  798    case PIPE_H265_ENC_PICTURE_TYPE_I:
  799    case PIPE_H265_ENC_PICTURE_TYPE_IDR:
  800       radeon_enc_code_ue(enc, 0x2);
  801       break;
  802    case PIPE_H265_ENC_PICTURE_TYPE_P:
  803    case PIPE_H265_ENC_PICTURE_TYPE_SKIP:
  804       radeon_enc_code_ue(enc, 0x1);
  805       break;
  806    case PIPE_H265_ENC_PICTURE_TYPE_B:
  807       radeon_enc_code_ue(enc, 0x0);
  808       break;
  809    default:
  810       radeon_enc_code_ue(enc, 0x1);
  811    }
  812 
  813    if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
  814       radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc);
  815       if (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P)
  816          radeon_enc_code_fixed_bits(enc, 0x1, 1);
  817       else {
  818          radeon_enc_code_fixed_bits(enc, 0x0, 1);
  819          radeon_enc_code_fixed_bits(enc, 0x0, 1);
  820          radeon_enc_code_ue(enc, 0x0);
  821          radeon_enc_code_ue(enc, 0x0);
  822       }
  823    }
  824 
  825    if ((enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P) ||
  826        (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B)) {
  827       radeon_enc_code_fixed_bits(enc, 0x0, 1);
  828       radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
  829       radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
  830    }
  831 
  832    radeon_enc_flush_headers(enc);
  833    bit_index++;
  834    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
  835    num_bits[inst_index] = enc->bits_output - bits_copied;
  836    bits_copied = enc->bits_output;
  837    inst_index++;
  838 
  839    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
  840    inst_index++;
  841 
  842    if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
  843        (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)) {
  844       radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled,
  845                                  1);
  846 
  847       radeon_enc_flush_headers(enc);
  848       bit_index++;
  849       instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
  850       num_bits[inst_index] = enc->bits_output - bits_copied;
  851       bits_copied = enc->bits_output;
  852       inst_index++;
  853    }
  854 
  855    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
  856 
  857    for (int i = bit_index; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
  858       RADEON_ENC_CS(0x00000000);
  859 
  860    for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
  861       RADEON_ENC_CS(instruction[j]);
  862       RADEON_ENC_CS(num_bits[j]);
  863    }
  864 
  865    RADEON_ENC_END();
  866 }
  867 
  868 static void radeon_enc_ctx(struct radeon_encoder *enc)
  869 {
  870    enc->enc_pic.ctx_buf.swizzle_mode = 0;
  871    enc->enc_pic.ctx_buf.rec_luma_pitch = align(enc->base.width, enc->alignment);
  872    enc->enc_pic.ctx_buf.rec_chroma_pitch = align(enc->base.width, enc->alignment);
  873    enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
  874 
  875    RADEON_ENC_BEGIN(enc->cmd.ctx);
  876    RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
  877    RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
  878    RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
  879    RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
  880    RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
  881    /* reconstructed_picture_1_luma_offset */
  882    RADEON_ENC_CS(0x00000000);
  883    /* reconstructed_picture_1_chroma_offset */
  884    RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16));
  885    /* reconstructed_picture_2_luma_offset */
  886    RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 3 / 2);
  887    /* reconstructed_picture_2_chroma_offset */
  888    RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 5 / 2);
  889 
  890    for (int i = 0; i < 136; i++)
  891       RADEON_ENC_CS(0x00000000);
  892 
  893    RADEON_ENC_END();
  894 }
  895 
  896 static void radeon_enc_bitstream(struct radeon_encoder *enc)
  897 {
  898    enc->enc_pic.bit_buf.mode = RENCODE_REC_SWIZZLE_MODE_LINEAR;
  899    enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size;
  900    enc->enc_pic.bit_buf.video_bitstream_data_offset = 0;
  901 
  902    RADEON_ENC_BEGIN(enc->cmd.bitstream);
  903    RADEON_ENC_CS(enc->enc_pic.bit_buf.mode);
  904    RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0);
  905    RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size);
  906    RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset);
  907    RADEON_ENC_END();
  908 }
  909 
  910 static void radeon_enc_feedback(struct radeon_encoder *enc)
  911 {
  912    enc->enc_pic.fb_buf.mode = RENCODE_FEEDBACK_BUFFER_MODE_LINEAR;
  913    enc->enc_pic.fb_buf.feedback_buffer_size = 16;
  914    enc->enc_pic.fb_buf.feedback_data_size = 40;
  915 
  916    RADEON_ENC_BEGIN(enc->cmd.feedback);
  917    RADEON_ENC_CS(enc->enc_pic.fb_buf.mode);
  918    RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0);
  919    RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size);
  920    RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size);
  921    RADEON_ENC_END();
  922 }
  923 
  924 static void radeon_enc_intra_refresh(struct radeon_encoder *enc)
  925 {
  926    enc->enc_pic.intra_ref.intra_refresh_mode = RENCODE_INTRA_REFRESH_MODE_NONE;
  927    enc->enc_pic.intra_ref.offset = 0;
  928    enc->enc_pic.intra_ref.region_size = 0;
  929 
  930    RADEON_ENC_BEGIN(enc->cmd.intra_refresh);
  931    RADEON_ENC_CS(enc->enc_pic.intra_ref.intra_refresh_mode);
  932    RADEON_ENC_CS(enc->enc_pic.intra_ref.offset);
  933    RADEON_ENC_CS(enc->enc_pic.intra_ref.region_size);
  934    RADEON_ENC_END();
  935 }
  936 
  937 static void radeon_enc_rc_per_pic(struct radeon_encoder *enc)
  938 {
  939    RADEON_ENC_BEGIN(enc->cmd.rc_per_pic);
  940    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp);
  941    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app);
  942    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app);
  943    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size);
  944    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
  945    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
  946    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
  947    RADEON_ENC_END();
  948 }
  949 
  950 static void radeon_enc_encode_params(struct radeon_encoder *enc)
  951 {
  952    switch (enc->enc_pic.picture_type) {
  953    case PIPE_H264_ENC_PICTURE_TYPE_I:
  954    case PIPE_H264_ENC_PICTURE_TYPE_IDR:
  955       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
  956       break;
  957    case PIPE_H264_ENC_PICTURE_TYPE_P:
  958       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
  959       break;
  960    case PIPE_H264_ENC_PICTURE_TYPE_SKIP:
  961       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
  962       break;
  963    case PIPE_H264_ENC_PICTURE_TYPE_B:
  964       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
  965       break;
  966    default:
  967       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
  968    }
  969 
  970    enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
  971    enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
  972    enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
  973    enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR;
  974 
  975    if (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
  976       enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
  977    else
  978       enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
  979 
  980    enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
  981 
  982    RADEON_ENC_BEGIN(enc->cmd.enc_params);
  983    RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
  984    RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
  985    RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
  986    RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
  987    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
  988    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
  989    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
  990    RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
  991    RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
  992    RADEON_ENC_END();
  993 }
  994 
  995 static void radeon_enc_encode_params_hevc(struct radeon_encoder *enc)
  996 {
  997    switch (enc->enc_pic.picture_type) {
  998    case PIPE_H265_ENC_PICTURE_TYPE_I:
  999    case PIPE_H265_ENC_PICTURE_TYPE_IDR:
 1000       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
 1001       break;
 1002    case PIPE_H265_ENC_PICTURE_TYPE_P:
 1003       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
 1004       break;
 1005    case PIPE_H265_ENC_PICTURE_TYPE_SKIP:
 1006       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
 1007       break;
 1008    case PIPE_H265_ENC_PICTURE_TYPE_B:
 1009       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
 1010       break;
 1011    default:
 1012       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
 1013    }
 1014 
 1015    enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
 1016    enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
 1017    enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
 1018    enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR;
 1019 
 1020    if (enc->enc_pic.enc_params.pic_type == RENCODE_PICTURE_TYPE_I)
 1021       enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
 1022    else
 1023       enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
 1024 
 1025    enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
 1026 
 1027    RADEON_ENC_BEGIN(enc->cmd.enc_params);
 1028    RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
 1029    RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
 1030    RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
 1031    RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
 1032    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
 1033    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
 1034    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
 1035    RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
 1036    RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
 1037    RADEON_ENC_END();
 1038 }
 1039 
 1040 static void radeon_enc_encode_params_h264(struct radeon_encoder *enc)
 1041 {
 1042    enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
 1043    enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE;
 1044    enc->enc_pic.h264_enc_params.reference_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
 1045    enc->enc_pic.h264_enc_params.reference_picture1_index = 0xFFFFFFFF;
 1046 
 1047    RADEON_ENC_BEGIN(enc->cmd.enc_params_h264);
 1048    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure);
 1049    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode);
 1050    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture_structure);
 1051    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture1_index);
 1052    RADEON_ENC_END();
 1053 }
 1054 
 1055 static void radeon_enc_op_init(struct radeon_encoder *enc)
 1056 {
 1057    RADEON_ENC_BEGIN(RENCODE_IB_OP_INITIALIZE);
 1058    RADEON_ENC_END();
 1059 }
 1060 
 1061 static void radeon_enc_op_close(struct radeon_encoder *enc)
 1062 {
 1063    RADEON_ENC_BEGIN(RENCODE_IB_OP_CLOSE_SESSION);
 1064    RADEON_ENC_END();
 1065 }
 1066 
 1067 static void radeon_enc_op_enc(struct radeon_encoder *enc)
 1068 {
 1069    RADEON_ENC_BEGIN(RENCODE_IB_OP_ENCODE);
 1070    RADEON_ENC_END();
 1071 }
 1072 
 1073 static void radeon_enc_op_init_rc(struct radeon_encoder *enc)
 1074 {
 1075    RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC);
 1076    RADEON_ENC_END();
 1077 }
 1078 
 1079 static void radeon_enc_op_init_rc_vbv(struct radeon_encoder *enc)
 1080 {
 1081    RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
 1082    RADEON_ENC_END();
 1083 }
 1084 
 1085 static void radeon_enc_op_speed(struct radeon_encoder *enc)
 1086 {
 1087    RADEON_ENC_BEGIN(RENCODE_IB_OP_SET_SPEED_ENCODING_MODE);
 1088    RADEON_ENC_END();
 1089 }
 1090 
 1091 static void begin(struct radeon_encoder *enc)
 1092 {
 1093    enc->session_info(enc);
 1094    enc->total_task_size = 0;
 1095    enc->task_info(enc, enc->need_feedback);
 1096    enc->op_init(enc);
 1097 
 1098    enc->session_init(enc);
 1099    enc->slice_control(enc);
 1100    enc->spec_misc(enc);
 1101    enc->deblocking_filter(enc);
 1102 
 1103    enc->layer_control(enc);
 1104    enc->rc_session_init(enc);
 1105    enc->quality_params(enc);
 1106    enc->layer_select(enc);
 1107    enc->rc_layer_init(enc);
 1108    enc->layer_select(enc);
 1109    enc->rc_per_pic(enc);
 1110    enc->op_init_rc(enc);
 1111    enc->op_init_rc_vbv(enc);
 1112    *enc->p_task_size = (enc->total_task_size);
 1113 }
 1114 
 1115 static void radeon_enc_headers_h264(struct radeon_encoder *enc)
 1116 {
 1117    if (enc->enc_pic.is_idr) {
 1118       enc->nalu_sps(enc);
 1119       enc->nalu_pps(enc);
 1120    }
 1121    enc->slice_header(enc);
 1122    enc->encode_params(enc);
 1123    enc->encode_params_codec_spec(enc);
 1124 }
 1125 
 1126 static void radeon_enc_headers_hevc(struct radeon_encoder *enc)
 1127 {
 1128    enc->nalu_aud(enc);
 1129    if (enc->enc_pic.is_idr) {
 1130       enc->nalu_vps(enc);
 1131       enc->nalu_pps(enc);
 1132       enc->nalu_sps(enc);
 1133    }
 1134    enc->slice_header(enc);
 1135    enc->encode_params(enc);
 1136 }
 1137 
 1138 static void encode(struct radeon_encoder *enc)
 1139 {
 1140    enc->session_info(enc);
 1141    enc->total_task_size = 0;
 1142    enc->task_info(enc, enc->need_feedback);
 1143 
 1144    enc->encode_headers(enc);
 1145    enc->ctx(enc);
 1146    enc->bitstream(enc);
 1147    enc->feedback(enc);
 1148    enc->intra_refresh(enc);
 1149 
 1150    enc->op_speed(enc);
 1151    enc->op_enc(enc);
 1152    *enc->p_task_size = (enc->total_task_size);
 1153 }
 1154 
 1155 static void destroy(struct radeon_encoder *enc)
 1156 {
 1157    enc->session_info(enc);
 1158    enc->total_task_size = 0;
 1159    enc->task_info(enc, enc->need_feedback);
 1160    enc->op_close(enc);
 1161    *enc->p_task_size = (enc->total_task_size);
 1162 }
 1163 
 1164 void radeon_enc_1_2_init(struct radeon_encoder *enc)
 1165 {
 1166    enc->begin = begin;
 1167    enc->encode = encode;
 1168    enc->destroy = destroy;
 1169    enc->session_info = radeon_enc_session_info;
 1170    enc->task_info = radeon_enc_task_info;
 1171    enc->layer_control = radeon_enc_layer_control;
 1172    enc->layer_select = radeon_enc_layer_select;
 1173    enc->rc_session_init = radeon_enc_rc_session_init;
 1174    enc->rc_layer_init = radeon_enc_rc_layer_init;
 1175    enc->quality_params = radeon_enc_quality_params;
 1176    enc->ctx = radeon_enc_ctx;
 1177    enc->bitstream = radeon_enc_bitstream;
 1178    enc->feedback = radeon_enc_feedback;
 1179    enc->intra_refresh = radeon_enc_intra_refresh;
 1180    enc->rc_per_pic = radeon_enc_rc_per_pic;
 1181    enc->encode_params = radeon_enc_encode_params;
 1182    enc->op_init = radeon_enc_op_init;
 1183    enc->op_close = radeon_enc_op_close;
 1184    enc->op_enc = radeon_enc_op_enc;
 1185    enc->op_init_rc = radeon_enc_op_init_rc;
 1186    enc->op_init_rc_vbv = radeon_enc_op_init_rc_vbv;
 1187    enc->op_speed = radeon_enc_op_speed;
 1188 
 1189    if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
 1190       enc->session_init = radeon_enc_session_init;
 1191       enc->slice_control = radeon_enc_slice_control;
 1192       enc->spec_misc = radeon_enc_spec_misc;
 1193       enc->deblocking_filter = radeon_enc_deblocking_filter_h264;
 1194       enc->nalu_sps = radeon_enc_nalu_sps;
 1195       enc->nalu_pps = radeon_enc_nalu_pps;
 1196       enc->slice_header = radeon_enc_slice_header;
 1197       enc->encode_params = radeon_enc_encode_params;
 1198       enc->encode_params_codec_spec = radeon_enc_encode_params_h264;
 1199       enc->encode_headers = radeon_enc_headers_h264;
 1200    } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
 1201       enc->session_init = radeon_enc_session_init_hevc;
 1202       enc->slice_control = radeon_enc_slice_control_hevc;
 1203       enc->spec_misc = radeon_enc_spec_misc_hevc;
 1204       enc->deblocking_filter = radeon_enc_deblocking_filter_hevc;
 1205       enc->nalu_sps = radeon_enc_nalu_sps_hevc;
 1206       enc->nalu_pps = radeon_enc_nalu_pps_hevc;
 1207       enc->nalu_vps = radeon_enc_nalu_vps;
 1208       enc->nalu_aud = radeon_enc_nalu_aud_hevc;
 1209       enc->slice_header = radeon_enc_slice_header_hevc;
 1210       enc->encode_params = radeon_enc_encode_params_hevc;
 1211       enc->encode_headers = radeon_enc_headers_hevc;
 1212    }
 1213 
 1214    enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO;
 1215    enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO;
 1216    enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT;
 1217    enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
 1218    enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
 1219    enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
 1220    enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
 1221    enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE;
 1222    enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
 1223    enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
 1224    enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
 1225    enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
 1226    enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
 1227    enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
 1228    enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
 1229    enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
 1230    enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
 1231    enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
 1232    enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER;
 1233    enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
 1234    enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
 1235    enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
 1236    enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
 1237 
 1238    enc->enc_pic.session_info.interface_version =
 1239       ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
 1240        (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
 1241 }