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    1 /**************************************************************************
    2  *
    3  * Copyright 2018 Advanced Micro Devices, Inc.
    4  * All Rights Reserved.
    5  *
    6  * Permission is hereby granted, free of charge, to any person obtaining a
    7  * copy of this software and associated documentation files (the
    8  * "Software"), to deal in the Software without restriction, including
    9  * without limitation the rights to use, copy, modify, merge, publish,
   10  * distribute, sub license, and/or sell copies of the Software, and to
   11  * permit persons to whom the Software is furnished to do so, subject to
   12  * the following conditions:
   13  *
   14  * The above copyright notice and this permission notice (including the
   15  * next paragraph) shall be included in all copies or substantial portions
   16  * of the Software.
   17  *
   18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
   19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
   20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
   21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
   22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
   23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
   24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
   25  *
   26  **************************************************************************/
   27 
   28 #ifndef _RADEON_UVD_ENC_H
   29 #define _RADEON_UVD_ENC_H
   30 
   31 #include "radeon_video.h"
   32 
   33 #define RENC_UVD_FW_INTERFACE_MAJOR_VERSION 1
   34 #define RENC_UVD_FW_INTERFACE_MINOR_VERSION 1
   35 
   36 #define RENC_UVD_IB_PARAM_SESSION_INFO               0x00000001
   37 #define RENC_UVD_IB_PARAM_TASK_INFO                  0x00000002
   38 #define RENC_UVD_IB_PARAM_SESSION_INIT               0x00000003
   39 #define RENC_UVD_IB_PARAM_LAYER_CONTROL              0x00000004
   40 #define RENC_UVD_IB_PARAM_LAYER_SELECT               0x00000005
   41 #define RENC_UVD_IB_PARAM_SLICE_CONTROL              0x00000006
   42 #define RENC_UVD_IB_PARAM_SPEC_MISC                  0x00000007
   43 #define RENC_UVD_IB_PARAM_RATE_CONTROL_SESSION_INIT  0x00000008
   44 #define RENC_UVD_IB_PARAM_RATE_CONTROL_LAYER_INIT    0x00000009
   45 #define RENC_UVD_IB_PARAM_RATE_CONTROL_PER_PICTURE   0x0000000a
   46 #define RENC_UVD_IB_PARAM_SLICE_HEADER               0x0000000b
   47 #define RENC_UVD_IB_PARAM_ENCODE_PARAMS              0x0000000c
   48 #define RENC_UVD_IB_PARAM_QUALITY_PARAMS             0x0000000d
   49 #define RENC_UVD_IB_PARAM_DEBLOCKING_FILTER          0x0000000e
   50 #define RENC_UVD_IB_PARAM_INTRA_REFRESH              0x0000000f
   51 #define RENC_UVD_IB_PARAM_ENCODE_CONTEXT_BUFFER      0x00000010
   52 #define RENC_UVD_IB_PARAM_VIDEO_BITSTREAM_BUFFER     0x00000011
   53 #define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER            0x00000012
   54 #define RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER         0x00000013
   55 #define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER_ADDITIONAL 0x00000014
   56 
   57 #define RENC_UVD_IB_OP_INITIALIZE                0x08000001
   58 #define RENC_UVD_IB_OP_CLOSE_SESSION             0x08000002
   59 #define RENC_UVD_IB_OP_ENCODE                    0x08000003
   60 #define RENC_UVD_IB_OP_INIT_RC                   0x08000004
   61 #define RENC_UVD_IB_OP_INIT_RC_VBV_BUFFER_LEVEL  0x08000005
   62 #define RENC_UVD_IB_OP_SET_SPEED_ENCODING_MODE   0x08000006
   63 #define RENC_UVD_IB_OP_SET_BALANCE_ENCODING_MODE 0x08000007
   64 #define RENC_UVD_IB_OP_SET_QUALITY_ENCODING_MODE 0x08000008
   65 
   66 #define RENC_UVD_IF_MAJOR_VERSION_MASK  0xFFFF0000
   67 #define RENC_UVD_IF_MAJOR_VERSION_SHIFT 16
   68 #define RENC_UVD_IF_MINOR_VERSION_MASK  0x0000FFFF
   69 #define RENC_UVD_IF_MINOR_VERSION_SHIFT 0
   70 
   71 #define RENC_UVD_PREENCODE_MODE_NONE 0x00000000
   72 #define RENC_UVD_PREENCODE_MODE_1X   0x00000001
   73 #define RENC_UVD_PREENCODE_MODE_2X   0x00000002
   74 #define RENC_UVD_PREENCODE_MODE_4X   0x00000004
   75 
   76 #define RENC_UVD_SLICE_CONTROL_MODE_FIXED_CTBS 0x00000000
   77 #define RENC_UVD_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001
   78 
   79 #define RENC_UVD_RATE_CONTROL_METHOD_NONE                    0x00000000
   80 #define RENC_UVD_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR 0x00000001
   81 #define RENC_UVD_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR    0x00000002
   82 #define RENC_UVD_RATE_CONTROL_METHOD_CBR                     0x00000003
   83 
   84 #define RENC_UVD_NALU_TYPE_AUD             0x00000001
   85 #define RENC_UVD_NALU_TYPE_VPS             0x00000002
   86 #define RENC_UVD_NALU_TYPE_SPS             0x00000003
   87 #define RENC_UVD_NALU_TYPE_PPS             0x00000004
   88 #define RENC_UVD_NALU_TYPE_END_OF_SEQUENCE 0x00000005
   89 
   90 #define RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS 16
   91 #define RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS        16
   92 
   93 #define RENC_UVD_HEADER_INSTRUCTION_END                 0
   94 #define RENC_UVD_HEADER_INSTRUCTION_DEPENDENT_SLICE_END 1
   95 #define RENC_UVD_HEADER_INSTRUCTION_COPY                2
   96 #define RENC_UVD_HEADER_INSTRUCTION_FIRST_SLICE         3
   97 #define RENC_UVD_HEADER_INSTRUCTION_SLICE_SEGMENT       4
   98 #define RENC_UVD_HEADER_INSTRUCTION_SLICE_QP_DELTA      5
   99 
  100 #define RENC_UVD_PICTURE_TYPE_B      0
  101 #define RENC_UVD_PICTURE_TYPE_P      1
  102 #define RENC_UVD_PICTURE_TYPE_I      2
  103 #define RENC_UVD_PICTURE_TYPE_P_SKIP 3
  104 
  105 #define RENC_UVD_SWIZZLE_MODE_LINEAR               0
  106 #define RENC_UVD_SWIZZLE_MODE_256B_D               2
  107 #define RENC_UVD_SWIZZLE_MODE_4kB_D                6
  108 #define RENC_UVD_SWIZZLE_MODE_64kB_D               10
  109 #define RENC_UVD_INTRA_REFRESH_MODE_NONE           0
  110 #define RENC_UVD_INTRA_REFRESH_MODE_CTB_MB_ROWS    1
  111 #define RENC_UVD_INTRA_REFRESH_MODE_CTB_MB_COLUMNS 2
  112 
  113 #define RENC_UVD_MAX_NUM_RECONSTRUCTED_PICTURES 34
  114 #define RENC_UVD_ADDR_MODE_LINEAR               0
  115 #define RENC_UVD_ADDR_MODE_PELE_8X8_1D          1
  116 #define RENC_UVD_ADDR_MODE_32AS8_88             2
  117 
  118 #define RENC_UVD_ARRAY_MODE_LINEAR         0
  119 #define RENC_UVD_ARRAY_MODE_PELE_8X8_1D    2
  120 #define RENC_UVD_ARRAY_MODE_2D_TILED_THIN1 4
  121 
  122 #define RENC_UVD_VIDEO_BITSTREAM_BUFFER_MODE_LINEAR   0
  123 #define RENC_UVD_VIDEO_BITSTREAM_BUFFER_MODE_CIRCULAR 1
  124 
  125 #define RENC_UVD_FEEDBACK_BUFFER_MODE_LINEAR   0
  126 #define RENC_UVD_FEEDBACK_BUFFER_MODE_CIRCULAR 1
  127 
  128 #define RENC_UVD_FEEDBACK_STATUS_OK          0x00000000
  129 #define RENC_UVD_FEEDBACK_STATUS_NOT_ENCODED 0x10000001
  130 
  131 typedef struct radeon_uvd_enc_feedback_s {
  132    uint32_t task_id;
  133    uint32_t first_in_task;
  134    uint32_t last_in_task;
  135    uint32_t status;
  136    uint32_t has_bitstream;
  137    uint32_t bitstream_offset;
  138    uint32_t bitstream_size;
  139    uint32_t enabled_filler_data;
  140    uint32_t filler_data_size;
  141    uint32_t extra_bytes;
  142 } radeon_uvd_enc_feedback_t;
  143 
  144 typedef struct ruvd_enc_session_info_s {
  145    uint32_t reserved;
  146    uint32_t interface_version;
  147    uint32_t sw_context_address_hi;
  148    uint32_t sw_context_address_lo;
  149 } ruvd_enc_session_info_t;
  150 
  151 typedef struct ruvd_enc_task_info_s {
  152    uint32_t total_size_of_all_packages;
  153    uint32_t task_id;
  154    uint32_t allowed_max_num_feedbacks;
  155 } ruvd_enc_task_info_t;
  156 
  157 typedef struct ruvd_enc_session_init_s {
  158    uint32_t aligned_picture_width;
  159    uint32_t aligned_picture_height;
  160    uint32_t padding_width;
  161    uint32_t padding_height;
  162    uint32_t pre_encode_mode;
  163    uint32_t pre_encode_chroma_enabled;
  164 } ruvd_enc_session_init_t;
  165 
  166 typedef struct ruvd_enc_layer_control_s {
  167    uint32_t max_num_temporal_layers;
  168    uint32_t num_temporal_layers;
  169 } ruvd_enc_layer_control_t;
  170 
  171 typedef struct ruvd_enc_layer_select_s {
  172    uint32_t temporal_layer_index;
  173 } ruvd_enc_layer_select_t;
  174 
  175 typedef struct ruvd_enc_hevc_slice_control_s {
  176    uint32_t slice_control_mode;
  177    union {
  178       struct {
  179          uint32_t num_ctbs_per_slice;
  180          uint32_t num_ctbs_per_slice_segment;
  181       } fixed_ctbs_per_slice;
  182 
  183       struct {
  184          uint32_t num_bits_per_slice;
  185          uint32_t num_bits_per_slice_segment;
  186       } fixed_bits_per_slice;
  187    };
  188 } ruvd_enc_hevc_slice_control_t;
  189 
  190 typedef struct ruvd_enc_hevc_spec_misc_s {
  191    uint32_t log2_min_luma_coding_block_size_minus3;
  192    uint32_t amp_disabled;
  193    uint32_t strong_intra_smoothing_enabled;
  194    uint32_t constrained_intra_pred_flag;
  195    uint32_t cabac_init_flag;
  196    uint32_t half_pel_enabled;
  197    uint32_t quarter_pel_enabled;
  198 } ruvd_enc_hevc_spec_misc_t;
  199 
  200 typedef struct ruvd_enc_rate_ctl_session_init_s {
  201    uint32_t rate_control_method;
  202    uint32_t vbv_buffer_level;
  203 } ruvd_enc_rate_ctl_session_init_t;
  204 
  205 typedef struct ruvd_enc_rate_ctl_layer_init_s {
  206    uint32_t target_bit_rate;
  207    uint32_t peak_bit_rate;
  208    uint32_t frame_rate_num;
  209    uint32_t frame_rate_den;
  210    uint32_t vbv_buffer_size;
  211    uint32_t avg_target_bits_per_picture;
  212    uint32_t peak_bits_per_picture_integer;
  213    uint32_t peak_bits_per_picture_fractional;
  214 } ruvd_enc_rate_ctl_layer_init_t;
  215 
  216 typedef struct ruvd_enc_rate_ctl_per_picture_s {
  217    uint32_t qp;
  218    uint32_t min_qp_app;
  219    uint32_t max_qp_app;
  220    uint32_t max_au_size;
  221    uint32_t enabled_filler_data;
  222    uint32_t skip_frame_enable;
  223    uint32_t enforce_hrd;
  224 } ruvd_enc_rate_ctl_per_picture_t;
  225 
  226 typedef struct ruvd_enc_quality_params_s {
  227    uint32_t vbaq_mode;
  228    uint32_t scene_change_sensitivity;
  229    uint32_t scene_change_min_idr_interval;
  230 } ruvd_enc_quality_params_t;
  231 
  232 typedef struct ruvd_enc_direct_output_nalu_s {
  233    uint32_t type;
  234    uint32_t size;
  235    uint32_t data[1];
  236 } ruvd_enc_direct_output_nalu_t;
  237 
  238 typedef struct ruvd_enc_slice_header_s {
  239    uint32_t bitstream_template[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS];
  240    struct {
  241       uint32_t instruction;
  242       uint32_t num_bits;
  243    } instructions[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS];
  244 } ruvd_enc_slice_header_t;
  245 
  246 typedef struct ruvd_enc_encode_params_s {
  247    uint32_t pic_type;
  248    uint32_t allowed_max_bitstream_size;
  249    uint32_t input_picture_luma_address_hi;
  250    uint32_t input_picture_luma_address_lo;
  251    uint32_t input_picture_chroma_address_hi;
  252    uint32_t input_picture_chroma_address_lo;
  253    uint32_t input_pic_luma_pitch;
  254    uint32_t input_pic_chroma_pitch;
  255    union {
  256       uint32_t input_pic_addr_mode;
  257       uint32_t reserved;
  258    };
  259    union {
  260       uint32_t input_pic_array_mode;
  261       uint32_t input_pic_swizzle_mode;
  262    };
  263    uint32_t reference_picture_index;
  264    uint32_t reconstructed_picture_index;
  265 } ruvd_enc_encode_params_t;
  266 
  267 typedef struct ruvd_enc_hevc_deblocking_filter_s {
  268    uint32_t loop_filter_across_slices_enabled;
  269    int32_t deblocking_filter_disabled;
  270    int32_t beta_offset_div2;
  271    int32_t tc_offset_div2;
  272    int32_t cb_qp_offset;
  273    int32_t cr_qp_offset;
  274 } ruvd_enc_hevc_deblocking_filter_t;
  275 
  276 typedef struct ruvd_enc_intra_refresh_s {
  277    uint32_t intra_refresh_mode;
  278    uint32_t offset;
  279    uint32_t region_size;
  280 } ruvd_enc_intra_refresh_t;
  281 
  282 typedef struct ruvd_enc_reconstructed_picture_s {
  283    uint32_t luma_offset;
  284    uint32_t chroma_offset;
  285 } ruvd_enc_reconstructed_picture_t;
  286 
  287 typedef struct ruvd_enc_encode_context_buffer_s {
  288    uint32_t encode_context_address_hi;
  289    uint32_t encode_context_address_lo;
  290    union {
  291       uint32_t addr_mode;
  292       uint32_t reserved;
  293    };
  294    union {
  295       uint32_t array_mode;
  296       uint32_t swizzle_mode;
  297    };
  298    uint32_t rec_luma_pitch;
  299    uint32_t rec_chroma_pitch;
  300    uint32_t num_reconstructed_pictures;
  301    ruvd_enc_reconstructed_picture_t reconstructed_pictures[RENC_UVD_MAX_NUM_RECONSTRUCTED_PICTURES];
  302    uint32_t pre_encode_picture_luma_pitch;
  303    uint32_t pre_encode_picture_chroma_pitch;
  304    ruvd_enc_reconstructed_picture_t
  305       pre_encode_reconstructed_pictures[RENC_UVD_MAX_NUM_RECONSTRUCTED_PICTURES];
  306    ruvd_enc_reconstructed_picture_t pre_encode_input_picture;
  307 } ruvd_enc_encode_context_buffer_t;
  308 
  309 typedef struct ruvd_enc_video_bitstream_buffer_s {
  310    uint32_t mode;
  311    uint32_t video_bitstream_buffer_address_hi;
  312    uint32_t video_bitstream_buffer_address_lo;
  313    uint32_t video_bitstream_buffer_size;
  314    uint32_t video_bitstream_data_offset;
  315 } ruvd_enc_video_bitstream_buffer_t;
  316 
  317 typedef struct ruvd_enc_feedback_buffer_s {
  318    uint32_t mode;
  319    uint32_t feedback_buffer_address_hi;
  320    uint32_t feedback_buffer_address_lo;
  321    uint32_t feedback_buffer_size;
  322    uint32_t feedback_data_size;
  323 } ruvd_enc_feedback_buffer_t;
  324 
  325 typedef void (*radeon_uvd_enc_get_buffer)(struct pipe_resource *resource, struct pb_buffer **handle,
  326                                           struct radeon_surf **surface);
  327 
  328 struct pipe_video_codec *radeon_uvd_create_encoder(struct pipe_context *context,
  329                                                    const struct pipe_video_codec *templat,
  330                                                    struct radeon_winsys *ws,
  331                                                    radeon_uvd_enc_get_buffer get_buffer);
  332 
  333 struct radeon_uvd_enc_pic {
  334    enum pipe_h265_enc_picture_type picture_type;
  335 
  336    unsigned frame_num;
  337    unsigned pic_order_cnt;
  338    unsigned pic_order_cnt_type;
  339    unsigned crop_left;
  340    unsigned crop_right;
  341    unsigned crop_top;
  342    unsigned crop_bottom;
  343    unsigned general_tier_flag;
  344    unsigned general_profile_idc;
  345    unsigned general_level_idc;
  346    unsigned max_poc;
  347    unsigned log2_max_poc;
  348    unsigned chroma_format_idc;
  349    unsigned pic_width_in_luma_samples;
  350    unsigned pic_height_in_luma_samples;
  351    unsigned log2_diff_max_min_luma_coding_block_size;
  352    unsigned log2_min_transform_block_size_minus2;
  353    unsigned log2_diff_max_min_transform_block_size;
  354    unsigned max_transform_hierarchy_depth_inter;
  355    unsigned max_transform_hierarchy_depth_intra;
  356    unsigned log2_parallel_merge_level_minus2;
  357    unsigned bit_depth_luma_minus8;
  358    unsigned bit_depth_chroma_minus8;
  359    unsigned nal_unit_type;
  360    unsigned max_num_merge_cand;
  361 
  362    bool not_referenced;
  363    bool is_iframe;
  364    bool is_even_frame;
  365    bool sample_adaptive_offset_enabled_flag;
  366    bool pcm_enabled_flag;
  367    bool sps_temporal_mvp_enabled_flag;
  368 
  369    ruvd_enc_task_info_t task_info;
  370    ruvd_enc_session_init_t session_init;
  371    ruvd_enc_layer_control_t layer_ctrl;
  372    ruvd_enc_layer_select_t layer_sel;
  373    ruvd_enc_hevc_slice_control_t hevc_slice_ctrl;
  374    ruvd_enc_hevc_spec_misc_t hevc_spec_misc;
  375    ruvd_enc_rate_ctl_session_init_t rc_session_init;
  376    ruvd_enc_rate_ctl_layer_init_t rc_layer_init;
  377    ruvd_enc_hevc_deblocking_filter_t hevc_deblock;
  378    ruvd_enc_rate_ctl_per_picture_t rc_per_pic;
  379    ruvd_enc_quality_params_t quality_params;
  380    ruvd_enc_encode_context_buffer_t ctx_buf;
  381    ruvd_enc_video_bitstream_buffer_t bit_buf;
  382    ruvd_enc_feedback_buffer_t fb_buf;
  383    ruvd_enc_intra_refresh_t intra_ref;
  384    ruvd_enc_encode_params_t enc_params;
  385 };
  386 
  387 struct radeon_uvd_encoder {
  388    struct pipe_video_codec base;
  389 
  390    void (*begin)(struct radeon_uvd_encoder *enc, struct pipe_picture_desc *pic);
  391    void (*encode)(struct radeon_uvd_encoder *enc);
  392    void (*destroy)(struct radeon_uvd_encoder *enc);
  393 
  394    unsigned stream_handle;
  395 
  396    struct pipe_screen *screen;
  397    struct radeon_winsys *ws;
  398    struct radeon_cmdbuf *cs;
  399 
  400    radeon_uvd_enc_get_buffer get_buffer;
  401 
  402    struct pb_buffer *handle;
  403    struct radeon_surf *luma;
  404    struct radeon_surf *chroma;
  405 
  406    struct pb_buffer *bs_handle;
  407    unsigned bs_size;
  408 
  409    unsigned cpb_num;
  410 
  411    struct rvid_buffer *si;
  412    struct rvid_buffer *fb;
  413    struct rvid_buffer cpb;
  414    struct radeon_uvd_enc_pic enc_pic;
  415 
  416    unsigned shifter;
  417    unsigned bits_in_shifter;
  418    unsigned num_zeros;
  419    unsigned byte_index;
  420    unsigned bits_output;
  421    uint32_t total_task_size;
  422    uint32_t *p_task_size;
  423 
  424    bool emulation_prevention;
  425    bool need_feedback;
  426 };
  427 
  428 struct si_screen;
  429 
  430 void radeon_uvd_enc_1_1_init(struct radeon_uvd_encoder *enc);
  431 bool si_radeon_uvd_enc_supported(struct si_screen *sscreen);
  432 
  433 #endif // _RADEON_UVD_ENC_H