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    1 /*
    2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
    3  *
    4  * Permission is hereby granted, free of charge, to any person obtaining a
    5  * copy of this software and associated documentation files (the "Software"),
    6  * to deal in the Software without restriction, including without limitation
    7  * on the rights to use, copy, modify, merge, publish, distribute, sub
    8  * license, and/or sell copies of the Software, and to permit persons to whom
    9  * the Software is furnished to do so, subject to the following conditions:
   10  *
   11  * The above copyright notice and this permission notice (including the next
   12  * paragraph) shall be included in all copies or substantial portions of the
   13  * Software.
   14  *
   15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
   18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
   19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
   20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
   21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
   22  *
   23  * Authors:
   24  *      Jerome Glisse
   25  */
   26 #ifndef R600_PIPE_H
   27 #define R600_PIPE_H
   28 
   29 #include "r600_pipe_common.h"
   30 #include "r600_cs.h"
   31 #include "r600_public.h"
   32 #include "pipe/p_defines.h"
   33 
   34 #include "util/u_suballoc.h"
   35 #include "util/list.h"
   36 #include "util/u_transfer.h"
   37 #include "util/u_memory.h"
   38 
   39 #include "tgsi/tgsi_scan.h"
   40 
   41 #define R600_NUM_ATOMS 56
   42 
   43 #define R600_MAX_IMAGES 8
   44 /*
   45  * ranges reserved for images on evergreen
   46  * first set for the immediate buffers,
   47  * second for the actual resources for RESQ.
   48  */
   49 #define R600_IMAGE_IMMED_RESOURCE_OFFSET 160
   50 #define R600_IMAGE_REAL_RESOURCE_OFFSET 168
   51 
   52 /* read caches */
   53 #define R600_CONTEXT_INV_VERTEX_CACHE       (R600_CONTEXT_PRIVATE_FLAG << 0)
   54 #define R600_CONTEXT_INV_TEX_CACHE      (R600_CONTEXT_PRIVATE_FLAG << 1)
   55 #define R600_CONTEXT_INV_CONST_CACHE        (R600_CONTEXT_PRIVATE_FLAG << 2)
   56 /* read-write caches */
   57 #define R600_CONTEXT_FLUSH_AND_INV      (R600_CONTEXT_PRIVATE_FLAG << 3)
   58 #define R600_CONTEXT_FLUSH_AND_INV_CB_META  (R600_CONTEXT_PRIVATE_FLAG << 4)
   59 #define R600_CONTEXT_FLUSH_AND_INV_DB_META  (R600_CONTEXT_PRIVATE_FLAG << 5)
   60 #define R600_CONTEXT_FLUSH_AND_INV_DB       (R600_CONTEXT_PRIVATE_FLAG << 6)
   61 #define R600_CONTEXT_FLUSH_AND_INV_CB       (R600_CONTEXT_PRIVATE_FLAG << 7)
   62 /* engine synchronization */
   63 #define R600_CONTEXT_PS_PARTIAL_FLUSH       (R600_CONTEXT_PRIVATE_FLAG << 8)
   64 #define R600_CONTEXT_WAIT_3D_IDLE       (R600_CONTEXT_PRIVATE_FLAG << 9)
   65 #define R600_CONTEXT_WAIT_CP_DMA_IDLE       (R600_CONTEXT_PRIVATE_FLAG << 10)
   66 #define R600_CONTEXT_CS_PARTIAL_FLUSH           (R600_CONTEXT_PRIVATE_FLAG << 11)
   67 
   68 /* the number of CS dwords for flushing and drawing */
   69 #define R600_MAX_FLUSH_CS_DWORDS    18
   70 #define R600_MAX_DRAW_CS_DWORDS     58
   71 #define R600_MAX_PFP_SYNC_ME_DWORDS 16
   72 
   73 #define EG_MAX_ATOMIC_BUFFERS 8
   74 
   75 #define R600_MAX_USER_CONST_BUFFERS 15
   76 #define R600_MAX_DRIVER_CONST_BUFFERS 3
   77 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
   78 #define R600_MAX_HW_CONST_BUFFERS 16
   79 
   80 /* start driver buffers after user buffers */
   81 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
   82 #define R600_UCP_SIZE (4*4*8)
   83 #define R600_CS_BLOCK_GRID_SIZE (8 * 4)
   84 #define R600_TCS_DEFAULT_LEVELS_SIZE (6 * 4)
   85 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
   86 
   87 /*
   88  * We only access this buffer through vtx clauses hence it's fine to exist
   89  * at index beyond 15.
   90  */
   91 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
   92 /*
   93  * Note GS doesn't use a constant buffer binding, just a resource index,
   94  * so it's fine to have it exist at index beyond 15. I.e. it's not actually
   95  * a const buffer, just a buffer resource.
   96  */
   97 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
   98 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
   99  * of 16 const buffers.
  100  * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
  101  *
  102  * In order to support d3d 11 mandated minimum of 15 user const buffers
  103  * we'd have to squash all use cases into one driver buffer.
  104  */
  105 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
  106 
  107 /* HW stages */
  108 #define R600_HW_STAGE_PS 0
  109 #define R600_HW_STAGE_VS 1
  110 #define R600_HW_STAGE_GS 2
  111 #define R600_HW_STAGE_ES 3
  112 #define EG_HW_STAGE_LS 4
  113 #define EG_HW_STAGE_HS 5
  114 
  115 #define R600_NUM_HW_STAGES 4
  116 #define EG_NUM_HW_STAGES 6
  117 
  118 struct r600_context;
  119 struct r600_bytecode;
  120 union  r600_shader_key;
  121 
  122 /* This is an atom containing GPU commands that never change.
  123  * This is supposed to be copied directly into the CS. */
  124 struct r600_command_buffer {
  125     uint32_t *buf;
  126     unsigned num_dw;
  127     unsigned max_num_dw;
  128     unsigned pkt_flags;
  129 };
  130 
  131 struct r600_db_state {
  132     struct r600_atom        atom;
  133     struct r600_surface     *rsurf;
  134 };
  135 
  136 struct r600_db_misc_state {
  137     struct r600_atom        atom;
  138     bool                occlusion_queries_disabled;
  139     bool                flush_depthstencil_through_cb;
  140     bool                flush_depth_inplace;
  141     bool                flush_stencil_inplace;
  142     bool                copy_depth, copy_stencil;
  143     unsigned            copy_sample;
  144     unsigned            log_samples;
  145     unsigned            db_shader_control;
  146     bool                htile_clear;
  147     uint8_t             ps_conservative_z;
  148 };
  149 
  150 struct r600_cb_misc_state {
  151     struct r600_atom atom;
  152     unsigned cb_color_control; /* this comes from blend state */
  153     unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
  154     unsigned nr_cbufs;
  155     unsigned bound_cbufs_target_mask;
  156     unsigned nr_ps_color_outputs;
  157     unsigned ps_color_export_mask;
  158     unsigned image_rat_enabled_mask;
  159     unsigned buffer_rat_enabled_mask;
  160     bool multiwrite;
  161     bool dual_src_blend;
  162 };
  163 
  164 struct r600_clip_misc_state {
  165     struct r600_atom atom;
  166     unsigned pa_cl_clip_cntl;   /* from rasterizer    */
  167     unsigned pa_cl_vs_out_cntl; /* from vertex shader */
  168     unsigned clip_plane_enable; /* from rasterizer    */
  169     unsigned cc_dist_mask;      /* from vertex shader */
  170     unsigned clip_dist_write;   /* from vertex shader */
  171     unsigned cull_dist_write;   /* from vertex shader */
  172     boolean clip_disable;       /* from vertex shader */
  173     boolean vs_out_viewport;    /* from vertex shader */
  174 };
  175 
  176 struct r600_alphatest_state {
  177     struct r600_atom atom;
  178     unsigned sx_alpha_test_control; /* this comes from dsa state */
  179     unsigned sx_alpha_ref; /* this comes from dsa state */
  180     bool bypass;
  181     bool cb0_export_16bpc; /* from set_framebuffer_state */
  182 };
  183 
  184 struct r600_vgt_state {
  185     struct r600_atom atom;
  186     uint32_t vgt_multi_prim_ib_reset_en;
  187     uint32_t vgt_multi_prim_ib_reset_indx;
  188     uint32_t vgt_indx_offset;
  189     bool last_draw_was_indirect;
  190 };
  191 
  192 struct r600_blend_color {
  193     struct r600_atom atom;
  194     struct pipe_blend_color state;
  195 };
  196 
  197 struct r600_clip_state {
  198     struct r600_atom atom;
  199     struct pipe_clip_state state;
  200 };
  201 
  202 struct r600_cs_shader_state {
  203     struct r600_atom atom;
  204     unsigned kernel_index;
  205     unsigned pc;
  206     struct r600_pipe_compute *shader;
  207 };
  208 
  209 struct r600_framebuffer {
  210     struct r600_atom atom;
  211     struct pipe_framebuffer_state state;
  212     unsigned compressed_cb_mask;
  213     unsigned nr_samples;
  214     bool export_16bpc;
  215     bool cb0_is_integer;
  216     bool is_msaa_resolve;
  217     bool dual_src_blend;
  218     bool do_update_surf_dirtiness;
  219 };
  220 
  221 struct r600_sample_mask {
  222     struct r600_atom atom;
  223     uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
  224 };
  225 
  226 struct r600_config_state {
  227     struct r600_atom atom;
  228     unsigned sq_gpr_resource_mgmt_1;
  229     unsigned sq_gpr_resource_mgmt_2;
  230     unsigned sq_gpr_resource_mgmt_3;
  231     bool dyn_gpr_enabled;
  232 };
  233 
  234 struct r600_stencil_ref
  235 {
  236     ubyte ref_value[2];
  237     ubyte valuemask[2];
  238     ubyte writemask[2];
  239 };
  240 
  241 struct r600_stencil_ref_state {
  242     struct r600_atom atom;
  243     struct r600_stencil_ref state;
  244     struct pipe_stencil_ref pipe_state;
  245 };
  246 
  247 struct r600_shader_stages_state {
  248     struct r600_atom atom;
  249     unsigned geom_enable;
  250 };
  251 
  252 struct r600_gs_rings_state {
  253     struct r600_atom atom;
  254     unsigned enable;
  255     struct pipe_constant_buffer esgs_ring;
  256     struct pipe_constant_buffer gsvs_ring;
  257 };
  258 
  259 /* This must start from 16. */
  260 /* features */
  261 #define DBG_NO_CP_DMA       (1 << 30)
  262 /* shader backend */
  263 #define DBG_NO_SB       (1 << 21)
  264 #define DBG_SB_CS       (1 << 22)
  265 #define DBG_SB_DRY_RUN  (1 << 23)
  266 #define DBG_SB_STAT     (1 << 24)
  267 #define DBG_SB_DUMP     (1 << 25)
  268 #define DBG_SB_NO_FALLBACK  (1 << 26)
  269 #define DBG_SB_DISASM   (1 << 27)
  270 #define DBG_SB_SAFEMATH (1 << 28)
  271 
  272 struct r600_screen {
  273     struct r600_common_screen   b;
  274     bool                has_msaa;
  275     bool                has_compressed_msaa_texturing;
  276     bool                has_atomics;
  277 
  278     /*for compute global memory binding, we allocate stuff here, instead of
  279      * buffers.
  280      * XXX: Not sure if this is the best place for global_pool.  Also,
  281      * it's not thread safe, so it won't work with multiple contexts. */
  282     struct compute_memory_pool *global_pool;
  283 };
  284 
  285 struct r600_pipe_sampler_view {
  286     struct pipe_sampler_view    base;
  287     struct list_head        list;
  288     struct r600_resource        *tex_resource;
  289     uint32_t            tex_resource_words[8];
  290     bool                skip_mip_address_reloc;
  291     bool                is_stencil_sampler;
  292 };
  293 
  294 struct r600_rasterizer_state {
  295     struct r600_command_buffer  buffer;
  296     boolean             flatshade;
  297     boolean             two_side;
  298     unsigned            sprite_coord_enable;
  299     unsigned                        clip_plane_enable;
  300     unsigned            pa_sc_line_stipple;
  301     unsigned            pa_cl_clip_cntl;
  302     unsigned            pa_su_sc_mode_cntl;
  303     float               offset_units;
  304     float               offset_scale;
  305     bool                offset_enable;
  306     bool                offset_units_unscaled;
  307     bool                scissor_enable;
  308     bool                multisample_enable;
  309     bool                clip_halfz;
  310     bool                rasterizer_discard;
  311 };
  312 
  313 struct r600_poly_offset_state {
  314     struct r600_atom        atom;
  315     enum pipe_format        zs_format;
  316     float               offset_units;
  317     float               offset_scale;
  318     bool                offset_units_unscaled;
  319 };
  320 
  321 struct r600_blend_state {
  322     struct r600_command_buffer  buffer;
  323     struct r600_command_buffer  buffer_no_blend;
  324     unsigned            cb_target_mask;
  325     unsigned            cb_color_control;
  326     unsigned            cb_color_control_no_blend;
  327     bool                dual_src_blend;
  328     bool                alpha_to_one;
  329 };
  330 
  331 struct r600_dsa_state {
  332     struct r600_command_buffer  buffer;
  333     unsigned            alpha_ref;
  334     ubyte               valuemask[2];
  335     ubyte               writemask[2];
  336     unsigned            zwritemask;
  337     unsigned            sx_alpha_test_control;
  338 };
  339 
  340 struct r600_pipe_shader;
  341 
  342 struct r600_pipe_shader_selector {
  343     struct r600_pipe_shader *current;
  344 
  345     struct tgsi_token       *tokens;
  346         struct nir_shader       *nir;
  347     struct pipe_stream_output_info  so;
  348     struct tgsi_shader_info     info;
  349 
  350     unsigned    num_shaders;
  351 
  352     enum pipe_shader_type   type;
  353         enum pipe_shader_ir ir_type;
  354 
  355     /* geometry shader properties */
  356     enum pipe_prim_type gs_output_prim;
  357     unsigned        gs_max_out_vertices;
  358     unsigned        gs_num_invocations;
  359 
  360     /* TCS/VS */
  361     uint64_t        lds_patch_outputs_written_mask;
  362     uint64_t        lds_outputs_written_mask;
  363     unsigned    nr_ps_max_color_exports;
  364 };
  365 
  366 struct r600_pipe_sampler_state {
  367     uint32_t            tex_sampler_words[3];
  368     union pipe_color_union      border_color;
  369     bool                border_color_use;
  370     bool                seamless_cube_map;
  371 };
  372 
  373 /* needed for blitter save */
  374 #define NUM_TEX_UNITS 16
  375 
  376 struct r600_seamless_cube_map {
  377     struct r600_atom        atom;
  378     bool                enabled;
  379 };
  380 
  381 struct r600_samplerview_state {
  382     struct r600_atom        atom;
  383     struct r600_pipe_sampler_view   *views[NUM_TEX_UNITS];
  384     uint32_t            enabled_mask;
  385     uint32_t            dirty_mask;
  386     uint32_t            compressed_depthtex_mask; /* which textures are depth */
  387     uint32_t            compressed_colortex_mask;
  388     boolean             dirty_buffer_constants;
  389 };
  390 
  391 struct r600_sampler_states {
  392     struct r600_atom        atom;
  393     struct r600_pipe_sampler_state  *states[NUM_TEX_UNITS];
  394     uint32_t            enabled_mask;
  395     uint32_t            dirty_mask;
  396     uint32_t            has_bordercolor_mask; /* which states contain the border color */
  397 };
  398 
  399 struct r600_textures_info {
  400     struct r600_samplerview_state   views;
  401     struct r600_sampler_states  states;
  402     bool                is_array_sampler[NUM_TEX_UNITS];
  403 };
  404 
  405 struct r600_shader_driver_constants_info {
  406     /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
  407     uint32_t            *constants;
  408     uint32_t            alloc_size;
  409     bool                texture_const_dirty;
  410     bool                vs_ucp_dirty;
  411     bool                ps_sample_pos_dirty;
  412     bool                            cs_block_grid_size_dirty;
  413     bool                tcs_default_levels_dirty;
  414 };
  415 
  416 struct r600_constbuf_state
  417 {
  418     struct r600_atom        atom;
  419     struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
  420     uint32_t            enabled_mask;
  421     uint32_t            dirty_mask;
  422 };
  423 
  424 struct r600_vertexbuf_state
  425 {
  426     struct r600_atom        atom;
  427     struct pipe_vertex_buffer   vb[PIPE_MAX_ATTRIBS];
  428     uint32_t            enabled_mask; /* non-NULL buffers */
  429     uint32_t            dirty_mask;
  430 };
  431 
  432 /* CSO (constant state object, in other words, immutable state). */
  433 struct r600_cso_state
  434 {
  435     struct r600_atom atom;
  436     void *cso; /* e.g. r600_blend_state */
  437     struct r600_command_buffer *cb;
  438 };
  439 
  440 struct r600_fetch_shader {
  441     struct r600_resource        *buffer;
  442     unsigned            offset;
  443 };
  444 
  445 struct r600_shader_state {
  446     struct r600_atom        atom;
  447     struct r600_pipe_shader *shader;
  448 };
  449 
  450 struct r600_atomic_buffer_state {
  451     struct pipe_shader_buffer buffer[EG_MAX_ATOMIC_BUFFERS];
  452 };
  453 
  454 struct r600_image_view {
  455     struct pipe_image_view base;
  456     uint32_t cb_color_base;
  457     uint32_t cb_color_pitch;
  458     uint32_t cb_color_slice;
  459     uint32_t cb_color_view;
  460     uint32_t cb_color_info;
  461     uint32_t cb_color_attrib;
  462     uint32_t cb_color_dim;
  463     uint32_t cb_color_fmask;
  464     uint32_t cb_color_fmask_slice;
  465     uint32_t immed_resource_words[8];
  466     uint32_t resource_words[8];
  467     bool skip_mip_address_reloc;
  468     uint32_t buf_size;
  469 };
  470 
  471 struct r600_image_state {
  472     struct r600_atom atom;
  473     uint32_t                        enabled_mask;
  474     uint32_t                        dirty_mask;
  475     uint32_t            compressed_depthtex_mask;
  476     uint32_t            compressed_colortex_mask;
  477     boolean             dirty_buffer_constants;
  478     struct r600_image_view views[R600_MAX_IMAGES];
  479 };
  480 
  481 /* Used to spill shader temps */
  482 struct r600_scratch_buffer {
  483     struct r600_resource        *buffer;
  484     boolean                 dirty;
  485     unsigned                size;
  486     unsigned                item_size;
  487 };
  488 
  489 struct r600_context {
  490     struct r600_common_context  b;
  491     struct r600_screen      *screen;
  492     struct blitter_context      *blitter;
  493     struct u_suballocator       *allocator_fetch_shader;
  494 
  495     /* Hardware info. */
  496     boolean             has_vertex_cache;
  497     unsigned            default_gprs[EG_NUM_HW_STAGES];
  498     unsigned                        current_gprs[EG_NUM_HW_STAGES];
  499     unsigned            r6xx_num_clause_temp_gprs;
  500 
  501     /* Miscellaneous state objects. */
  502     void                *custom_dsa_flush;
  503     void                *custom_blend_resolve;
  504     void                *custom_blend_decompress;
  505     void                            *custom_blend_fastclear;
  506     /* With rasterizer discard, there doesn't have to be a pixel shader.
  507      * In that case, we bind this one: */
  508     void                *dummy_pixel_shader;
  509     /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
  510      * bug where valid CMASK and FMASK are required to be present to avoid
  511      * a hardlock in certain operations but aren't actually used
  512      * for anything useful. */
  513     struct r600_resource        *dummy_fmask;
  514     struct r600_resource        *dummy_cmask;
  515 
  516     /* State binding slots are here. */
  517     struct r600_atom        *atoms[R600_NUM_ATOMS];
  518     /* Dirty atom bitmask for fast tests */
  519     uint64_t            dirty_atoms;
  520     /* States for CS initialization. */
  521     struct r600_command_buffer  start_cs_cmd; /* invariant state mostly */
  522     /** Compute specific registers initializations.  The start_cs_cmd atom
  523      *  must be emitted before start_compute_cs_cmd. */
  524     struct r600_command_buffer      start_compute_cs_cmd;
  525     /* Register states. */
  526     struct r600_alphatest_state alphatest_state;
  527     struct r600_cso_state       blend_state;
  528     struct r600_blend_color     blend_color;
  529     struct r600_cb_misc_state   cb_misc_state;
  530     struct r600_clip_misc_state clip_misc_state;
  531     struct r600_clip_state      clip_state;
  532     struct r600_db_misc_state   db_misc_state;
  533     struct r600_db_state        db_state;
  534     struct r600_cso_state       dsa_state;
  535     struct r600_framebuffer     framebuffer;
  536     struct r600_poly_offset_state   poly_offset_state;
  537     struct r600_cso_state       rasterizer_state;
  538     struct r600_sample_mask     sample_mask;
  539     struct r600_seamless_cube_map   seamless_cube_map;
  540     struct r600_config_state    config_state;
  541     struct r600_stencil_ref_state   stencil_ref;
  542     struct r600_vgt_state       vgt_state;
  543     struct r600_atomic_buffer_state atomic_buffer_state;
  544     /* only have images on fragment shader */
  545     struct r600_image_state         fragment_images;
  546     struct r600_image_state         compute_images;
  547     struct r600_image_state         fragment_buffers;
  548     struct r600_image_state         compute_buffers;
  549     /* Shaders and shader resources. */
  550     struct r600_cso_state       vertex_fetch_shader;
  551     struct r600_shader_state        hw_shader_stages[EG_NUM_HW_STAGES];
  552     struct r600_cs_shader_state cs_shader_state;
  553     struct r600_shader_stages_state shader_stages;
  554     struct r600_gs_rings_state  gs_rings;
  555     struct r600_constbuf_state  constbuf_state[PIPE_SHADER_TYPES];
  556     struct r600_textures_info   samplers[PIPE_SHADER_TYPES];
  557 
  558     struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
  559 
  560     /** Vertex buffers for fetch shaders */
  561     struct r600_vertexbuf_state vertex_buffer_state;
  562     /** Vertex buffers for compute shaders */
  563     struct r600_vertexbuf_state cs_vertex_buffer_state;
  564 
  565     /* Additional context states. */
  566     unsigned            compute_cb_target_mask;
  567     struct r600_pipe_shader_selector *ps_shader;
  568     struct r600_pipe_shader_selector *vs_shader;
  569     struct r600_pipe_shader_selector *gs_shader;
  570 
  571     struct r600_pipe_shader_selector *tcs_shader;
  572     struct r600_pipe_shader_selector *tes_shader;
  573 
  574     struct r600_pipe_shader_selector *fixed_func_tcs_shader;
  575 
  576     struct r600_rasterizer_state    *rasterizer;
  577     bool                alpha_to_one;
  578     bool                force_blend_disable;
  579     bool                            gs_tri_strip_adj_fix;
  580     boolean             dual_src_blend;
  581     unsigned            zwritemask;
  582     unsigned            ps_iter_samples;
  583 
  584     /* The list of all texture buffer objects in this context.
  585      * This list is walked when a buffer is invalidated/reallocated and
  586      * the GPU addresses are updated. */
  587     struct list_head        texture_buffers;
  588 
  589     /* Last draw state (-1 = unset). */
  590     enum pipe_prim_type     last_primitive_type; /* Last primitive type used in draw_vbo. */
  591     enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
  592     enum pipe_prim_type     last_rast_prim;
  593     unsigned            last_start_instance;
  594 
  595     void                *sb_context;
  596     struct r600_isa     *isa;
  597     float sample_positions[4 * 16];
  598     float tess_state[8];
  599     uint32_t cs_block_grid_sizes[8]; /* 3 for grid + 1 pad, 3 for block  + 1 pad*/
  600     struct r600_pipe_shader_selector *last_ls;
  601     struct r600_pipe_shader_selector *last_tcs;
  602     unsigned last_num_tcs_input_cp;
  603     unsigned lds_alloc;
  604 
  605     struct r600_scratch_buffer scratch_buffers[MAX2(R600_NUM_HW_STAGES, EG_NUM_HW_STAGES)];
  606 
  607     /* Debug state. */
  608     bool            is_debug;
  609     struct radeon_saved_cs  last_gfx;
  610     struct r600_resource    *last_trace_buf;
  611     struct r600_resource    *trace_buf;
  612     unsigned        trace_id;
  613 
  614     bool cmd_buf_is_compute;
  615     struct pipe_resource *append_fence;
  616     uint32_t append_fence_id;
  617 };
  618 
  619 static inline void r600_emit_command_buffer(struct radeon_cmdbuf *cs,
  620                         struct r600_command_buffer *cb)
  621 {
  622     assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw);
  623     memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw);
  624     cs->current.cdw += cb->num_dw;
  625 }
  626 
  627 static inline void r600_set_atom_dirty(struct r600_context *rctx,
  628                        struct r600_atom *atom,
  629                        bool dirty)
  630 {
  631     uint64_t mask;
  632 
  633     assert(atom->id != 0);
  634     assert(atom->id < sizeof(mask) * 8);
  635     mask = 1ull << atom->id;
  636     if (dirty)
  637         rctx->dirty_atoms |= mask;
  638     else
  639         rctx->dirty_atoms &= ~mask;
  640 }
  641 
  642 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
  643                     struct r600_atom *atom)
  644 {
  645     r600_set_atom_dirty(rctx, atom, true);
  646 }
  647 
  648 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
  649 {
  650     atom->emit(&rctx->b, atom);
  651     r600_set_atom_dirty(rctx, atom, false);
  652 }
  653 
  654 static inline void r600_set_cso_state(struct r600_context *rctx,
  655                       struct r600_cso_state *state, void *cso)
  656 {
  657     state->cso = cso;
  658     r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
  659 }
  660 
  661 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
  662                           struct r600_cso_state *state, void *cso,
  663                           struct r600_command_buffer *cb)
  664 {
  665     state->cb = cb;
  666     state->atom.num_dw = cb ? cb->num_dw : 0;
  667     r600_set_cso_state(rctx, state, cso);
  668 }
  669 
  670 /* compute_memory_pool.c */
  671 struct compute_memory_pool;
  672 void compute_memory_pool_delete(struct compute_memory_pool* pool);
  673 struct compute_memory_pool* compute_memory_pool_new(
  674     struct r600_screen *rscreen);
  675 
  676 /* evergreen_state.c */
  677 struct pipe_sampler_view *
  678 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
  679                      struct pipe_resource *texture,
  680                      const struct pipe_sampler_view *state,
  681                      unsigned width0, unsigned height0,
  682                      unsigned force_level);
  683 void evergreen_init_common_regs(struct r600_context *ctx,
  684                 struct r600_command_buffer *cb,
  685                 enum chip_class ctx_chip_class,
  686                 enum radeon_family ctx_family,
  687                 int ctx_drm_minor);
  688 void cayman_init_common_regs(struct r600_command_buffer *cb,
  689                  enum chip_class ctx_chip_class,
  690                  enum radeon_family ctx_family,
  691                  int ctx_drm_minor);
  692 
  693 void evergreen_init_state_functions(struct r600_context *rctx);
  694 void evergreen_init_atom_start_cs(struct r600_context *rctx);
  695 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
  696 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
  697 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
  698 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
  699 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
  700 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
  701 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
  702 void *evergreen_create_resolve_blend(struct r600_context *rctx);
  703 void *evergreen_create_decompress_blend(struct r600_context *rctx);
  704 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
  705 bool evergreen_is_format_supported(struct pipe_screen *screen,
  706                    enum pipe_format format,
  707                    enum pipe_texture_target target,
  708                    unsigned sample_count,
  709                    unsigned storage_sample_count,
  710                    unsigned usage);
  711 void evergreen_init_color_surface(struct r600_context *rctx,
  712                   struct r600_surface *surf);
  713 void evergreen_init_color_surface_rat(struct r600_context *rctx,
  714                     struct r600_surface *surf);
  715 void evergreen_update_db_shader_control(struct r600_context * rctx);
  716 bool evergreen_adjust_gprs(struct r600_context *rctx);
  717 void evergreen_setup_scratch_buffers(struct r600_context *rctx);
  718 uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_misc_state *a,
  719                       unsigned nr_cbufs);
  720 /* r600_blit.c */
  721 void r600_init_blit_functions(struct r600_context *rctx);
  722 void r600_decompress_depth_textures(struct r600_context *rctx,
  723                     struct r600_samplerview_state *textures);
  724 void r600_decompress_depth_images(struct r600_context *rctx,
  725                   struct r600_image_state *images);
  726 void r600_decompress_color_textures(struct r600_context *rctx,
  727                     struct r600_samplerview_state *textures);
  728 void r600_decompress_color_images(struct r600_context *rctx,
  729                   struct r600_image_state *images);
  730 void r600_resource_copy_region(struct pipe_context *ctx,
  731                    struct pipe_resource *dst,
  732                    unsigned dst_level,
  733                    unsigned dstx, unsigned dsty, unsigned dstz,
  734                    struct pipe_resource *src,
  735                    unsigned src_level,
  736                    const struct pipe_box *src_box);
  737 
  738 /* r600_shader.c */
  739 int r600_pipe_shader_create(struct pipe_context *ctx,
  740                 struct r600_pipe_shader *shader,
  741                 union r600_shader_key key);
  742 
  743 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
  744 
  745 /* r600_state.c */
  746 struct pipe_sampler_view *
  747 r600_create_sampler_view_custom(struct pipe_context *ctx,
  748                 struct pipe_resource *texture,
  749                 const struct pipe_sampler_view *state,
  750                 unsigned width_first_level, unsigned height_first_level);
  751 void r600_init_state_functions(struct r600_context *rctx);
  752 void r600_init_atom_start_cs(struct r600_context *rctx);
  753 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
  754 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
  755 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
  756 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
  757 void *r600_create_db_flush_dsa(struct r600_context *rctx);
  758 void *r600_create_resolve_blend(struct r600_context *rctx);
  759 void *r700_create_resolve_blend(struct r600_context *rctx);
  760 void *r600_create_decompress_blend(struct r600_context *rctx);
  761 bool r600_adjust_gprs(struct r600_context *rctx);
  762 bool r600_is_format_supported(struct pipe_screen *screen,
  763                   enum pipe_format format,
  764                   enum pipe_texture_target target,
  765                   unsigned sample_count,
  766                   unsigned storage_sample_count,
  767                   unsigned usage);
  768 void r600_update_db_shader_control(struct r600_context * rctx);
  769 void r600_setup_scratch_buffers(struct r600_context *rctx);
  770 
  771 /* r600_hw_context.c */
  772 void r600_context_gfx_flush(void *context, unsigned flags,
  773                 struct pipe_fence_handle **fence);
  774 void r600_begin_new_cs(struct r600_context *ctx);
  775 void r600_flush_emit(struct r600_context *ctx);
  776 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in, unsigned num_atomics);
  777 void r600_emit_pfp_sync_me(struct r600_context *rctx);
  778 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
  779                  struct pipe_resource *dst, uint64_t dst_offset,
  780                  struct pipe_resource *src, uint64_t src_offset,
  781                  unsigned size);
  782 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
  783                    struct pipe_resource *dst, uint64_t offset,
  784                    unsigned size, uint32_t clear_value,
  785                    enum r600_coherency coher);
  786 void r600_dma_copy_buffer(struct r600_context *rctx,
  787               struct pipe_resource *dst,
  788               struct pipe_resource *src,
  789               uint64_t dst_offset,
  790               uint64_t src_offset,
  791               uint64_t size);
  792 
  793 /*
  794  * evergreen_hw_context.c
  795  */
  796 void evergreen_dma_copy_buffer(struct r600_context *rctx,
  797                    struct pipe_resource *dst,
  798                    struct pipe_resource *src,
  799                    uint64_t dst_offset,
  800                    uint64_t src_offset,
  801                    uint64_t size);
  802 void evergreen_setup_tess_constants(struct r600_context *rctx,
  803                     const struct pipe_draw_info *info,
  804                     unsigned *num_patches);
  805 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
  806                     const struct pipe_draw_info *info,
  807                     unsigned num_patches);
  808 void evergreen_set_ls_hs_config(struct r600_context *rctx,
  809                 struct radeon_cmdbuf *cs,
  810                 uint32_t ls_hs_config);
  811 void evergreen_set_lds_alloc(struct r600_context *rctx,
  812                  struct radeon_cmdbuf *cs,
  813                  uint32_t lds_alloc);
  814 
  815 /* r600_state_common.c */
  816 void r600_init_common_state_functions(struct r600_context *rctx);
  817 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
  818 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
  819 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
  820 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
  821 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
  822 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
  823 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
  824 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
  825 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
  826             void (*emit)(struct r600_context *ctx, struct r600_atom *state),
  827             unsigned num_dw);
  828 void r600_vertex_buffers_dirty(struct r600_context *rctx);
  829 void r600_sampler_views_dirty(struct r600_context *rctx,
  830                   struct r600_samplerview_state *state);
  831 void r600_sampler_states_dirty(struct r600_context *rctx,
  832                    struct r600_sampler_states *state);
  833 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
  834 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
  835 void r600_setup_scratch_area_for_shader(struct r600_context *rctx,
  836     struct r600_pipe_shader *shader, struct r600_scratch_buffer *scratch,
  837     unsigned ring_base_reg, unsigned item_size_reg, unsigned ring_size_reg);
  838 uint32_t r600_translate_stencil_op(int s_op);
  839 uint32_t r600_translate_fill(uint32_t func);
  840 unsigned r600_tex_wrap(unsigned wrap);
  841 unsigned r600_tex_mipfilter(unsigned filter);
  842 unsigned r600_tex_compare(unsigned compare);
  843 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
  844 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
  845                    const unsigned char *swizzle_view,
  846                    boolean vtx);
  847 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
  848                   const unsigned char *swizzle_view,
  849                   uint32_t *word4_p, uint32_t *yuv_format_p,
  850                   bool do_endian_swap);
  851 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
  852                   bool do_endian_swap);
  853 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap);
  854 
  855 /* r600_uvd.c */
  856 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
  857                            const struct pipe_video_codec *decoder);
  858 
  859 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
  860                            const struct pipe_video_buffer *tmpl);
  861 
  862 /*
  863  * Helpers for building command buffers
  864  */
  865 
  866 #define PKT3_SET_CONFIG_REG 0x68
  867 #define PKT3_SET_CONTEXT_REG    0x69
  868 #define PKT3_SET_CTL_CONST      0x6F
  869 #define PKT3_SET_LOOP_CONST                    0x6C
  870 
  871 #define R600_CONFIG_REG_OFFSET  0x08000
  872 #define R600_CONTEXT_REG_OFFSET 0x28000
  873 #define R600_CTL_CONST_OFFSET   0x3CFF0
  874 #define R600_LOOP_CONST_OFFSET                 0X0003E200
  875 #define EG_LOOP_CONST_OFFSET               0x0003A200
  876 
  877 #define PKT_TYPE_S(x)                   (((unsigned)(x) & 0x3) << 30)
  878 #define PKT_COUNT_S(x)                  (((unsigned)(x) & 0x3FFF) << 16)
  879 #define PKT3_IT_OPCODE_S(x)             (((unsigned)(x) & 0xFF) << 8)
  880 #define PKT3_PREDICATE(x)               (((x) >> 0) & 0x1)
  881 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
  882 
  883 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
  884 
  885 /*Evergreen Compute packet3*/
  886 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
  887 
  888 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
  889 {
  890     cb->buf[cb->num_dw++] = value;
  891 }
  892 
  893 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
  894 {
  895     assert(cb->num_dw+num <= cb->max_num_dw);
  896     memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
  897     cb->num_dw += num;
  898 }
  899 
  900 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
  901 {
  902     assert(reg < R600_CONTEXT_REG_OFFSET);
  903     assert(cb->num_dw+2+num <= cb->max_num_dw);
  904     cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
  905     cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
  906 }
  907 
  908 /**
  909  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
  910  * shaders.
  911  */
  912 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
  913 {
  914     assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
  915     assert(cb->num_dw+2+num <= cb->max_num_dw);
  916     cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
  917     cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
  918 }
  919 
  920 /**
  921  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
  922  * shaders.
  923  */
  924 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
  925 {
  926     assert(reg >= R600_CTL_CONST_OFFSET);
  927     assert(cb->num_dw+2+num <= cb->max_num_dw);
  928     cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
  929     cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
  930 }
  931 
  932 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
  933 {
  934     assert(reg >= R600_LOOP_CONST_OFFSET);
  935     assert(cb->num_dw+2+num <= cb->max_num_dw);
  936     cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
  937     cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
  938 }
  939 
  940 /**
  941  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
  942  * shaders.
  943  */
  944 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
  945 {
  946     assert(reg >= EG_LOOP_CONST_OFFSET);
  947     assert(cb->num_dw+2+num <= cb->max_num_dw);
  948     cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
  949     cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
  950 }
  951 
  952 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
  953 {
  954     r600_store_config_reg_seq(cb, reg, 1);
  955     r600_store_value(cb, value);
  956 }
  957 
  958 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
  959 {
  960     r600_store_context_reg_seq(cb, reg, 1);
  961     r600_store_value(cb, value);
  962 }
  963 
  964 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
  965 {
  966     r600_store_ctl_const_seq(cb, reg, 1);
  967     r600_store_value(cb, value);
  968 }
  969 
  970 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
  971 {
  972     r600_store_loop_const_seq(cb, reg, 1);
  973     r600_store_value(cb, value);
  974 }
  975 
  976 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
  977 {
  978     eg_store_loop_const_seq(cb, reg, 1);
  979     r600_store_value(cb, value);
  980 }
  981 
  982 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
  983 void r600_release_command_buffer(struct r600_command_buffer *cb);
  984 
  985 static inline void radeon_compute_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
  986 {
  987     radeon_set_context_reg_seq(cs, reg, num);
  988     /* Set the compute bit on the packet header */
  989     cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
  990 }
  991 
  992 static inline void radeon_set_ctl_const_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
  993 {
  994     assert(reg >= R600_CTL_CONST_OFFSET);
  995     assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
  996     radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0));
  997     radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2);
  998 }
  999 
 1000 static inline void radeon_compute_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
 1001 {
 1002     radeon_compute_set_context_reg_seq(cs, reg, 1);
 1003     radeon_emit(cs, value);
 1004 }
 1005 
 1006 static inline void radeon_set_context_reg_flag(struct radeon_cmdbuf *cs, unsigned reg, unsigned value, unsigned flag)
 1007 {
 1008     if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
 1009         radeon_compute_set_context_reg(cs, reg, value);
 1010     } else {
 1011         radeon_set_context_reg(cs, reg, value);
 1012     }
 1013 }
 1014 
 1015 static inline void radeon_set_ctl_const(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
 1016 {
 1017     radeon_set_ctl_const_seq(cs, reg, 1);
 1018     radeon_emit(cs, value);
 1019 }
 1020 
 1021 /*
 1022  * common helpers
 1023  */
 1024 
 1025 /* 12.4 fixed-point */
 1026 static inline unsigned r600_pack_float_12p4(float x)
 1027 {
 1028     return x <= 0    ? 0 :
 1029            x >= 4096 ? 0xffff : x * 16;
 1030 }
 1031 
 1032 static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
 1033 {
 1034     switch (coher) {
 1035     default:
 1036     case R600_COHERENCY_NONE:
 1037         return 0;
 1038     case R600_COHERENCY_SHADER:
 1039         return R600_CONTEXT_INV_CONST_CACHE |
 1040                R600_CONTEXT_INV_VERTEX_CACHE |
 1041                R600_CONTEXT_INV_TEX_CACHE |
 1042                R600_CONTEXT_STREAMOUT_FLUSH;
 1043     case R600_COHERENCY_CB_META:
 1044         return R600_CONTEXT_FLUSH_AND_INV_CB |
 1045                R600_CONTEXT_FLUSH_AND_INV_CB_META;
 1046     }
 1047 }
 1048 
 1049 #define     V_028A6C_OUTPRIM_TYPE_POINTLIST            0
 1050 #define     V_028A6C_OUTPRIM_TYPE_LINESTRIP            1
 1051 #define     V_028A6C_OUTPRIM_TYPE_TRISTRIP             2
 1052 
 1053 unsigned r600_conv_prim_to_gs_out(unsigned mode);
 1054 
 1055 void eg_trace_emit(struct r600_context *rctx);
 1056 void eg_dump_debug_state(struct pipe_context *ctx, FILE *f,
 1057              unsigned flags);
 1058 
 1059 struct r600_pipe_shader_selector *r600_create_shader_state_tokens(struct pipe_context *ctx,
 1060                                   const void *tokens,
 1061                                   enum pipe_shader_ir,
 1062                                   unsigned pipe_shader_type);
 1063 int r600_shader_select(struct pipe_context *ctx,
 1064                struct r600_pipe_shader_selector* sel,
 1065                bool *dirty);
 1066 
 1067 void r600_delete_shader_selector(struct pipe_context *ctx,
 1068                  struct r600_pipe_shader_selector *sel);
 1069 
 1070 struct r600_shader_atomic;
 1071 void evergreen_emit_atomic_buffer_setup_count(struct r600_context *rctx,
 1072                           struct r600_pipe_shader *cs_shader,
 1073                           struct r600_shader_atomic *combined_atomics,
 1074                           uint8_t *atomic_used_mask_p);
 1075 void evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
 1076                     bool is_compute,
 1077                     struct r600_shader_atomic *combined_atomics,
 1078                     uint8_t atomic_used_mask);
 1079 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
 1080                        bool is_compute,
 1081                        struct r600_shader_atomic *combined_atomics,
 1082                        uint8_t *atomic_used_mask_p);
 1083 void r600_update_compressed_resource_state(struct r600_context *rctx, bool compute_only);
 1084 
 1085 void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type);
 1086 void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_only);
 1087 #endif