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Member "mesa-20.1.8/src/gallium/drivers/r600/r600_pipe.c" (16 Sep 2020, 26259 Bytes) of package /linux/misc/mesa-20.1.8.tar.xz:


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    1 /*
    2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
    3  *
    4  * Permission is hereby granted, free of charge, to any person obtaining a
    5  * copy of this software and associated documentation files (the "Software"),
    6  * to deal in the Software without restriction, including without limitation
    7  * on the rights to use, copy, modify, merge, publish, distribute, sub
    8  * license, and/or sell copies of the Software, and to permit persons to whom
    9  * the Software is furnished to do so, subject to the following conditions:
   10  *
   11  * The above copyright notice and this permission notice (including the next
   12  * paragraph) shall be included in all copies or substantial portions of the
   13  * Software.
   14  *
   15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
   18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
   19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
   20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
   21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
   22  */
   23 #include "r600_pipe.h"
   24 #include "r600_public.h"
   25 #include "r600_isa.h"
   26 #include "evergreen_compute.h"
   27 #include "r600d.h"
   28 
   29 #include "sb/sb_public.h"
   30 
   31 #include <errno.h>
   32 #include "pipe/p_shader_tokens.h"
   33 #include "util/u_debug.h"
   34 #include "util/u_memory.h"
   35 #include "util/u_screen.h"
   36 #include "util/u_simple_shaders.h"
   37 #include "util/u_upload_mgr.h"
   38 #include "util/u_math.h"
   39 #include "vl/vl_decoder.h"
   40 #include "vl/vl_video_buffer.h"
   41 #include "radeon_video.h"
   42 #include "radeon_uvd.h"
   43 #include "util/os_time.h"
   44 
   45 static const struct debug_named_value r600_debug_options[] = {
   46     /* features */
   47     { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
   48 
   49     /* shader backend */
   50     { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
   51     { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
   52     { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
   53     { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
   54     { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
   55     { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
   56     { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
   57     { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
   58 
   59     DEBUG_NAMED_VALUE_END /* must be last */
   60 };
   61 
   62 /*
   63  * pipe_context
   64  */
   65 
   66 static void r600_destroy_context(struct pipe_context *context)
   67 {
   68     struct r600_context *rctx = (struct r600_context *)context;
   69     unsigned sh, i;
   70 
   71     r600_isa_destroy(rctx->isa);
   72 
   73     r600_sb_context_destroy(rctx->sb_context);
   74 
   75     for (sh = 0; sh < (rctx->b.chip_class < EVERGREEN ? R600_NUM_HW_STAGES : EG_NUM_HW_STAGES); sh++) {
   76         r600_resource_reference(&rctx->scratch_buffers[sh].buffer, NULL);
   77     }
   78     r600_resource_reference(&rctx->dummy_cmask, NULL);
   79     r600_resource_reference(&rctx->dummy_fmask, NULL);
   80 
   81     if (rctx->append_fence)
   82         pipe_resource_reference((struct pipe_resource**)&rctx->append_fence, NULL);
   83     for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
   84         rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, NULL);
   85         free(rctx->driver_consts[sh].constants);
   86     }
   87 
   88     if (rctx->fixed_func_tcs_shader)
   89         rctx->b.b.delete_tcs_state(&rctx->b.b, rctx->fixed_func_tcs_shader);
   90 
   91     if (rctx->dummy_pixel_shader) {
   92         rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
   93     }
   94     if (rctx->custom_dsa_flush) {
   95         rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
   96     }
   97     if (rctx->custom_blend_resolve) {
   98         rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
   99     }
  100     if (rctx->custom_blend_decompress) {
  101         rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
  102     }
  103     if (rctx->custom_blend_fastclear) {
  104         rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
  105     }
  106     util_unreference_framebuffer_state(&rctx->framebuffer.state);
  107 
  108     if (rctx->gs_rings.gsvs_ring.buffer)
  109         pipe_resource_reference(&rctx->gs_rings.gsvs_ring.buffer, NULL);
  110 
  111     if (rctx->gs_rings.esgs_ring.buffer)
  112         pipe_resource_reference(&rctx->gs_rings.esgs_ring.buffer, NULL);
  113 
  114     for (sh = 0; sh < PIPE_SHADER_TYPES; ++sh)
  115         for (i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; ++i)
  116             rctx->b.b.set_constant_buffer(context, sh, i, NULL);
  117 
  118     if (rctx->blitter) {
  119         util_blitter_destroy(rctx->blitter);
  120     }
  121     if (rctx->allocator_fetch_shader) {
  122         u_suballocator_destroy(rctx->allocator_fetch_shader);
  123     }
  124 
  125     r600_release_command_buffer(&rctx->start_cs_cmd);
  126 
  127     FREE(rctx->start_compute_cs_cmd.buf);
  128 
  129     r600_common_context_cleanup(&rctx->b);
  130 
  131     r600_resource_reference(&rctx->trace_buf, NULL);
  132     r600_resource_reference(&rctx->last_trace_buf, NULL);
  133     radeon_clear_saved_cs(&rctx->last_gfx);
  134 
  135     FREE(rctx);
  136 }
  137 
  138 static struct pipe_context *r600_create_context(struct pipe_screen *screen,
  139                                                 void *priv, unsigned flags)
  140 {
  141     struct r600_context *rctx = CALLOC_STRUCT(r600_context);
  142     struct r600_screen* rscreen = (struct r600_screen *)screen;
  143     struct radeon_winsys *ws = rscreen->b.ws;
  144 
  145     if (!rctx)
  146         return NULL;
  147 
  148     rctx->b.b.screen = screen;
  149     assert(!priv);
  150     rctx->b.b.priv = NULL; /* for threaded_context_unwrap_sync */
  151     rctx->b.b.destroy = r600_destroy_context;
  152     rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
  153 
  154     if (!r600_common_context_init(&rctx->b, &rscreen->b, flags))
  155         goto fail;
  156 
  157     rctx->screen = rscreen;
  158     list_inithead(&rctx->texture_buffers);
  159 
  160     r600_init_blit_functions(rctx);
  161 
  162     if (rscreen->b.info.has_hw_decode) {
  163         rctx->b.b.create_video_codec = r600_uvd_create_decoder;
  164         rctx->b.b.create_video_buffer = r600_video_buffer_create;
  165     } else {
  166         rctx->b.b.create_video_codec = vl_create_decoder;
  167         rctx->b.b.create_video_buffer = vl_video_buffer_create;
  168     }
  169 
  170     if (getenv("R600_TRACE"))
  171         rctx->is_debug = true;
  172     r600_init_common_state_functions(rctx);
  173 
  174     switch (rctx->b.chip_class) {
  175     case R600:
  176     case R700:
  177         r600_init_state_functions(rctx);
  178         r600_init_atom_start_cs(rctx);
  179         rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
  180         rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
  181                                       : r600_create_resolve_blend(rctx);
  182         rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
  183         rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
  184                        rctx->b.family == CHIP_RV620 ||
  185                        rctx->b.family == CHIP_RS780 ||
  186                        rctx->b.family == CHIP_RS880 ||
  187                        rctx->b.family == CHIP_RV710);
  188         break;
  189     case EVERGREEN:
  190     case CAYMAN:
  191         evergreen_init_state_functions(rctx);
  192         evergreen_init_atom_start_cs(rctx);
  193         evergreen_init_atom_start_compute_cs(rctx);
  194         rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
  195         rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
  196         rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
  197         rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
  198         rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
  199                        rctx->b.family == CHIP_PALM ||
  200                        rctx->b.family == CHIP_SUMO ||
  201                        rctx->b.family == CHIP_SUMO2 ||
  202                        rctx->b.family == CHIP_CAICOS ||
  203                        rctx->b.family == CHIP_CAYMAN ||
  204                        rctx->b.family == CHIP_ARUBA);
  205 
  206         rctx->append_fence = pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
  207                              PIPE_USAGE_DEFAULT, 32);
  208         break;
  209     default:
  210         R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
  211         goto fail;
  212     }
  213 
  214     rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
  215                        r600_context_gfx_flush, rctx, false);
  216     rctx->b.gfx.flush = r600_context_gfx_flush;
  217 
  218     rctx->allocator_fetch_shader =
  219         u_suballocator_create(&rctx->b.b, 64 * 1024,
  220                       0, PIPE_USAGE_DEFAULT, 0, FALSE);
  221     if (!rctx->allocator_fetch_shader)
  222         goto fail;
  223 
  224     rctx->isa = calloc(1, sizeof(struct r600_isa));
  225     if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
  226         goto fail;
  227 
  228     if (rscreen->b.debug_flags & DBG_FORCE_DMA)
  229         rctx->b.b.resource_copy_region = rctx->b.dma_copy;
  230 
  231     rctx->blitter = util_blitter_create(&rctx->b.b);
  232     if (rctx->blitter == NULL)
  233         goto fail;
  234     util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
  235     rctx->blitter->draw_rectangle = r600_draw_rectangle;
  236 
  237     r600_begin_new_cs(rctx);
  238 
  239     rctx->dummy_pixel_shader =
  240         util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
  241                              TGSI_SEMANTIC_GENERIC,
  242                              TGSI_INTERPOLATE_CONSTANT);
  243     rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
  244 
  245     return &rctx->b.b;
  246 
  247 fail:
  248     r600_destroy_context(&rctx->b.b);
  249     return NULL;
  250 }
  251 
  252 static bool is_nir_enabled(struct r600_common_screen *screen) {
  253    return (screen->debug_flags & DBG_NIR &&
  254        screen->family >= CHIP_CEDAR &&
  255        screen->family < CHIP_CAYMAN);
  256 }
  257 
  258 /*
  259  * pipe_screen
  260  */
  261 
  262 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
  263 {
  264     struct r600_screen *rscreen = (struct r600_screen *)pscreen;
  265     enum radeon_family family = rscreen->b.family;
  266 
  267     switch (param) {
  268     /* Supported features (boolean caps). */
  269     case PIPE_CAP_NPOT_TEXTURES:
  270     case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  271     case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  272     case PIPE_CAP_ANISOTROPIC_FILTER:
  273     case PIPE_CAP_POINT_SPRITE:
  274     case PIPE_CAP_OCCLUSION_QUERY:
  275     case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  276     case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  277     case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  278     case PIPE_CAP_TEXTURE_SWIZZLE:
  279     case PIPE_CAP_DEPTH_CLIP_DISABLE:
  280     case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  281     case PIPE_CAP_SHADER_STENCIL_EXPORT:
  282     case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  283     case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  284     case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  285     case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  286     case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  287     case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
  288     case PIPE_CAP_VERTEX_SHADER_SATURATE:
  289     case PIPE_CAP_SEAMLESS_CUBE_MAP:
  290     case PIPE_CAP_PRIMITIVE_RESTART:
  291     case PIPE_CAP_CONDITIONAL_RENDER:
  292     case PIPE_CAP_TEXTURE_BARRIER:
  293     case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  294     case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
  295     case PIPE_CAP_TGSI_INSTANCEID:
  296     case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
  297     case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
  298     case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
  299     case PIPE_CAP_START_INSTANCE:
  300     case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  301     case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  302     case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  303     case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  304     case PIPE_CAP_TEXTURE_MULTISAMPLE:
  305     case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  306     case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
  307     case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
  308     case PIPE_CAP_SAMPLE_SHADING:
  309     case PIPE_CAP_CLIP_HALFZ:
  310     case PIPE_CAP_POLYGON_OFFSET_CLAMP:
  311     case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
  312     case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
  313     case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
  314     case PIPE_CAP_TGSI_TXQS:
  315     case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
  316     case PIPE_CAP_INVALIDATE_BUFFER:
  317     case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
  318     case PIPE_CAP_QUERY_MEMORY_INFO:
  319     case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
  320     case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
  321     case PIPE_CAP_CLEAR_TEXTURE:
  322     case PIPE_CAP_TGSI_MUL_ZERO_WINS:
  323     case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
  324     case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
  325     case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
  326         return 1;
  327 
  328     case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
  329         /* Optimal number for good TexSubImage performance on Polaris10. */
  330         return 64 * 1024 * 1024;
  331 
  332     case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
  333         return rscreen->b.info.drm_minor >= 43;
  334 
  335     case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
  336         return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
  337 
  338     case PIPE_CAP_COMPUTE:
  339         return rscreen->b.chip_class > R700;
  340 
  341     case PIPE_CAP_TGSI_TEXCOORD:
  342         return is_nir_enabled(&rscreen->b);
  343 
  344     case PIPE_CAP_FAKE_SW_MSAA:
  345         return 0;
  346 
  347     case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
  348         return MIN2(rscreen->b.info.max_alloc_size, INT_MAX);
  349 
  350         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
  351                 return R600_MAP_BUFFER_ALIGNMENT;
  352 
  353     case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  354         return 256;
  355 
  356     case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
  357         return 1;
  358 
  359     case PIPE_CAP_GLSL_FEATURE_LEVEL:
  360         if (family >= CHIP_CEDAR)
  361            return 430;
  362         /* pre-evergreen geom shaders need newer kernel */
  363         if (rscreen->b.info.drm_minor >= 37)
  364            return 330;
  365         return 140;
  366 
  367     case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
  368         return 140;
  369 
  370     /* Supported except the original R600. */
  371     case PIPE_CAP_INDEP_BLEND_ENABLE:
  372     case PIPE_CAP_INDEP_BLEND_FUNC:
  373         /* R600 doesn't support per-MRT blends */
  374         return family == CHIP_R600 ? 0 : 1;
  375 
  376     /* Supported on Evergreen. */
  377     case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  378     case PIPE_CAP_CUBE_MAP_ARRAY:
  379     case PIPE_CAP_TEXTURE_GATHER_SM5:
  380     case PIPE_CAP_TEXTURE_QUERY_LOD:
  381     case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
  382     case PIPE_CAP_SAMPLER_VIEW_TARGET:
  383     case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
  384     case PIPE_CAP_TGSI_CLOCK:
  385     case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
  386     case PIPE_CAP_QUERY_BUFFER_OBJECT:
  387         return family >= CHIP_CEDAR ? 1 : 0;
  388     case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
  389         return family >= CHIP_CEDAR ? 4 : 0;
  390     case PIPE_CAP_DRAW_INDIRECT:
  391         /* kernel command checker support is also required */
  392         return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
  393 
  394     case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
  395         return family >= CHIP_CEDAR ? 0 : 1;
  396 
  397     case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
  398         return 8;
  399 
  400     case PIPE_CAP_MAX_GS_INVOCATIONS:
  401         return 32;
  402 
  403     /* shader buffer objects */
  404     case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
  405         return 1 << 27;
  406     case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
  407         return 8;
  408 
  409     case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
  410         return 0;
  411 
  412     case PIPE_CAP_DOUBLES:
  413         if (rscreen->b.family == CHIP_ARUBA ||
  414             rscreen->b.family == CHIP_CAYMAN ||
  415             rscreen->b.family == CHIP_CYPRESS ||
  416             rscreen->b.family == CHIP_HEMLOCK)
  417             return 1;
  418         return 0;
  419     case PIPE_CAP_CULL_DISTANCE:
  420         return 1;
  421 
  422     case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
  423         if (family >= CHIP_CEDAR)
  424             return 256;
  425         return 0;
  426 
  427     case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
  428         if (family >= CHIP_CEDAR)
  429             return 30;
  430         else
  431             return 0;
  432     /* Stream output. */
  433     case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
  434         return rscreen->b.has_streamout ? 4 : 0;
  435     case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
  436     case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
  437         return rscreen->b.has_streamout ? 1 : 0;
  438     case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
  439     case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
  440         return 32*4;
  441 
  442     /* Geometry shader output. */
  443     case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
  444         return 1024;
  445     case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
  446         return 16384;
  447     case PIPE_CAP_MAX_VERTEX_STREAMS:
  448         return family >= CHIP_CEDAR ? 4 : 1;
  449 
  450     case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
  451         /* Should be 2047, but 2048 is a requirement for GL 4.4 */
  452         return 2048;
  453 
  454     /* Texturing. */
  455     case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
  456         if (family >= CHIP_CEDAR)
  457             return 16384;
  458         else
  459             return 8192;
  460     case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  461         if (family >= CHIP_CEDAR)
  462             return 15;
  463         else
  464             return 14;
  465     case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  466         /* textures support 8192, but layered rendering supports 2048 */
  467         return 12;
  468     case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  469         /* textures support 8192, but layered rendering supports 2048 */
  470         return 2048;
  471 
  472     /* Render targets. */
  473     case PIPE_CAP_MAX_RENDER_TARGETS:
  474         /* XXX some r6xx are buggy and can only do 4 */
  475         return 8;
  476 
  477     case PIPE_CAP_MAX_VIEWPORTS:
  478         return R600_MAX_VIEWPORTS;
  479     case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
  480     case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
  481         return 8;
  482 
  483     /* Timer queries, present when the clock frequency is non zero. */
  484     case PIPE_CAP_QUERY_TIME_ELAPSED:
  485         return rscreen->b.info.clock_crystal_freq != 0;
  486     case PIPE_CAP_QUERY_TIMESTAMP:
  487         return rscreen->b.info.drm_minor >= 20 &&
  488                rscreen->b.info.clock_crystal_freq != 0;
  489 
  490     case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  491     case PIPE_CAP_MIN_TEXEL_OFFSET:
  492         return -8;
  493 
  494     case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
  495     case PIPE_CAP_MAX_TEXEL_OFFSET:
  496         return 7;
  497 
  498     case PIPE_CAP_MAX_VARYINGS:
  499         return 32;
  500 
  501     case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
  502         return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
  503     case PIPE_CAP_ENDIANNESS:
  504         return PIPE_ENDIAN_LITTLE;
  505 
  506     case PIPE_CAP_VENDOR_ID:
  507         return ATI_VENDOR_ID;
  508     case PIPE_CAP_DEVICE_ID:
  509         return rscreen->b.info.pci_id;
  510     case PIPE_CAP_ACCELERATED:
  511         return 1;
  512     case PIPE_CAP_VIDEO_MEMORY:
  513         return rscreen->b.info.vram_size >> 20;
  514     case PIPE_CAP_UMA:
  515         return 0;
  516     case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
  517         return rscreen->b.chip_class >= R700;
  518     case PIPE_CAP_PCI_GROUP:
  519         return rscreen->b.info.pci_domain;
  520     case PIPE_CAP_PCI_BUS:
  521         return rscreen->b.info.pci_bus;
  522     case PIPE_CAP_PCI_DEVICE:
  523         return rscreen->b.info.pci_dev;
  524     case PIPE_CAP_PCI_FUNCTION:
  525         return rscreen->b.info.pci_func;
  526 
  527     case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
  528         if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
  529             return 8;
  530         return 0;
  531     case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
  532         if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
  533             return EG_MAX_ATOMIC_BUFFERS;
  534         return 0;
  535 
  536     default:
  537         return u_pipe_screen_get_param_defaults(pscreen, param);
  538     }
  539 }
  540 
  541 static int r600_get_shader_param(struct pipe_screen* pscreen,
  542                  enum pipe_shader_type shader,
  543                  enum pipe_shader_cap param)
  544 {
  545     struct r600_screen *rscreen = (struct r600_screen *)pscreen;
  546 
  547     switch(shader)
  548     {
  549     case PIPE_SHADER_FRAGMENT:
  550     case PIPE_SHADER_VERTEX:
  551         break;
  552     case PIPE_SHADER_GEOMETRY:
  553         if (rscreen->b.family >= CHIP_CEDAR)
  554             break;
  555         /* pre-evergreen geom shaders need newer kernel */
  556         if (rscreen->b.info.drm_minor >= 37)
  557             break;
  558         return 0;
  559       /* With NIR we currently disable TES, TCS and COMP shaders */
  560     case PIPE_SHADER_TESS_CTRL:
  561     case PIPE_SHADER_TESS_EVAL:
  562         if (rscreen->b.family >= CHIP_CEDAR)
  563             break;
  564     case PIPE_SHADER_COMPUTE:
  565         if (!is_nir_enabled(&rscreen->b))
  566             break;
  567     default:
  568         return 0;
  569     }
  570 
  571     switch (param) {
  572     case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
  573     case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
  574     case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
  575     case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
  576         return 16384;
  577     case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
  578         return 32;
  579     case PIPE_SHADER_CAP_MAX_INPUTS:
  580         return shader == PIPE_SHADER_VERTEX ? 16 : 32;
  581     case PIPE_SHADER_CAP_MAX_OUTPUTS:
  582         return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
  583     case PIPE_SHADER_CAP_MAX_TEMPS:
  584         return 256; /* Max native temporaries. */
  585     case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
  586         if (shader == PIPE_SHADER_COMPUTE) {
  587             uint64_t max_const_buffer_size;
  588             enum pipe_shader_ir ir_type = is_nir_enabled(&rscreen->b) ?
  589                 PIPE_SHADER_IR_NIR: PIPE_SHADER_IR_TGSI;
  590             pscreen->get_compute_param(pscreen, ir_type,
  591                            PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
  592                            &max_const_buffer_size);
  593             return MIN2(max_const_buffer_size, INT_MAX);
  594 
  595         } else {
  596             return R600_MAX_CONST_BUFFER_SIZE;
  597         }
  598     case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
  599         return R600_MAX_USER_CONST_BUFFERS;
  600     case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
  601         return 1;
  602     case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
  603         return 1;
  604     case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
  605     case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
  606     case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
  607     case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
  608         return 1;
  609     case PIPE_SHADER_CAP_SUBROUTINES:
  610     case PIPE_SHADER_CAP_INT64_ATOMICS:
  611     case PIPE_SHADER_CAP_FP16:
  612         return 0;
  613     case PIPE_SHADER_CAP_INTEGERS:
  614     case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
  615         return 1;
  616     case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
  617     case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
  618         return 16;
  619     case PIPE_SHADER_CAP_PREFERRED_IR:
  620         if (is_nir_enabled(&rscreen->b))
  621             return PIPE_SHADER_IR_NIR;
  622         return PIPE_SHADER_IR_TGSI;
  623     case PIPE_SHADER_CAP_SUPPORTED_IRS: {
  624         int ir = 0;
  625         if (shader == PIPE_SHADER_COMPUTE)
  626             ir = 1 << PIPE_SHADER_IR_NATIVE;
  627         if (rscreen->b.family >= CHIP_CEDAR) {
  628             ir |= 1 << PIPE_SHADER_IR_TGSI;
  629             if (is_nir_enabled(&rscreen->b))
  630                 ir |= 1 << PIPE_SHADER_IR_NIR;
  631         }
  632         return ir;
  633     }
  634     case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
  635         if (rscreen->b.family == CHIP_ARUBA ||
  636             rscreen->b.family == CHIP_CAYMAN ||
  637             rscreen->b.family == CHIP_CYPRESS ||
  638             rscreen->b.family == CHIP_HEMLOCK)
  639             return 1;
  640         return 0;
  641     case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
  642     case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
  643     case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
  644     case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
  645     case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
  646         return 0;
  647     case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
  648     case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
  649         if (rscreen->b.family >= CHIP_CEDAR &&
  650             (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE))
  651             return 8;
  652         return 0;
  653     case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
  654         if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
  655             return 8;
  656         return 0;
  657     case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
  658         /* having to allocate the atomics out amongst shaders stages is messy,
  659            so give compute 8 buffers and all the others one */
  660         if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics) {
  661             return EG_MAX_ATOMIC_BUFFERS;
  662         }
  663         return 0;
  664     case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
  665         /* due to a bug in the shader compiler, some loops hang
  666          * if they are not unrolled, see:
  667          *    https://bugs.freedesktop.org/show_bug.cgi?id=86720
  668          */
  669         return 255;
  670     }
  671     return 0;
  672 }
  673 
  674 static void r600_destroy_screen(struct pipe_screen* pscreen)
  675 {
  676     struct r600_screen *rscreen = (struct r600_screen *)pscreen;
  677 
  678     if (!rscreen)
  679         return;
  680 
  681     if (!rscreen->b.ws->unref(rscreen->b.ws))
  682         return;
  683 
  684     if (rscreen->global_pool) {
  685         compute_memory_pool_delete(rscreen->global_pool);
  686     }
  687 
  688     r600_destroy_common_screen(&rscreen->b);
  689 }
  690 
  691 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
  692                           const struct pipe_resource *templ)
  693 {
  694     if (templ->target == PIPE_BUFFER &&
  695         (templ->bind & PIPE_BIND_GLOBAL))
  696         return r600_compute_global_buffer_create(screen, templ);
  697 
  698     return r600_resource_create_common(screen, templ);
  699 }
  700 
  701 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws,
  702                        const struct pipe_screen_config *config)
  703 {
  704     struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
  705 
  706     if (!rscreen) {
  707         return NULL;
  708     }
  709 
  710     /* Set functions first. */
  711     rscreen->b.b.context_create = r600_create_context;
  712     rscreen->b.b.destroy = r600_destroy_screen;
  713     rscreen->b.b.get_param = r600_get_param;
  714     rscreen->b.b.get_shader_param = r600_get_shader_param;
  715     rscreen->b.b.resource_create = r600_resource_create;
  716 
  717     if (!r600_common_screen_init(&rscreen->b, ws)) {
  718         FREE(rscreen);
  719         return NULL;
  720     }
  721 
  722     if (rscreen->b.info.chip_class >= EVERGREEN) {
  723         rscreen->b.b.is_format_supported = evergreen_is_format_supported;
  724     } else {
  725         rscreen->b.b.is_format_supported = r600_is_format_supported;
  726     }
  727 
  728     rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
  729     if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
  730         rscreen->b.debug_flags |= DBG_COMPUTE;
  731     if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
  732         rscreen->b.debug_flags |= DBG_ALL_SHADERS | DBG_FS;
  733     if (!debug_get_bool_option("R600_HYPERZ", TRUE))
  734         rscreen->b.debug_flags |= DBG_NO_HYPERZ;
  735 
  736     if (rscreen->b.family == CHIP_UNKNOWN) {
  737         fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
  738         FREE(rscreen);
  739         return NULL;
  740     }
  741 
  742     /* Figure out streamout kernel support. */
  743     switch (rscreen->b.chip_class) {
  744     case R600:
  745         if (rscreen->b.family < CHIP_RS780) {
  746             rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
  747         } else {
  748             rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
  749         }
  750         break;
  751     case R700:
  752         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
  753         break;
  754     case EVERGREEN:
  755     case CAYMAN:
  756         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
  757         break;
  758     default:
  759         rscreen->b.has_streamout = FALSE;
  760         break;
  761     }
  762 
  763     /* MSAA support. */
  764     switch (rscreen->b.chip_class) {
  765     case R600:
  766     case R700:
  767         rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
  768         rscreen->has_compressed_msaa_texturing = false;
  769         break;
  770     case EVERGREEN:
  771         rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
  772         rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
  773         break;
  774     case CAYMAN:
  775         rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
  776         rscreen->has_compressed_msaa_texturing = true;
  777         break;
  778     default:
  779         rscreen->has_msaa = FALSE;
  780         rscreen->has_compressed_msaa_texturing = false;
  781     }
  782 
  783     rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
  784                   !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
  785 
  786     rscreen->b.barrier_flags.cp_to_L2 =
  787         R600_CONTEXT_INV_VERTEX_CACHE |
  788         R600_CONTEXT_INV_TEX_CACHE |
  789         R600_CONTEXT_INV_CONST_CACHE;
  790     rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_CS_PARTIAL_FLUSH | R600_CONTEXT_FLUSH_AND_INV;
  791 
  792     rscreen->global_pool = compute_memory_pool_new(rscreen);
  793 
  794     /* Create the auxiliary context. This must be done last. */
  795     rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
  796 
  797     rscreen->has_atomics = rscreen->b.info.drm_minor >= 44;
  798 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
  799     struct pipe_resource templ = {};
  800 
  801     templ.width0 = 4;
  802     templ.height0 = 2048;
  803     templ.depth0 = 1;
  804     templ.array_size = 1;
  805     templ.target = PIPE_TEXTURE_2D;
  806     templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
  807     templ.usage = PIPE_USAGE_DEFAULT;
  808 
  809     struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
  810     unsigned char *map = ws->buffer_map(res->buf, NULL, PIPE_TRANSFER_WRITE);
  811 
  812     memset(map, 0, 256);
  813 
  814     r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
  815     r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
  816     r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
  817     r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
  818     r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
  819 
  820     ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
  821 
  822     int i;
  823     for (i = 0; i < 256; i++) {
  824         printf("%02X", map[i]);
  825         if (i % 16 == 15)
  826             printf("\n");
  827     }
  828 #endif
  829 
  830     if (rscreen->b.debug_flags & DBG_TEST_DMA)
  831         r600_test_dma(&rscreen->b);
  832 
  833     r600_query_fix_enabled_rb_mask(&rscreen->b);
  834     return &rscreen->b.b;
  835 }