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Member "mesa-20.1.8/src/gallium/drivers/r600/r600_isa.c" (16 Sep 2020, 48023 Bytes) of package /linux/misc/mesa-20.1.8.tar.xz:


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    1 /*
    2  * Copyright 2012 Vadim Girlin <vadimgirlin@gmail.com>
    3  *
    4  * Permission is hereby granted, free of charge, to any person obtaining a
    5  * copy of this software and associated documentation files (the "Software"),
    6  * to deal in the Software without restriction, including without limitation
    7  * on the rights to use, copy, modify, merge, publish, distribute, sub
    8  * license, and/or sell copies of the Software, and to permit persons to whom
    9  * the Software is furnished to do so, subject to the following conditions:
   10  *
   11  * The above copyright notice and this permission notice (including the next
   12  * paragraph) shall be included in all copies or substantial portions of the
   13  * Software.
   14  *
   15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
   18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
   19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
   20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
   21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
   22  *
   23  * Authors:
   24  *      Vadim Girlin
   25  */
   26 
   27 #include "r600_pipe.h"
   28 #include "r600_isa.h"
   29 
   30 const struct alu_op_info r600_alu_op_table[] = {
   31         {"ADD",                       2, { 0x00, 0x00 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC },
   32         {"MUL",                       2, { 0x01, 0x01 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC },
   33         {"MUL_IEEE",                  2, { 0x02, 0x02 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_IEEE },
   34         {"MAX",                       2, { 0x03, 0x03 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC },
   35         {"MIN",                       2, { 0x04, 0x04 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC },
   36         {"MAX_DX10",                  2, { 0x05, 0x05 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_DX10 },
   37         {"MIN_DX10",                  2, { 0x06, 0x06 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_DX10 },
   38         {"SETE",                      2, { 0x08, 0x08 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_E },
   39         {"SETGT",                     2, { 0x09, 0x09 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_GT },
   40         {"SETGE",                     2, { 0x0A, 0x0A },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_GE },
   41         {"SETNE",                     2, { 0x0B, 0x0B },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_NE },
   42         {"SETE_DX10",                 2, { 0x0C, 0x0C },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_E | AF_DX10 | AF_INT_DST },
   43         {"SETGT_DX10",                2, { 0x0D, 0x0D },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_GT | AF_DX10 | AF_INT_DST },
   44         {"SETGE_DX10",                2, { 0x0E, 0x0E },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_GE | AF_DX10 | AF_INT_DST },
   45         {"SETNE_DX10",                2, { 0x0F, 0x0F },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_NE | AF_DX10 | AF_INT_DST },
   46         {"FRACT",                     1, { 0x10, 0x10 },{  AF_VS, AF_VS, AF_VS, AF_VS},  0 },
   47         {"TRUNC",                     1, { 0x11, 0x11 },{  AF_VS, AF_VS, AF_VS, AF_VS},  0 },
   48         {"CEIL",                      1, { 0x12, 0x12 },{  AF_VS, AF_VS, AF_VS, AF_VS},  0 },
   49         {"RNDNE",                     1, { 0x13, 0x13 },{  AF_VS, AF_VS, AF_VS, AF_VS},  0 },
   50         {"FLOOR",                     1, { 0x14, 0x14 },{  AF_VS, AF_VS, AF_VS, AF_VS},  0 },
   51         {"ASHR_INT",                  2, { 0x70, 0x15 },{   AF_S, AF_VS, AF_VS, AF_VS},  AF_INT_DST },
   52         {"LSHR_INT",                  2, { 0x71, 0x16 },{   AF_S, AF_VS, AF_VS, AF_VS},  AF_INT_DST },
   53         {"LSHL_INT",                  2, { 0x72, 0x17 },{   AF_S, AF_VS, AF_VS, AF_VS},  AF_INT_DST },
   54         {"MOV",                       1, { 0x19, 0x19 },{  AF_VS, AF_VS, AF_VS, AF_VS},  0 },
   55         {"ALU_NOP",                   0, { 0x1A, 0x1A },{  AF_VS, AF_VS, AF_VS, AF_VS},  0 },
   56         {"PRED_SETGT_UINT",           2, { 0x1E, 0x1E },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_GT | AF_UINT_CMP },
   57         {"PRED_SETGE_UINT",           2, { 0x1F, 0x1F },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_GE | AF_UINT_CMP },
   58         {"PRED_SETE",                 2, { 0x20, 0x20 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_E },
   59         {"PRED_SETGT",                2, { 0x21, 0x21 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_GT },
   60         {"PRED_SETGE",                2, { 0x22, 0x22 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_GE },
   61         {"PRED_SETNE",                2, { 0x23, 0x23 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_NE },
   62         {"PRED_SET_INV",              1, { 0x24, 0x24 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED },
   63         {"PRED_SET_POP",              2, { 0x25, 0x25 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED },
   64         {"PRED_SET_CLR",              0, { 0x26, 0x26 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED },
   65         {"PRED_SET_RESTORE",          1, { 0x27, 0x27 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED },
   66         {"PRED_SETE_PUSH",            2, { 0x28, 0x28 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_E },
   67         {"PRED_SETGT_PUSH",           2, { 0x29, 0x29 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_GT },
   68         {"PRED_SETGE_PUSH",           2, { 0x2A, 0x2A },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_GE },
   69         {"PRED_SETNE_PUSH",           2, { 0x2B, 0x2B },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_NE },
   70         {"KILLE",                     2, { 0x2C, 0x2C },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_E },
   71         {"KILLGT",                    2, { 0x2D, 0x2D },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_GT },
   72         {"KILLGE",                    2, { 0x2E, 0x2E },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_GE },
   73         {"KILLNE",                    2, { 0x2F, 0x2F },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_NE },
   74         {"AND_INT",                   2, { 0x30, 0x30 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_INT_DST },
   75         {"OR_INT",                    2, { 0x31, 0x31 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_INT_DST },
   76         {"XOR_INT",                   2, { 0x32, 0x32 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_INT_DST },
   77         {"NOT_INT",                   1, { 0x33, 0x33 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_INT_DST },
   78         {"ADD_INT",                   2, { 0x34, 0x34 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_INT_DST },
   79         {"SUB_INT",                   2, { 0x35, 0x35 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_INT_DST },
   80         {"MAX_INT",                   2, { 0x36, 0x36 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_INT_DST },
   81         {"MIN_INT",                   2, { 0x37, 0x37 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_INT_DST },
   82         {"MAX_UINT",                  2, { 0x38, 0x38 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_UINT_DST },
   83         {"MIN_UINT",                  2, { 0x39, 0x39 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_UINT_DST },
   84         {"SETE_INT",                  2, { 0x3A, 0x3A },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_E | AF_INT_DST | AF_INT_CMP },
   85         {"SETGT_INT",                 2, { 0x3B, 0x3B },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_GT | AF_INT_DST | AF_INT_CMP },
   86         {"SETGE_INT",                 2, { 0x3C, 0x3C },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_GE | AF_INT_DST | AF_INT_CMP },
   87         {"SETNE_INT",                 2, { 0x3D, 0x3D },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_NE | AF_INT_DST | AF_INT_CMP },
   88         {"SETGT_UINT",                2, { 0x3E, 0x3E },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_GT | AF_UINT_DST | AF_UINT_CMP },
   89         {"SETGE_UINT",                2, { 0x3F, 0x3F },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_SET | AF_CC_GE | AF_UINT_DST | AF_UINT_CMP },
   90         {"KILLGT_UINT",               2, { 0x40, 0x40 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_GT | AF_UINT_CMP },
   91         {"KILLGE_UINT",               2, { 0x41, 0x41 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_GE | AF_UINT_CMP },
   92         {"PRED_SETE_INT",             2, { 0x42, 0x42 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_E | AF_INT_CMP },
   93         {"PRED_SETGT_INT",            2, { 0x43, 0x43 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_GT | AF_INT_CMP },
   94         {"PRED_SETGE_INT",            2, { 0x44, 0x44 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_GE | AF_INT_CMP },
   95         {"PRED_SETNE_INT",            2, { 0x45, 0x45 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED | AF_CC_NE | AF_INT_CMP },
   96         {"KILLE_INT",                 2, { 0x46, 0x46 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_E | AF_INT_CMP },
   97         {"KILLGT_INT",                2, { 0x47, 0x47 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_GT | AF_INT_CMP },
   98         {"KILLGE_INT",                2, { 0x48, 0x48 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_GE | AF_INT_CMP },
   99         {"KILLNE_INT",                2, { 0x49, 0x49 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_KILL | AF_CC_NE | AF_INT_CMP },
  100         {"PRED_SETE_PUSH_INT",        2, { 0x4A, 0x4A },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_E | AF_INT_CMP },
  101         {"PRED_SETGT_PUSH_INT",       2, { 0x4B, 0x4B },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_GT | AF_INT_CMP },
  102         {"PRED_SETGE_PUSH_INT",       2, { 0x4C, 0x4C },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_GE | AF_INT_CMP },
  103         {"PRED_SETNE_PUSH_INT",       2, { 0x4D, 0x4D },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_NE | AF_INT_CMP },
  104         {"PRED_SETLT_PUSH_INT",       2, { 0x4E, 0x4E },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_LT | AF_INT_CMP },
  105         {"PRED_SETLE_PUSH_INT",       2, { 0x4F, 0x4F },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_PRED_PUSH | AF_CC_LE | AF_INT_CMP },
  106         {"FLT_TO_INT",                1, { 0x6B, 0x50 },{   AF_S,  AF_S,  AF_V,  AF_V},  AF_INT_DST | AF_CVT },
  107         {"BFREV_INT",                 1, {   -1, 0x51 },{      0,     0, AF_VS, AF_VS},  AF_INT_DST },
  108         {"ADDC_UINT",                 2, {   -1, 0x52 },{      0,     0, AF_VS, AF_VS},  AF_UINT_DST },
  109         {"SUBB_UINT",                 2, {   -1, 0x53 },{      0,     0, AF_VS, AF_VS},  AF_UINT_DST },
  110         {"GROUP_BARRIER",             0, {   -1, 0x54 },{      0,     0, AF_VS, AF_VS},  0 },
  111         {"GROUP_SEQ_BEGIN",           0, {   -1, 0x55 },{      0,     0, AF_VS,     0},  0 },
  112         {"GROUP_SEQ_END",             0, {   -1, 0x56 },{      0,     0, AF_VS,     0},  0 },
  113         {"SET_MODE",                  2, {   -1, 0x57 },{      0,     0, AF_VS, AF_VS},  0 },
  114         {"SET_CF_IDX0",               0, {   -1, 0x58 },{      0,     0, AF_VS,     0},  0 },
  115         {"SET_CF_IDX1",               0, {   -1, 0x59 },{      0,     0, AF_VS,     0},  0 },
  116         {"SET_LDS_SIZE",              2, {   -1, 0x5A },{      0,     0, AF_VS, AF_VS},  0 },
  117         {"MUL_INT24",                 2, {   -1, 0x5B },{      0,     0,     0,  AF_V},  AF_INT_DST | AF_24 },
  118         {"MULHI_INT24",               2, {   -1, 0x5C },{      0,     0,     0,  AF_V},  AF_INT_DST | AF_24 },
  119         {"FLT_TO_INT_TRUNC",          1, {   -1, 0x5D },{      0,     0,     0,  AF_V},  AF_INT_DST | AF_CVT},
  120         {"EXP_IEEE",                  1, { 0x61, 0x81 },{   AF_S,  AF_S,  AF_S,  AF_S},  AF_IEEE },
  121         {"LOG_CLAMPED",               1, { 0x62, 0x82 },{   AF_S,  AF_S,  AF_S,  AF_S},  0 },
  122         {"LOG_IEEE",                  1, { 0x63, 0x83 },{   AF_S,  AF_S,  AF_S,  AF_S},  AF_IEEE },
  123         {"RECIP_CLAMPED",             1, { 0x64, 0x84 },{   AF_S,  AF_S,  AF_S,  AF_S},  0 },
  124         {"RECIP_FF",                  1, { 0x65, 0x85 },{   AF_S,  AF_S,  AF_S,  AF_S},  0 },
  125         {"RECIP_IEEE",                1, { 0x66, 0x86 },{   AF_S,  AF_S,  AF_S,  AF_S},  AF_IEEE },
  126         {"RECIPSQRT_CLAMPED",         1, { 0x67, 0x87 },{   AF_S,  AF_S,  AF_S,  AF_S},  0 },
  127         {"RECIPSQRT_FF",              1, { 0x68, 0x88 },{   AF_S,  AF_S,  AF_S,  AF_S},  0 },
  128         {"RECIPSQRT_IEEE",            1, { 0x69, 0x89 },{   AF_S,  AF_S,  AF_S,  AF_S},  AF_IEEE },
  129         {"SQRT_IEEE",                 1, { 0x6A, 0x8A },{   AF_S,  AF_S,  AF_S,  AF_S},  AF_IEEE },
  130         {"SIN",                       1, { 0x6E, 0x8D },{   AF_S,  AF_S,  AF_S,  AF_S},  0 },
  131         {"COS",                       1, { 0x6F, 0x8E },{   AF_S,  AF_S,  AF_S,  AF_S},  0 },
  132         {"MULLO_INT",                 2, { 0x73, 0x8F },{   AF_S,  AF_S,  AF_S,  AF_4V},  AF_M_COMM | AF_INT_DST | AF_REPL},
  133         {"MULHI_INT",                 2, { 0x74, 0x90 },{   AF_S,  AF_S,  AF_S,  AF_4V},  AF_M_COMM | AF_INT_DST | AF_REPL},
  134         {"MULLO_UINT",                2, { 0x75, 0x91 },{   AF_S,  AF_S,  AF_S,  AF_4V},  AF_M_COMM | AF_UINT_DST | AF_REPL},
  135         {"MULHI_UINT",                2, { 0x76, 0x92 },{   AF_S,  AF_S,  AF_S,  AF_4V},  AF_M_COMM | AF_UINT_DST | AF_REPL},
  136         {"RECIP_INT",                 1, { 0x77, 0x93 },{   AF_S,  AF_S,  AF_S,     0},  AF_INT_DST },
  137         {"RECIP_UINT",                1, { 0x78, 0x94 },{   AF_S,  AF_S,  AF_S,     0},  AF_UINT_DST },
  138         {"RECIP_64",                  2, {   -1, 0x95 },{      0,     0,  AF_S,  AF_S},  AF_64 },
  139         {"RECIP_CLAMPED_64",          2, {   -1, 0x96 },{      0,     0,  AF_S,  AF_S},  AF_64 },
  140         {"RECIPSQRT_64",              2, {   -1, 0x97 },{      0,     0,  AF_S,  AF_S},  AF_64 },
  141         {"RECIPSQRT_CLAMPED_64",      2, {   -1, 0x98 },{      0,     0,  AF_S,  AF_S},  AF_64 },
  142         {"SQRT_64",                   2, {   -1, 0x99 },{      0,     0,  AF_S,  AF_S},  AF_64 },
  143         {"FLT_TO_UINT",               1, { 0x79, 0x9A },{   AF_S,  AF_S,  AF_S,  AF_V},  AF_UINT_DST | AF_CVT},
  144         {"INT_TO_FLT",                1, { 0x6C, 0x9B },{   AF_S,  AF_S,  AF_S,  AF_V},  AF_CVT},
  145         {"UINT_TO_FLT",               1, { 0x6D, 0x9C },{   AF_S,  AF_S,  AF_S,  AF_V},  AF_CVT },
  146         {"BFM_INT",                   2, {   -1, 0xA0 },{      0,     0,  AF_V,  AF_V},  AF_INT_DST },
  147         {"FLT32_TO_FLT16",            1, {   -1, 0xA2 },{      0,     0,  AF_V,  AF_V},  0 },
  148         {"FLT16_TO_FLT32",            1, {   -1, 0xA3 },{      0,     0,  AF_V,  AF_V},  0 },
  149         {"UBYTE0_FLT",                1, {   -1, 0xA4 },{      0,     0,  AF_V,  AF_V},  0 },
  150         {"UBYTE1_FLT",                1, {   -1, 0xA5 },{      0,     0,  AF_V,  AF_V},  0 },
  151         {"UBYTE2_FLT",                1, {   -1, 0xA6 },{      0,     0,  AF_V,  AF_V},  0 },
  152         {"UBYTE3_FLT",                1, {   -1, 0xA7 },{      0,     0,  AF_V,  AF_V},  0 },
  153         {"BCNT_INT",                  1, {   -1, 0xAA },{      0,     0,  AF_V,  AF_V},  AF_INT_DST },
  154         {"FFBH_UINT",                 1, {   -1, 0xAB },{      0,     0,  AF_V,  AF_V},  AF_UINT_DST },
  155         {"FFBL_INT",                  1, {   -1, 0xAC },{      0,     0,  AF_V,  AF_V},  AF_INT_DST },
  156         {"FFBH_INT",                  1, {   -1, 0xAD },{      0,     0,  AF_V,  AF_V},  AF_INT_DST },
  157         {"FLT_TO_UINT4",              1, {   -1, 0xAE },{      0,     0,  AF_V,  AF_V},  AF_UINT_DST },
  158         {"DOT_IEEE",                  2, {   -1, 0xAF },{      0,     0,  AF_V,  AF_V},  AF_PREV_NEXT | AF_IEEE },
  159         {"FLT_TO_INT_RPI",            1, {   -1, 0xB0 },{      0,     0,  AF_V,  AF_V},  AF_INT_DST | AF_CVT},
  160         {"FLT_TO_INT_FLOOR",          1, {   -1, 0xB1 },{      0,     0,  AF_V,  AF_V},  AF_INT_DST | AF_CVT},
  161         {"MULHI_UINT24",              2, {   -1, 0xB2 },{      0,     0,  AF_V,  AF_V},  AF_UINT_DST | AF_24 },
  162         {"MBCNT_32HI_INT",            1, {   -1, 0xB3 },{      0,     0,  AF_V,  AF_V},  AF_INT_DST },
  163         {"OFFSET_TO_FLT",             1, {   -1, 0xB4 },{      0,     0,  AF_V,  AF_V},  0 },
  164         {"MUL_UINT24",                2, {   -1, 0xB5 },{      0,     0,  AF_V,  AF_V},  AF_UINT_DST | AF_24 },
  165         {"BCNT_ACCUM_PREV_INT",       1, {   -1, 0xB6 },{      0,     0,  AF_V,  AF_V},  AF_INT_DST | AF_PREV_NEXT },
  166         {"MBCNT_32LO_ACCUM_PREV_INT", 1, {   -1, 0xB7 },{      0,     0,  AF_V,  AF_V},  AF_INT_DST | AF_PREV_NEXT },
  167         {"SETE_64",                   2, {   -1, 0xB8 },{      0,     0,  AF_V,  AF_V},  AF_SET | AF_CC_E | AF_64 },
  168         {"SETNE_64",                  2, {   -1, 0xB9 },{      0,     0,  AF_V,  AF_V},  AF_SET | AF_CC_NE | AF_64 },
  169         {"SETGT_64",                  2, {   -1, 0xBA },{      0,     0,  AF_V,  AF_V},  AF_SET | AF_CC_GT | AF_64 },
  170         {"SETGE_64",                  2, {   -1, 0xBB },{      0,     0,  AF_V,  AF_V},  AF_SET | AF_CC_GE | AF_64 },
  171         {"MIN_64",                    2, {   -1, 0xBC },{      0,     0,  AF_V,  AF_V},  AF_64 },
  172         {"MAX_64",                    2, {   -1, 0xBD },{      0,     0,  AF_V,  AF_V},  AF_64 },
  173         {"DOT4",                      2, { 0x50, 0xBE },{  AF_4V, AF_4V, AF_4V, AF_4V},  AF_REPL },
  174         {"DOT4_IEEE",                 2, { 0x51, 0xBF },{  AF_4V, AF_4V, AF_4V, AF_4V},  AF_REPL | AF_IEEE  },
  175         {"CUBE",                      2, { 0x52, 0xC0 },{  AF_4V, AF_4V, AF_4V, AF_4V},  0 },
  176         {"MAX4",                      1, { 0x53, 0xC1 },{  AF_4V, AF_4V, AF_4V, AF_4V},  AF_REPL },
  177         {"FREXP_64",                  1, { 0x07, 0xC4 },{   AF_V,  AF_V,  AF_V,  AF_V},  AF_64 },
  178         {"LDEXP_64",                  2, { 0x7A, 0xC5 },{   AF_V,  AF_V,  AF_V,  AF_V},  AF_64 },
  179         {"FRACT_64",                  1, { 0x7B, 0xC6 },{   AF_V,  AF_V,  AF_V,  AF_V},  AF_64 },
  180         {"PRED_SETGT_64",             2, { 0x7C, 0xC7 },{   AF_V,  AF_V,  AF_V,  AF_V},  AF_PRED | AF_CC_GT | AF_64 },
  181         {"PRED_SETE_64",              2, { 0x7D, 0xC8 },{   AF_V,  AF_V,  AF_V,  AF_V},  AF_PRED | AF_CC_E | AF_64 },
  182         {"PRED_SETGE_64",             2, { 0x7E, 0xC9 },{   AF_V,  AF_V,  AF_V,  AF_V},  AF_PRED | AF_CC_GE | AF_64 },
  183         {"MUL_64",                    2, { 0x1B, 0xCA },{   AF_V,  AF_V,  AF_V,  AF_4V}, AF_64 },
  184         {"ADD_64",                    2, { 0x17, 0xCB },{   AF_V,  AF_V,  AF_V,  AF_V},  AF_64 },
  185         {"MOVA_INT",                  1, { 0x18, 0xCC },{   AF_V,  AF_V,  AF_V,  AF_V},  AF_MOVA },
  186         {"FLT64_TO_FLT32",            1, { 0x1C, 0xCD },{   AF_V,  AF_V,  AF_V,  AF_V},  AF_64 },
  187         {"FLT32_TO_FLT64",            1, { 0x1D, 0xCE },{   AF_V,  AF_V,  AF_V,  AF_V},  AF_64 },
  188         {"SAD_ACCUM_PREV_UINT",       2, {   -1, 0xCF },{      0,     0,  AF_V,  AF_V},  AF_UINT_DST | AF_PREV_NEXT },
  189         {"DOT",                       2, {   -1, 0xD0 },{      0,     0,  AF_V,  AF_V},  AF_PREV_NEXT },
  190         {"MUL_PREV",                  1, {   -1, 0xD1 },{      0,     0,  AF_V,  AF_V},  AF_PREV_INTERLEAVE },
  191         {"MUL_IEEE_PREV",             1, {   -1, 0xD2 },{      0,     0,  AF_V,  AF_V},  AF_PREV_INTERLEAVE | AF_IEEE },
  192         {"ADD_PREV",                  1, {   -1, 0xD3 },{      0,     0,  AF_V,  AF_V},  AF_PREV_INTERLEAVE },
  193         {"MULADD_PREV",               2, {   -1, 0xD4 },{      0,     0,  AF_V,  AF_V},  AF_PREV_INTERLEAVE },
  194         {"MULADD_IEEE_PREV",          2, {   -1, 0xD5 },{      0,     0,  AF_V,  AF_V},  AF_PREV_INTERLEAVE | AF_IEEE },
  195         {"INTERP_XY",                 2, {   -1, 0xD6 },{      0,     0, AF_4V, AF_4V},  AF_INTERP },
  196         {"INTERP_ZW",                 2, {   -1, 0xD7 },{      0,     0, AF_4V, AF_4V},  AF_INTERP },
  197         {"INTERP_X",                  2, {   -1, 0xD8 },{      0,     0,  AF_V,  AF_V},  AF_INTERP },
  198         {"INTERP_Z",                  2, {   -1, 0xD9 },{      0,     0,  AF_V,  AF_V},  AF_INTERP },
  199         {"STORE_FLAGS",               1, {   -1, 0xDA },{      0,     0,  AF_V,  AF_V},  0 },
  200         {"LOAD_STORE_FLAGS",          1, {   -1, 0xDB },{      0,     0,  AF_V,  AF_V},  0 },
  201         {"LDS_1A",                    2, {   -1, 0xDC },{      0,     0,  AF_V,  AF_V},  0 },
  202         {"LDS_1A1D",                  2, {   -1, 0xDD },{      0,     0,  AF_V,  AF_V},  0 },
  203         {"LDS_2A",                    2, {   -1, 0xDF },{      0,     0,  AF_V,  AF_V},  0 },
  204         {"INTERP_LOAD_P0",            1, {   -1, 0xE0 },{      0,     0,  AF_V,  AF_V},  AF_INTERP },
  205         {"INTERP_LOAD_P10",           1, {   -1, 0xE1 },{      0,     0,  AF_V,  AF_V},  AF_INTERP },
  206         {"INTERP_LOAD_P20",           1, {   -1, 0xE2 },{      0,     0,  AF_V,  AF_V},  AF_INTERP },
  207         {"BFE_UINT",                  3, {   -1, 0x04 },{      0,     0,  AF_V,  AF_V},  AF_UINT_DST },
  208         {"BFE_INT",                   3, {   -1, 0x05 },{      0,     0,  AF_V,  AF_V},  AF_INT_DST },
  209         {"BFI_INT",                   3, {   -1, 0x06 },{      0,     0,  AF_V,  AF_V},  AF_INT_DST },
  210         {"FMA",                       3, {   -1, 0x07 },{      0,     0,  AF_V,  AF_V},  0 },
  211         {"MULADD_INT24",              3, {   -1, 0x08 },{      0,     0,     0,  AF_V},  AF_INT_DST | AF_24 },
  212         {"CNDNE_64",                  3, {   -1, 0x09 },{      0,     0,  AF_V,  AF_V},  AF_CMOV | AF_64 },
  213         {"FMA_64",                    3, {   -1, 0x0A },{      0,     0,  AF_V,  AF_4V}, AF_64 },
  214         {"LERP_UINT",                 3, {   -1, 0x0B },{      0,     0,  AF_V,  AF_V},  AF_UINT_DST },
  215         {"BIT_ALIGN_INT",             3, {   -1, 0x0C },{      0,     0,  AF_V,  AF_V},  AF_INT_DST },
  216         {"BYTE_ALIGN_INT",            3, {   -1, 0x0D },{      0,     0,  AF_V,  AF_V},  AF_INT_DST },
  217         {"SAD_ACCUM_UINT",            3, {   -1, 0x0E },{      0,     0,  AF_V,  AF_V},  AF_UINT_DST },
  218         {"SAD_ACCUM_HI_UINT",         3, {   -1, 0x0F },{      0,     0,  AF_V,  AF_V},  AF_UINT_DST },
  219         {"MULADD_UINT24",             3, {   -1, 0x10 },{      0,     0,  AF_V,  AF_V},  AF_UINT_DST | AF_24 },
  220         {"LDS_IDX_OP",                3, {   -1, 0x11 },{      0,     0,  AF_V,  AF_V},  0 },
  221         {"MULADD",                    3, { 0x10, 0x14 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC },
  222         {"MULADD_M2",                 3, { 0x11, 0x15 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC },
  223         {"MULADD_M4",                 3, { 0x12, 0x16 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC },
  224         {"MULADD_D2",                 3, { 0x13, 0x17 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC },
  225         {"MULADD_IEEE",               3, { 0x14, 0x18 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_M_COMM | AF_M_ASSOC | AF_IEEE },
  226         {"CNDE",                      3, { 0x18, 0x19 },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_CMOV | AF_CC_E },
  227         {"CNDGT",                     3, { 0x19, 0x1A },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_CMOV | AF_CC_GT },
  228         {"CNDGE",                     3, { 0x1A, 0x1B },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_CMOV | AF_CC_GE },
  229         {"CNDE_INT",                  3, { 0x1C, 0x1C },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_CMOV | AF_CC_E | AF_INT_CMP },
  230         {"CNDGT_INT",                 3, { 0x1D, 0x1D },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_CMOV | AF_CC_GT | AF_INT_CMP },
  231         {"CNDGE_INT",                 3, { 0x1E, 0x1E },{  AF_VS, AF_VS, AF_VS, AF_VS},  AF_CMOV | AF_CC_GE | AF_INT_CMP },
  232         {"MUL_LIT",                   3, { 0x0C, 0x1F },{   AF_S,  AF_S,  AF_S,  AF_V},  0 },
  233 
  234         {"MOVA",                      1, { 0x15,   -1 },{   AF_V,  AF_V,     0,     0},  AF_MOVA },
  235         {"MOVA_FLOOR",                1, { 0x16,   -1 },{   AF_V,  AF_V,     0,     0},  AF_MOVA },
  236         {"MOVA_GPR_INT",              1, { 0x60,   -1 },{   AF_S,     0,     0,     0},  AF_MOVA },
  237 
  238         {"MULADD_64",                 3, { 0x08,   -1 },{   AF_V,  AF_V,     0,     0},  AF_64 },
  239         {"MULADD_64_M2",              3, { 0x09,   -1 },{   AF_V,  AF_V,     0,     0},  AF_64 },
  240         {"MULADD_64_M4",              3, { 0x0A,   -1 },{   AF_V,  AF_V,     0,     0},  AF_64 },
  241         {"MULADD_64_D2",              3, { 0x0B,   -1 },{   AF_V,  AF_V,     0,     0},  AF_64 },
  242         {"MUL_LIT_M2",                3, { 0x0D,   -1 },{  AF_VS, AF_VS,     0,     0},  0 },
  243         {"MUL_LIT_M4",                3, { 0x0E,   -1 },{  AF_VS, AF_VS,     0,     0},  0 },
  244         {"MUL_LIT_D2",                3, { 0x0F,   -1 },{  AF_VS, AF_VS,     0,     0},  0 },
  245         {"MULADD_IEEE_M2",            3, { 0x15,   -1 },{  AF_VS, AF_VS,     0,     0},  AF_M_COMM | AF_M_ASSOC | AF_IEEE },
  246         {"MULADD_IEEE_M4",            3, { 0x16,   -1 },{  AF_VS, AF_VS,     0,     0},  AF_M_COMM | AF_M_ASSOC | AF_IEEE },
  247         {"MULADD_IEEE_D2",            3, { 0x17,   -1 },{  AF_VS, AF_VS,     0,     0},  AF_M_COMM | AF_M_ASSOC | AF_IEEE },
  248 
  249         {"LDS_ADD",                   2, {   -1, 0x0011 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  250         {"LDS_SUB",                   2, {   -1, 0x0111 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  251         {"LDS_RSUB",                  2, {   -1, 0x0211 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  252         {"LDS_INC",                   2, {   -1, 0x0311 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  253         {"LDS_DEC",                   2, {   -1, 0x0411 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  254         {"LDS_MIN_INT",               2, {   -1, 0x0511 },{      0,     0,  AF_V,  AF_V},  AF_LDS | AF_INT_DST },
  255         {"LDS_MAX_INT",               2, {   -1, 0x0611 },{      0,     0,  AF_V,  AF_V},  AF_LDS | AF_INT_DST },
  256         {"LDS_MIN_UINT",              2, {   -1, 0x0711 },{      0,     0,  AF_V,  AF_V},  AF_LDS | AF_UINT_DST },
  257         {"LDS_MAX_UINT",              2, {   -1, 0x0811 },{      0,     0,  AF_V,  AF_V},  AF_LDS | AF_UINT_DST },
  258         {"LDS_AND",                   2, {   -1, 0x0911 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  259         {"LDS_OR",                    2, {   -1, 0x0A11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  260         {"LDS_XOR",                   2, {   -1, 0x0B11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  261         {"LDS_MSKOR",                 3, {   -1, 0x0C11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  262         {"LDS_WRITE",                 2, {   -1, 0x0D11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  263         {"LDS_WRITE_REL",             3, {   -1, 0x0E11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  264         {"LDS_WRITE2",                3, {   -1, 0x0F11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  265         {"LDS_CMP_STORE",             3, {   -1, 0x1011 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  266         {"LDS_CMP_STORE_SPF",         3, {   -1, 0x1111 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  267         {"LDS_BYTE_WRITE",            2, {   -1, 0x1211 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  268         {"LDS_SHORT_WRITE",           2, {   -1, 0x1311 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  269         {"LDS_ADD_RET",               2, {   -1, 0x2011 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  270         {"LDS_SUB_RET",               2, {   -1, 0x2111 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  271         {"LDS_RSUB_RET",              2, {   -1, 0x2211 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  272         {"LDS_INC_RET",               2, {   -1, 0x2311 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  273         {"LDS_DEC_RET",               2, {   -1, 0x2411 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  274         {"LDS_MIN_INT_RET",           2, {   -1, 0x2511 },{      0,     0,  AF_V,  AF_V},  AF_LDS | AF_INT_DST },
  275         {"LDS_MAX_INT_RET",           2, {   -1, 0x2611 },{      0,     0,  AF_V,  AF_V},  AF_LDS | AF_INT_DST },
  276         {"LDS_MIN_UINT_RET",          2, {   -1, 0x2711 },{      0,     0,  AF_V,  AF_V},  AF_LDS | AF_UINT_DST },
  277         {"LDS_MAX_UINT_RET",          2, {   -1, 0x2811 },{      0,     0,  AF_V,  AF_V},  AF_LDS | AF_UINT_DST },
  278         {"LDS_AND_RET",               2, {   -1, 0x2911 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  279         {"LDS_OR_RET",                2, {   -1, 0x2A11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  280         {"LDS_XOR_RET",               2, {   -1, 0x2B11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  281         {"LDS_MSKOR_RET",             3, {   -1, 0x2C11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  282         {"LDS_XCHG_RET",              2, {   -1, 0x2D11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  283         {"LDS_XCHG_REL_RET",          3, {   -1, 0x2E11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  284         {"LDS_XCHG2_RET",             3, {   -1, 0x2F11 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  285         {"LDS_CMP_XCHG_RET",          3, {   -1, 0x3011 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  286         {"LDS_CMP_XCHG_SPF_RET",      3, {   -1, 0x3111 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  287         {"LDS_READ_RET",              1, {   -1, 0x3211 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  288         {"LDS_READ_REL_RET",          1, {   -1, 0x3311 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  289         {"LDS_READ2_RET",             2, {   -1, 0x3411 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  290         {"LDS_READWRITE_RET",         3, {   -1, 0x3511 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  291         {"LDS_BYTE_READ_RET",         1, {   -1, 0x3611 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  292         {"LDS_UBYTE_READ_RET",        1, {   -1, 0x3711 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  293         {"LDS_SHORT_READ_RET",        1, {   -1, 0x3811 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  294         {"LDS_USHORT_READ_RET",       1, {   -1, 0x3911 },{      0,     0,  AF_V,  AF_V},  AF_LDS },
  295 };
  296 
  297 static const struct fetch_op_info fetch_op_table[] = {
  298         {"VFETCH",                        { 0x000000,  0x000000,  0x000000,  0x000000 }, FF_VTX },
  299         {"SEMFETCH",                      { 0x000001,  0x000001,  0x000001,  0x000001 }, FF_VTX },
  300 
  301         {"READ_SCRATCH",                  {       -1,  0x000002,  0x000002,  0x000002 }, FF_VTX | FF_MEM },
  302         {"READ_REDUCT",                   {       -1,  0x000102,        -1,        -1 }, FF_VTX | FF_MEM },
  303         {"READ_MEM",                      {       -1,  0x000202,  0x000202,  0x000202 }, FF_VTX | FF_MEM },
  304         {"DS_LOCAL_WRITE",                {       -1,  0x000402,        -1,        -1 }, FF_VTX | FF_MEM },
  305         {"DS_LOCAL_READ",                 {       -1,  0x000502,        -1,        -1 }, FF_VTX | FF_MEM },
  306 
  307         {"GDS_ADD",                       {       -1,        -1,  0x020002,  0x020002 }, FF_GDS },
  308         {"GDS_SUB",                       {       -1,        -1,  0x020102,  0x020102 }, FF_GDS },
  309         {"GDS_RSUB",                      {       -1,        -1,  0x020202,  0x020202 }, FF_GDS },
  310         {"GDS_INC",                       {       -1,        -1,  0x020302,  0x020302 }, FF_GDS },
  311         {"GDS_DEC",                       {       -1,        -1,  0x020402,  0x020402 }, FF_GDS },
  312         {"GDS_MIN_INT",                   {       -1,        -1,  0x020502,  0x020502 }, FF_GDS },
  313         {"GDS_MAX_INT",                   {       -1,        -1,  0x020602,  0x020602 }, FF_GDS },
  314         {"GDS_MIN_UINT",                  {       -1,        -1,  0x020702,  0x020702 }, FF_GDS },
  315         {"GDS_MAX_UINT",                  {       -1,        -1,  0x020802,  0x020802 }, FF_GDS },
  316         {"GDS_AND",                       {       -1,        -1,  0x020902,  0x020902 }, FF_GDS },
  317         {"GDS_OR",                        {       -1,        -1,  0x020A02,  0x020A02 }, FF_GDS },
  318         {"GDS_XOR",                       {       -1,        -1,  0x020B02,  0x020B02 }, FF_GDS },
  319         {"GDS_MSKOR",                     {       -1,        -1,  0x030C02,  0x030C02 }, FF_GDS },
  320         {"GDS_WRITE",                     {       -1,        -1,  0x020D02,  0x020D02 }, FF_GDS },
  321         {"GDS_WRITE_REL",                 {       -1,        -1,  0x030E02,  0x030E02 }, FF_GDS },
  322         {"GDS_WRITE2",                    {       -1,        -1,  0x030F02,  0x030F02 }, FF_GDS },
  323         {"GDS_CMP_STORE",                 {       -1,        -1,  0x031002,  0x031002 }, FF_GDS },
  324         {"GDS_CMP_STORE_SPF",             {       -1,        -1,  0x031102,  0x031102 }, FF_GDS },
  325         {"GDS_BYTE_WRITE",                {       -1,        -1,  0x021202,  0x021202 }, FF_GDS },
  326         {"GDS_SHORT_WRITE",               {       -1,        -1,  0x021302,  0x021302 }, FF_GDS },
  327         {"GDS_ADD_RET",                   {       -1,        -1,  0x122002,  0x122002 }, FF_GDS },
  328         {"GDS_SUB_RET",                   {       -1,        -1,  0x122102,  0x122102 }, FF_GDS },
  329         {"GDS_RSUB_RET",                  {       -1,        -1,  0x122202,  0x122202 }, FF_GDS },
  330         {"GDS_INC_RET",                   {       -1,        -1,  0x122302,  0x122302 }, FF_GDS },
  331         {"GDS_DEC_RET",                   {       -1,        -1,  0x122402,  0x122402 }, FF_GDS },
  332         {"GDS_MIN_INT_RET",               {       -1,        -1,  0x122502,  0x122502 }, FF_GDS },
  333         {"GDS_MAX_INT_RET",               {       -1,        -1,  0x122602,  0x122602 }, FF_GDS },
  334         {"GDS_MIN_UINT_RET",              {       -1,        -1,  0x122702,  0x122702 }, FF_GDS },
  335         {"GDS_MAX_UINT_RET",              {       -1,        -1,  0x122802,  0x122802 }, FF_GDS },
  336         {"GDS_AND_RET",                   {       -1,        -1,  0x122902,  0x122902 }, FF_GDS },
  337         {"GDS_OR_RET",                    {       -1,        -1,  0x122A02,  0x122A02 }, FF_GDS },
  338         {"GDS_XOR_RET",                   {       -1,        -1,  0x122B02,  0x122B02 }, FF_GDS },
  339         {"GDS_MSKOR_RET",                 {       -1,        -1,  0x132C02,  0x132C02 }, FF_GDS },
  340         {"GDS_XCHG_RET",                  {       -1,        -1,  0x122D02,  0x122D02 }, FF_GDS },
  341         {"GDS_XCHG_REL_RET",              {       -1,        -1,  0x232E02,  0x232E02 }, FF_GDS },
  342         {"GDS_XCHG2_RET",                 {       -1,        -1,  0x232F02,  0x232F02 }, FF_GDS },
  343         {"GDS_CMP_XCHG_RET",              {       -1,        -1,  0x133002,  0x133002 }, FF_GDS },
  344         {"GDS_CMP_XCHG_SPF_RET",          {       -1,        -1,  0x133102,  0x133102 }, FF_GDS },
  345         {"GDS_READ_RET",                  {       -1,        -1,  0x113202,  0x113202 }, FF_GDS },
  346         {"GDS_READ_REL_RET",              {       -1,        -1,  0x213302,  0x213302 }, FF_GDS },
  347         {"GDS_READ2_RET",                 {       -1,        -1,  0x223402,  0x223402 }, FF_GDS },
  348         {"GDS_READWRITE_RET",             {       -1,        -1,  0x133502,  0x133502 }, FF_GDS },
  349         {"GDS_BYTE_READ_RET",             {       -1,        -1,  0x113602,  0x113602 }, FF_GDS },
  350         {"GDS_UBYTE_READ_RET",            {       -1,        -1,  0x113702,  0x113702 }, FF_GDS },
  351         {"GDS_SHORT_READ_RET",            {       -1,        -1,  0x113802,  0x113802 }, FF_GDS },
  352         {"GDS_USHORT_READ_RET",           {       -1,        -1,  0x113902,  0x113902 }, FF_GDS },
  353         {"GDS_ATOMIC_ORDERED_ALLOC",      {       -1,        -1,  0x113F02,  0x113F02 }, FF_GDS },
  354 
  355         {"TF_WRITE",                      {       -1,        -1,  0x020502,  0x020502 }, FF_GDS },
  356 
  357         {"DS_GLOBAL_WRITE",               {       -1,  0x000602,        -1,        -1 }, 0 },
  358         {"DS_GLOBAL_READ",                {       -1,  0x000702,        -1,        -1 }, 0 },
  359 
  360         {"LD",                            { 0x000003,  0x000003,  0x000003,  0x000003 }, 0 },
  361         {"LDFPTR",                        {       -1,        -1,  0x000103,  0x000103 }, 0 },
  362         {"GET_TEXTURE_RESINFO",           { 0x000004,  0x000004,  0x000004,  0x000004 }, 0 },
  363         {"GET_NUMBER_OF_SAMPLES",         { 0x000005,  0x000005,  0x000005,  0x000005 }, 0 },
  364         {"GET_LOD",                       { 0x000006,  0x000006,  0x000006,  0x000006 }, 0 },
  365         {"GET_GRADIENTS_H",               { 0x000007,  0x000007,  0x000007,  0x000007 }, FF_GETGRAD },
  366         {"GET_GRADIENTS_V",               { 0x000008,  0x000008,  0x000008,  0x000008 }, FF_GETGRAD },
  367         {"GET_GRADIENTS_H_FINE",          {       -1,        -1,  0x000107,  0x000107 }, FF_GETGRAD },
  368         {"GET_GRADIENTS_V_FINE",          {       -1,        -1,  0x000108,  0x000108 }, FF_GETGRAD },
  369         {"GET_LERP",                      { 0x000009,  0x000009,        -1,        -1 }, 0 },
  370         {"SET_TEXTURE_OFFSETS",           {       -1,        -1,  0x000009,  0x000009 }, FF_SET_TEXTURE_OFFSETS },
  371         {"KEEP_GRADIENTS",                {       -1,  0x00000A,  0x00000A,  0x00000A }, 0 },
  372         {"SET_GRADIENTS_H",               { 0x00000B,  0x00000B,  0x00000B,  0x00000B }, FF_SETGRAD },
  373         {"SET_GRADIENTS_V",               { 0x00000C,  0x00000C,  0x00000C,  0x00000C }, FF_SETGRAD },
  374         {"SET_GRADIENTS_H_COARSE",        {       -1,        -1,        -1,  0x00010B }, FF_SETGRAD },
  375         {"SET_GRADIENTS_V_COARSE",        {       -1,        -1,        -1,  0x00010C }, FF_SETGRAD },
  376         {"SET_GRADIENTS_H_PACKED_FINE",   {       -1,        -1,        -1,  0x00020B }, FF_SETGRAD },
  377         {"SET_GRADIENTS_V_PACKED_FINE",   {       -1,        -1,        -1,  0x00020C }, FF_SETGRAD },
  378         {"SET_GRADIENTS_H_PACKED_COARSE", {       -1,        -1,        -1,  0x00030B }, FF_SETGRAD },
  379         {"SET_GRADIENTS_V_PACKED_COARSE", {       -1,        -1,        -1,  0x00030C }, FF_SETGRAD },
  380         {"PASS",                          { 0x00000D,  0x00000D,  0x00000D,  0x00000D }, 0 }, /* ???? 700, eg, cm docs - marked as reserved */
  381         {"PASS1",                         {       -1,        -1,  0x00010D,  0x00010D }, 0 },
  382         {"PASS2",                         {       -1,        -1,  0x00020D,  0x00020D }, 0 },
  383         {"PASS3",                         {       -1,        -1,  0x00030D,  0x00030D }, 0 },
  384         {"SET_CUBEMAP_INDEX",             { 0x00000E,  0x00000E,        -1,        -1 }, 0 },
  385         {"GET_BUFFER_RESINFO",            {       -1,        -1,  0x00000E,  0x00000E }, FF_VTX },
  386         {"FETCH4",                        { 0x00000F,  0x00000F,        -1,        -1 }, 0 },
  387 
  388         {"SAMPLE",                        { 0x000010,  0x000010,  0x000010,  0x000010 }, FF_TEX },
  389         {"SAMPLE_L",                      { 0x000011,  0x000011,  0x000011,  0x000011 }, FF_TEX },
  390         {"SAMPLE_LB",                     { 0x000012,  0x000012,  0x000012,  0x000012 }, FF_TEX },
  391         {"SAMPLE_LZ",                     { 0x000013,  0x000013,  0x000013,  0x000013 }, FF_TEX },
  392         {"SAMPLE_G",                      { 0x000014,  0x000014,  0x000014,  0x000014 }, FF_TEX | FF_USEGRAD },
  393         {"SAMPLE_G_L",                    { 0x000015,  0x000015,        -1,        -1 }, FF_TEX | FF_USEGRAD},
  394         {"GATHER4",                       {       -1,        -1,  0x000015,  0x000015 }, FF_TEX },
  395         {"SAMPLE_G_LB",                   { 0x000016,  0x000016,  0x000016,  0x000016 }, FF_TEX | FF_USEGRAD},
  396         {"SAMPLE_G_LZ",                   { 0x000017,  0x000017,        -1,        -1 }, FF_TEX | FF_USEGRAD},
  397         {"GATHER4_O",                     {       -1,        -1,  0x000017,  0x000017 }, FF_TEX | FF_USE_TEXTURE_OFFSETS},
  398         {"SAMPLE_C",                      { 0x000018,  0x000018,  0x000018,  0x000018 }, FF_TEX },
  399         {"SAMPLE_C_L",                    { 0x000019,  0x000019,  0x000019,  0x000019 }, FF_TEX },
  400         {"SAMPLE_C_LB",                   { 0x00001A,  0x00001A,  0x00001A,  0x00001A }, FF_TEX },
  401         {"SAMPLE_C_LZ",                   { 0x00001B,  0x00001B,  0x00001B,  0x00001B }, FF_TEX },
  402         {"SAMPLE_C_G",                    { 0x00001C,  0x00001C,  0x00001C,  0x00001C }, FF_TEX | FF_USEGRAD},
  403         {"SAMPLE_C_G_L",                  { 0x00001D,  0x00001D,        -1,        -1 }, FF_TEX | FF_USEGRAD},
  404         {"GATHER4_C",                     {       -1,        -1,  0x00001D,  0x00001D }, FF_TEX },
  405         {"SAMPLE_C_G_LB",                 { 0x00001E,  0x00001E,  0x00001E,  0x00001E }, FF_TEX | FF_USEGRAD},
  406         {"SAMPLE_C_G_LZ",                 { 0x00001F,  0x00001F,        -1,        -1 }, FF_TEX | FF_USEGRAD},
  407         {"GATHER4_C_O",                   {       -1,        -1,  0x00001F,  0x00001F }, FF_TEX | FF_USE_TEXTURE_OFFSETS}
  408 };
  409 
  410 static const struct cf_op_info cf_op_table[] = {
  411         {"NOP",                           { 0x00, 0x00, 0x00, 0x00 },  0  },
  412 
  413         {"TEX",                           { 0x01, 0x01, 0x01, 0x01 },  CF_CLAUSE | CF_FETCH | CF_UNCOND }, /* merged with "TC" entry */
  414         {"VTX",                           { 0x02, 0x02, 0x02,   -1 },  CF_CLAUSE | CF_FETCH | CF_UNCOND }, /* merged with "VC" entry */
  415         {"VTX_TC",                        { 0x03, 0x03,   -1,   -1 },  CF_CLAUSE | CF_FETCH | CF_UNCOND },
  416         {"GDS",                           {   -1,   -1, 0x03, 0x03 },  CF_CLAUSE | CF_FETCH | CF_UNCOND },
  417 
  418         {"LOOP_START",                    { 0x04, 0x04, 0x04, 0x04 },  CF_LOOP | CF_LOOP_START },
  419         {"LOOP_END",                      { 0x05, 0x05, 0x05, 0x05 },  CF_LOOP  },
  420         {"LOOP_START_DX10",               { 0x06, 0x06, 0x06, 0x06 },  CF_LOOP | CF_LOOP_START },
  421         {"LOOP_START_NO_AL",              { 0x07, 0x07, 0x07, 0x07 },  CF_LOOP | CF_LOOP_START },
  422         {"LOOP_CONTINUE",                 { 0x08, 0x08, 0x08, 0x08 },  CF_LOOP  },
  423         {"LOOP_BREAK",                    { 0x09, 0x09, 0x09, 0x09 },  CF_LOOP  },
  424         {"JUMP",                          { 0x0A, 0x0A, 0x0A, 0x0A },  CF_BRANCH  },
  425         {"PUSH",                          { 0x0B, 0x0B, 0x0B, 0x0B },  CF_BRANCH  },
  426         {"PUSH_ELSE",                     { 0x0C, 0x0C,   -1,   -1 },  CF_BRANCH  },
  427         {"ELSE",                          { 0x0D, 0x0D, 0x0D, 0x0D },  CF_BRANCH  },
  428         {"POP",                           { 0x0E, 0x0E, 0x0E, 0x0E },  CF_BRANCH  },
  429         {"POP_JUMP",                      { 0x0F, 0x0F,   -1,   -1 },  CF_BRANCH  },
  430         {"POP_PUSH",                      { 0x10, 0x10,   -1,   -1 },  CF_BRANCH  },
  431         {"POP_PUSH_ELSE",                 { 0x11, 0x11,   -1,   -1 },  CF_BRANCH  },
  432         {"CALL",                          { 0x12, 0x12, 0x12, 0x12 },  CF_CALL  },
  433         {"CALL_FS",                       { 0x13, 0x13, 0x13, 0x13 },  CF_CALL  },
  434         {"RET",                           { 0x14, 0x14, 0x14, 0x14 },  0 },
  435         {"EMIT_VERTEX",                   { 0x15, 0x15, 0x15, 0x15 },  CF_EMIT | CF_UNCOND },
  436         {"EMIT_CUT_VERTEX",               { 0x16, 0x16, 0x16, 0x16 },  CF_EMIT | CF_UNCOND  },
  437         {"CUT_VERTEX",                    { 0x17, 0x17, 0x17, 0x17 },  CF_EMIT | CF_UNCOND  },
  438         {"KILL",                          { 0x18, 0x18, 0x18, 0x18 },  CF_UNCOND  },
  439         {"END_PROGRAM",                   { 0x19, 0x19, 0x19, 0x19 },  0  },  /* ??? "reserved" in isa docs */
  440         {"WAIT_ACK",                      {   -1, 0x1A, 0x1A, 0x1A },  0  },
  441         {"TEX_ACK",                       {   -1, 0x1B, 0x1B, 0x1B },  CF_CLAUSE | CF_FETCH | CF_ACK | CF_UNCOND },
  442         {"VTX_ACK",                       {   -1, 0x1C, 0x1C,   -1 },  CF_CLAUSE | CF_FETCH | CF_ACK | CF_UNCOND },
  443         {"VTX_TC_ACK",                    {   -1, 0x1D,   -1,   -1 },  CF_CLAUSE | CF_FETCH | CF_ACK | CF_UNCOND },
  444         {"JUMPTABLE",                     {   -1,   -1, 0x1D, 0x1D },  CF_BRANCH  },
  445         {"WAVE_SYNC",                     {   -1,   -1, 0x1E, 0x1E },  0  },
  446         {"HALT",                          {   -1,   -1, 0x1F, 0x1F },  0  },
  447         {"CF_END",                        {   -1,   -1,   -1, 0x20 },  0  },
  448         {"LDS_DEALLOC",                   {   -1,   -1,   -1, 0x21 },  0  },
  449         {"PUSH_WQM",                      {   -1,   -1,   -1, 0x22 },  CF_BRANCH  },
  450         {"POP_WQM",                       {   -1,   -1,   -1, 0x23 },  CF_BRANCH  },
  451         {"ELSE_WQM",                      {   -1,   -1,   -1, 0x24 },  CF_BRANCH  },
  452         {"JUMP_ANY",                      {   -1,   -1,   -1, 0x25 },  CF_BRANCH  },
  453 
  454         /* ??? next 5 added from CAYMAN ISA doc, not in the original table */
  455         {"REACTIVATE",                    {   -1,   -1,   -1, 0x26 },  0  },
  456         {"REACTIVATE_WQM",                {   -1,   -1,   -1, 0x27 },  0  },
  457         {"INTERRUPT",                     {   -1,   -1,   -1, 0x28 },  0  },
  458         {"INTERRUPT_AND_SLEEP",           {   -1,   -1,   -1, 0x29 },  0  },
  459         {"SET_PRIORITY",                  {   -1,   -1,   -1, 0x2A },  0  },
  460 
  461         {"MEM_STREAM0_BUF0",              {   -1,   -1, 0x40, 0x40 },  CF_MEM | CF_STRM  },
  462         {"MEM_STREAM0_BUF1",              {   -1,   -1, 0x41, 0x41 },  CF_MEM | CF_STRM  },
  463         {"MEM_STREAM0_BUF2",              {   -1,   -1, 0x42, 0x42 },  CF_MEM | CF_STRM  },
  464         {"MEM_STREAM0_BUF3",              {   -1,   -1, 0x43, 0x43 },  CF_MEM | CF_STRM  },
  465         {"MEM_STREAM1_BUF0",              {   -1,   -1, 0x44, 0x44 },  CF_MEM | CF_STRM  },
  466         {"MEM_STREAM1_BUF1",              {   -1,   -1, 0x45, 0x45 },  CF_MEM | CF_STRM  },
  467         {"MEM_STREAM1_BUF2",              {   -1,   -1, 0x46, 0x46 },  CF_MEM | CF_STRM  },
  468         {"MEM_STREAM1_BUF3",              {   -1,   -1, 0x47, 0x47 },  CF_MEM | CF_STRM  },
  469         {"MEM_STREAM2_BUF0",              {   -1,   -1, 0x48, 0x48 },  CF_MEM | CF_STRM  },
  470         {"MEM_STREAM2_BUF1",              {   -1,   -1, 0x49, 0x49 },  CF_MEM | CF_STRM  },
  471         {"MEM_STREAM2_BUF2",              {   -1,   -1, 0x4A, 0x4A },  CF_MEM | CF_STRM  },
  472         {"MEM_STREAM2_BUF3",              {   -1,   -1, 0x4B, 0x4B },  CF_MEM | CF_STRM  },
  473         {"MEM_STREAM3_BUF0",              {   -1,   -1, 0x4C, 0x4C },  CF_MEM | CF_STRM  },
  474         {"MEM_STREAM3_BUF1",              {   -1,   -1, 0x4D, 0x4D },  CF_MEM | CF_STRM  },
  475         {"MEM_STREAM3_BUF2",              {   -1,   -1, 0x4E, 0x4E },  CF_MEM | CF_STRM  },
  476         {"MEM_STREAM3_BUF3",              {   -1,   -1, 0x4F, 0x4F },  CF_MEM | CF_STRM  },
  477 
  478         {"MEM_STREAM0",                   { 0x20, 0x20,   -1,   -1 },  CF_MEM | CF_STRM  },
  479         {"MEM_STREAM1",                   { 0x21, 0x21,   -1,   -1 },  CF_MEM | CF_STRM  },
  480         {"MEM_STREAM2",                   { 0x22, 0x22,   -1,   -1 },  CF_MEM | CF_STRM  },
  481         {"MEM_STREAM3",                   { 0x23, 0x23,   -1,   -1 },  CF_MEM | CF_STRM  },
  482 
  483         {"MEM_SCRATCH",                   { 0x24, 0x24, 0x50, 0x50 },  CF_MEM  },
  484         {"MEM_REDUCT",                    { 0x25, 0x25,   -1,   -1 },  CF_MEM  },
  485         {"MEM_RING",                      { 0x26, 0x26, 0x52, 0x52 },  CF_MEM | CF_EMIT },
  486 
  487         {"EXPORT",                        { 0x27, 0x27, 0x53, 0x53 },  CF_EXP  },
  488         {"EXPORT_DONE",                   { 0x28, 0x28, 0x54, 0x54 },  CF_EXP  },
  489 
  490         {"MEM_EXPORT",                    {   -1, 0x3A, 0x55, 0x55 },  CF_MEM  },
  491         {"MEM_RAT",                       {   -1,   -1, 0x56, 0x56 },  CF_MEM | CF_RAT },
  492         {"MEM_RAT_NOCACHE",               {   -1,   -1, 0x57, 0x57 },  CF_MEM | CF_RAT },
  493         {"MEM_RING1",                     {   -1,   -1, 0x58, 0x58 },  CF_MEM | CF_EMIT },
  494         {"MEM_RING2",                     {   -1,   -1, 0x59, 0x59 },  CF_MEM | CF_EMIT },
  495         {"MEM_RING3",                     {   -1,   -1, 0x5A, 0x5A },  CF_MEM | CF_EMIT },
  496         {"MEM_MEM_COMBINED",              {   -1,   -1, 0x5B, 0x5B },  CF_MEM  },
  497         {"MEM_RAT_COMBINED_NOCACHE",      {   -1,   -1, 0x5C, 0x5C },  CF_MEM | CF_RAT },
  498         {"MEM_RAT_COMBINED",              {   -1,   -1,   -1, 0x5D },  CF_MEM | CF_RAT }, /* ??? not in cayman isa doc */
  499 
  500         {"EXPORT_DONE_END",               {   -1,   -1,   -1, 0x5E },  CF_EXP  },   /* ??? not in cayman isa doc */
  501 
  502         {"ALU",                           { 0x08, 0x08, 0x08, 0x08 },  CF_CLAUSE | CF_ALU  },
  503         {"ALU_PUSH_BEFORE",               { 0x09, 0x09, 0x09, 0x09 },  CF_CLAUSE | CF_ALU  },
  504         {"ALU_POP_AFTER",                 { 0x0A, 0x0A, 0x0A, 0x0A },  CF_CLAUSE | CF_ALU  },
  505         {"ALU_POP2_AFTER",                { 0x0B, 0x0B, 0x0B, 0x0B },  CF_CLAUSE | CF_ALU  },
  506         {"ALU_EXT",                       {   -1,   -1, 0x0C, 0x0C },  CF_CLAUSE | CF_ALU | CF_ALU_EXT  },
  507         {"ALU_CONTINUE",                  { 0x0D, 0x0D, 0x0D,   -1 },  CF_CLAUSE | CF_ALU  },
  508         {"ALU_BREAK",                     { 0x0E, 0x0E, 0x0E,   -1 },  CF_CLAUSE | CF_ALU  },
  509         {"ALU_VALID_PIXEL_MODE",          {   -1,   -1,   -1, 0x0E },  CF_CLAUSE | CF_ALU  },
  510         {"ALU_ELSE_AFTER",                { 0x0F, 0x0F, 0x0F, 0x0F },  CF_CLAUSE | CF_ALU  },
  511         {"CF_NATIVE",                     { 0x00, 0x00, 0x00, 0x00 },  0  }
  512 };
  513 
  514 unsigned
  515 r600_alu_op_table_size(void)
  516 {
  517     return ARRAY_SIZE(r600_alu_op_table);
  518 }
  519 
  520 const struct alu_op_info *
  521 r600_isa_alu(unsigned op) {
  522     assert (op < ARRAY_SIZE(r600_alu_op_table));
  523     return &r600_alu_op_table[op];
  524 }
  525 
  526 const struct fetch_op_info *
  527 r600_isa_fetch(unsigned op) {
  528     assert (op < ARRAY_SIZE(fetch_op_table));
  529     return &fetch_op_table[op];
  530 }
  531 
  532 const struct cf_op_info *
  533 r600_isa_cf(unsigned op) {
  534     assert (op < ARRAY_SIZE(cf_op_table));
  535     return &cf_op_table[op];
  536 }
  537 
  538 int r600_isa_init(struct r600_context *ctx, struct r600_isa *isa) {
  539     unsigned i;
  540 
  541     assert(ctx->b.chip_class >= R600 && ctx->b.chip_class <= CAYMAN);
  542     isa->hw_class = ctx->b.chip_class - R600;
  543 
  544     /* reverse lookup maps are required for bytecode parsing */
  545 
  546     isa->alu_op2_map = calloc(256, sizeof(unsigned));
  547     if (!isa->alu_op2_map)
  548         return -1;
  549     isa->alu_op3_map = calloc(256, sizeof(unsigned));
  550     if (!isa->alu_op3_map)
  551         return -1;
  552     isa->fetch_map = calloc(256, sizeof(unsigned));
  553     if (!isa->fetch_map)
  554         return -1;
  555     isa->cf_map = calloc(256, sizeof(unsigned));
  556     if (!isa->cf_map)
  557         return -1;
  558 
  559     for (i = 0; i < ARRAY_SIZE(r600_alu_op_table); ++i) {
  560         const struct alu_op_info *op = &r600_alu_op_table[i];
  561         int opc;
  562         if (op->flags & AF_LDS || op->slots[isa->hw_class] == 0)
  563             continue;
  564         opc = op->opcode[isa->hw_class >> 1];
  565         assert(opc != -1);
  566         if (op->src_count == 3)
  567             isa->alu_op3_map[opc] = i + 1;
  568         else
  569             isa->alu_op2_map[opc] = i + 1;
  570     }
  571 
  572     for (i = 0; i < ARRAY_SIZE(fetch_op_table); ++i) {
  573         const struct fetch_op_info *op = &fetch_op_table[i];
  574         int opc = op->opcode[isa->hw_class];
  575         if ((op->flags & FF_GDS) || ((opc & 0xFF) != opc))
  576             continue; /* ignore GDS ops and INST_MOD versions for now */
  577         isa->fetch_map[opc] = i + 1;
  578     }
  579 
  580     for (i = 0; i < ARRAY_SIZE(cf_op_table); ++i) {
  581         const struct cf_op_info *op = &cf_op_table[i];
  582         int opc = op->opcode[isa->hw_class];
  583         if (opc == -1)
  584             continue;
  585         /* using offset for CF_ALU_xxx opcodes because they overlap with other
  586          * CF opcodes (they use different encoding in hw) */
  587         if (op->flags & CF_ALU)
  588             opc += 0x80;
  589         isa->cf_map[opc] = i + 1;
  590     }
  591 
  592     return 0;
  593 }
  594 
  595 int r600_isa_destroy(struct r600_isa *isa) {
  596 
  597     if (!isa)
  598         return 0;
  599 
  600     free(isa->alu_op2_map);
  601     free(isa->alu_op3_map);
  602     free(isa->fetch_map);
  603     free(isa->cf_map);
  604 
  605     free(isa);
  606     return 0;
  607 }
  608 
  609 
  610