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Member "mesa-20.1.8/src/gallium/drivers/r300/r300_context.c" (16 Sep 2020, 19143 Bytes) of package /linux/misc/mesa-20.1.8.tar.xz:


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    1 /*
    2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
    3  *
    4  * Permission is hereby granted, free of charge, to any person obtaining a
    5  * copy of this software and associated documentation files (the "Software"),
    6  * to deal in the Software without restriction, including without limitation
    7  * on the rights to use, copy, modify, merge, publish, distribute, sub
    8  * license, and/or sell copies of the Software, and to permit persons to whom
    9  * the Software is furnished to do so, subject to the following conditions:
   10  *
   11  * The above copyright notice and this permission notice (including the next
   12  * paragraph) shall be included in all copies or substantial portions of the
   13  * Software.
   14  *
   15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
   18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
   19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
   20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
   21  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
   22 
   23 #include "draw/draw_context.h"
   24 
   25 #include "util/u_memory.h"
   26 #include "util/u_sampler.h"
   27 #include "util/simple_list.h"
   28 #include "util/u_upload_mgr.h"
   29 #include "util/os_time.h"
   30 #include "vl/vl_decoder.h"
   31 #include "vl/vl_video_buffer.h"
   32 
   33 #include "r300_cb.h"
   34 #include "r300_context.h"
   35 #include "r300_emit.h"
   36 #include "r300_screen.h"
   37 #include "r300_screen_buffer.h"
   38 #include "compiler/radeon_regalloc.h"
   39 
   40 #include <inttypes.h>
   41 
   42 static void r300_release_referenced_objects(struct r300_context *r300)
   43 {
   44     struct pipe_framebuffer_state *fb =
   45             (struct pipe_framebuffer_state*)r300->fb_state.state;
   46     struct r300_textures_state *textures =
   47             (struct r300_textures_state*)r300->textures_state.state;
   48     unsigned i;
   49 
   50     /* Framebuffer state. */
   51     util_unreference_framebuffer_state(fb);
   52 
   53     /* Textures. */
   54     for (i = 0; i < textures->sampler_view_count; i++)
   55         pipe_sampler_view_reference(
   56                 (struct pipe_sampler_view**)&textures->sampler_views[i], NULL);
   57 
   58     /* The special dummy texture for texkill. */
   59     if (r300->texkill_sampler) {
   60         pipe_sampler_view_reference(
   61                 (struct pipe_sampler_view**)&r300->texkill_sampler,
   62                 NULL);
   63     }
   64 
   65     /* Manually-created vertex buffers. */
   66     pipe_vertex_buffer_unreference(&r300->dummy_vb);
   67     pb_reference(&r300->vbo, NULL);
   68 
   69     r300->context.delete_depth_stencil_alpha_state(&r300->context,
   70                                                    r300->dsa_decompress_zmask);
   71 }
   72 
   73 static void r300_destroy_context(struct pipe_context* context)
   74 {
   75     struct r300_context* r300 = r300_context(context);
   76 
   77     if (r300->cs && r300->hyperz_enabled) {
   78         r300->rws->cs_request_feature(r300->cs, RADEON_FID_R300_HYPERZ_ACCESS, FALSE);
   79     }
   80     if (r300->cs && r300->cmask_access) {
   81         r300->rws->cs_request_feature(r300->cs, RADEON_FID_R300_CMASK_ACCESS, FALSE);
   82     }
   83 
   84     if (r300->blitter)
   85         util_blitter_destroy(r300->blitter);
   86     if (r300->draw)
   87         draw_destroy(r300->draw);
   88 
   89     if (r300->uploader)
   90         u_upload_destroy(r300->uploader);
   91     if (r300->context.stream_uploader)
   92         u_upload_destroy(r300->context.stream_uploader);
   93 
   94     /* XXX: This function assumes r300->query_list was initialized */
   95     r300_release_referenced_objects(r300);
   96 
   97     if (r300->cs)
   98         r300->rws->cs_destroy(r300->cs);
   99     if (r300->ctx)
  100         r300->rws->ctx_destroy(r300->ctx);
  101 
  102     rc_destroy_regalloc_state(&r300->fs_regalloc_state);
  103 
  104     /* XXX: No way to tell if this was initialized or not? */
  105     slab_destroy_child(&r300->pool_transfers);
  106 
  107     /* Free the structs allocated in r300_setup_atoms() */
  108     if (r300->aa_state.state) {
  109         FREE(r300->aa_state.state);
  110         FREE(r300->blend_color_state.state);
  111         FREE(r300->clip_state.state);
  112         FREE(r300->fb_state.state);
  113         FREE(r300->gpu_flush.state);
  114         FREE(r300->hyperz_state.state);
  115         FREE(r300->invariant_state.state);
  116         FREE(r300->rs_block_state.state);
  117         FREE(r300->sample_mask.state);
  118         FREE(r300->scissor_state.state);
  119         FREE(r300->textures_state.state);
  120         FREE(r300->vap_invariant_state.state);
  121         FREE(r300->viewport_state.state);
  122         FREE(r300->ztop_state.state);
  123         FREE(r300->fs_constants.state);
  124         FREE(r300->vs_constants.state);
  125         if (!r300->screen->caps.has_tcl) {
  126             FREE(r300->vertex_stream_state.state);
  127         }
  128     }
  129     FREE(r300);
  130 }
  131 
  132 static void r300_flush_callback(void *data, unsigned flags,
  133                 struct pipe_fence_handle **fence)
  134 {
  135     struct r300_context* const cs_context_copy = data;
  136 
  137     r300_flush(&cs_context_copy->context, flags, fence);
  138 }
  139 
  140 #define R300_INIT_ATOM(atomname, atomsize) \
  141  do { \
  142     r300->atomname.name = #atomname; \
  143     r300->atomname.state = NULL; \
  144     r300->atomname.size = atomsize; \
  145     r300->atomname.emit = r300_emit_##atomname; \
  146     r300->atomname.dirty = FALSE; \
  147  } while (0)
  148 
  149 #define R300_ALLOC_ATOM(atomname, statetype) \
  150 do { \
  151     r300->atomname.state = CALLOC_STRUCT(statetype); \
  152     if (r300->atomname.state == NULL) \
  153         return FALSE; \
  154 } while (0)
  155 
  156 static boolean r300_setup_atoms(struct r300_context* r300)
  157 {
  158     boolean is_rv350 = r300->screen->caps.is_rv350;
  159     boolean is_r500 = r300->screen->caps.is_r500;
  160     boolean has_tcl = r300->screen->caps.has_tcl;
  161 
  162     /* Create the actual atom list.
  163      *
  164      * Some atoms never change size, others change every emit - those have
  165      * the size of 0 here.
  166      *
  167      * NOTE: The framebuffer state is split into these atoms:
  168      * - gpu_flush          (unpipelined regs)
  169      * - aa_state           (unpipelined regs)
  170      * - fb_state           (unpipelined regs)
  171      * - hyperz_state       (unpipelined regs followed by pipelined ones)
  172      * - fb_state_pipelined (pipelined regs)
  173      * The motivation behind this is to be able to emit a strict
  174      * subset of the regs, and to have reasonable register ordering. */
  175     /* SC, GB (unpipelined), RB3D (unpipelined), ZB (unpipelined). */
  176     R300_INIT_ATOM(gpu_flush, 9);
  177     R300_INIT_ATOM(aa_state, 4);
  178     R300_INIT_ATOM(fb_state, 0);
  179     R300_INIT_ATOM(hyperz_state, is_r500 || is_rv350 ? 10 : 8);
  180     /* ZB (unpipelined), SC. */
  181     R300_INIT_ATOM(ztop_state, 2);
  182     /* ZB, FG. */
  183     R300_INIT_ATOM(dsa_state, is_r500 ? 10 : 6);
  184     /* RB3D. */
  185     R300_INIT_ATOM(blend_state, 8);
  186     R300_INIT_ATOM(blend_color_state, is_r500 ? 3 : 2);
  187     /* SC. */
  188     R300_INIT_ATOM(sample_mask, 2);
  189     R300_INIT_ATOM(scissor_state, 3);
  190     /* GB, FG, GA, SU, SC, RB3D. */
  191     R300_INIT_ATOM(invariant_state, 14 + (is_rv350 ? 4 : 0) + (is_r500 ? 4 : 0));
  192     /* VAP. */
  193     R300_INIT_ATOM(viewport_state, 9);
  194     R300_INIT_ATOM(pvs_flush, 2);
  195     R300_INIT_ATOM(vap_invariant_state, is_r500 || !has_tcl ? 11 : 9);
  196     R300_INIT_ATOM(vertex_stream_state, 0);
  197     R300_INIT_ATOM(vs_state, 0);
  198     R300_INIT_ATOM(vs_constants, 0);
  199     R300_INIT_ATOM(clip_state, has_tcl ? 3 + (6 * 4) : 0);
  200     /* VAP, RS, GA, GB, SU, SC. */
  201     R300_INIT_ATOM(rs_block_state, 0);
  202     R300_INIT_ATOM(rs_state, 0);
  203     /* SC, US. */
  204     R300_INIT_ATOM(fb_state_pipelined, 8);
  205     /* US. */
  206     R300_INIT_ATOM(fs, 0);
  207     R300_INIT_ATOM(fs_rc_constant_state, 0);
  208     R300_INIT_ATOM(fs_constants, 0);
  209     /* TX. */
  210     R300_INIT_ATOM(texture_cache_inval, 2);
  211     R300_INIT_ATOM(textures_state, 0);
  212     /* Clear commands */
  213     R300_INIT_ATOM(hiz_clear, r300->screen->caps.hiz_ram > 0 ? 4 : 0);
  214     R300_INIT_ATOM(zmask_clear, r300->screen->caps.zmask_ram > 0 ? 4 : 0);
  215     R300_INIT_ATOM(cmask_clear, 4);
  216     /* ZB (unpipelined), SU. */
  217     R300_INIT_ATOM(query_start, 4);
  218 
  219     /* Replace emission functions for r500. */
  220     if (is_r500) {
  221         r300->fs.emit = r500_emit_fs;
  222         r300->fs_rc_constant_state.emit = r500_emit_fs_rc_constant_state;
  223         r300->fs_constants.emit = r500_emit_fs_constants;
  224     }
  225 
  226     /* Some non-CSO atoms need explicit space to store the state locally. */
  227     R300_ALLOC_ATOM(aa_state, r300_aa_state);
  228     R300_ALLOC_ATOM(blend_color_state, r300_blend_color_state);
  229     R300_ALLOC_ATOM(clip_state, r300_clip_state);
  230     R300_ALLOC_ATOM(hyperz_state, r300_hyperz_state);
  231     R300_ALLOC_ATOM(invariant_state, r300_invariant_state);
  232     R300_ALLOC_ATOM(textures_state, r300_textures_state);
  233     R300_ALLOC_ATOM(vap_invariant_state, r300_vap_invariant_state);
  234     R300_ALLOC_ATOM(viewport_state, r300_viewport_state);
  235     R300_ALLOC_ATOM(ztop_state, r300_ztop_state);
  236     R300_ALLOC_ATOM(fb_state, pipe_framebuffer_state);
  237     R300_ALLOC_ATOM(gpu_flush, pipe_framebuffer_state);
  238     r300->sample_mask.state = malloc(4);
  239     R300_ALLOC_ATOM(scissor_state, pipe_scissor_state);
  240     R300_ALLOC_ATOM(rs_block_state, r300_rs_block);
  241     R300_ALLOC_ATOM(fs_constants, r300_constant_buffer);
  242     R300_ALLOC_ATOM(vs_constants, r300_constant_buffer);
  243     if (!r300->screen->caps.has_tcl) {
  244         R300_ALLOC_ATOM(vertex_stream_state, r300_vertex_stream_state);
  245     }
  246 
  247     /* Some non-CSO atoms don't use the state pointer. */
  248     r300->fb_state_pipelined.allow_null_state = TRUE;
  249     r300->fs_rc_constant_state.allow_null_state = TRUE;
  250     r300->pvs_flush.allow_null_state = TRUE;
  251     r300->query_start.allow_null_state = TRUE;
  252     r300->texture_cache_inval.allow_null_state = TRUE;
  253 
  254     /* Some states must be marked as dirty here to properly set up
  255      * hardware in the first command stream. */
  256     r300_mark_atom_dirty(r300, &r300->invariant_state);
  257     r300_mark_atom_dirty(r300, &r300->pvs_flush);
  258     r300_mark_atom_dirty(r300, &r300->vap_invariant_state);
  259     r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
  260     r300_mark_atom_dirty(r300, &r300->textures_state);
  261 
  262     return TRUE;
  263 }
  264 
  265 /* Not every state tracker calls every driver function before the first draw
  266  * call and we must initialize the command buffers somehow. */
  267 static void r300_init_states(struct pipe_context *pipe)
  268 {
  269     struct r300_context *r300 = r300_context(pipe);
  270     struct pipe_blend_color bc = {{0}};
  271     struct pipe_clip_state cs = {{{0}}};
  272     struct pipe_scissor_state ss = {0};
  273     struct r300_gpu_flush *gpuflush =
  274             (struct r300_gpu_flush*)r300->gpu_flush.state;
  275     struct r300_vap_invariant_state *vap_invariant =
  276             (struct r300_vap_invariant_state*)r300->vap_invariant_state.state;
  277     struct r300_invariant_state *invariant =
  278             (struct r300_invariant_state*)r300->invariant_state.state;
  279 
  280     CB_LOCALS;
  281 
  282     pipe->set_blend_color(pipe, &bc);
  283     pipe->set_clip_state(pipe, &cs);
  284     pipe->set_scissor_states(pipe, 0, 1, &ss);
  285     pipe->set_sample_mask(pipe, ~0);
  286 
  287     /* Initialize the GPU flush. */
  288     {
  289         BEGIN_CB(gpuflush->cb_flush_clean, 6);
  290 
  291         /* Flush and free renderbuffer caches. */
  292         OUT_CB_REG(R300_RB3D_DSTCACHE_CTLSTAT,
  293             R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
  294             R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
  295         OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT,
  296             R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
  297             R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
  298 
  299         /* Wait until the GPU is idle.
  300          * This fixes random pixels sometimes appearing probably caused
  301          * by incomplete rendering. */
  302         OUT_CB_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
  303         END_CB;
  304     }
  305 
  306     /* Initialize the VAP invariant state. */
  307     {
  308         BEGIN_CB(vap_invariant->cb, r300->vap_invariant_state.size);
  309         OUT_CB_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
  310         OUT_CB_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
  311         OUT_CB_32F(1.0);
  312         OUT_CB_32F(1.0);
  313         OUT_CB_32F(1.0);
  314         OUT_CB_32F(1.0);
  315         OUT_CB_REG(R300_VAP_PSC_SGN_NORM_CNTL, R300_SGN_NORM_NO_ZERO);
  316 
  317         if (r300->screen->caps.is_r500) {
  318             OUT_CB_REG(R500_VAP_TEX_TO_COLOR_CNTL, 0);
  319         } else if (!r300->screen->caps.has_tcl) {
  320             /* RSxxx:
  321              * Static VAP setup since r300_emit_vs_state() is never called.
  322              */
  323             OUT_CB_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(10) |
  324                                       R300_PVS_NUM_CNTLRS(5) |
  325                                       R300_PVS_NUM_FPUS(2) |
  326                                       R300_PVS_VF_MAX_VTX_NUM(5));
  327         }
  328         END_CB;
  329     }
  330 
  331     /* Initialize the invariant state. */
  332     {
  333         BEGIN_CB(invariant->cb, r300->invariant_state.size);
  334         OUT_CB_REG(R300_GB_SELECT, 0);
  335         OUT_CB_REG(R300_FG_FOG_BLEND, 0);
  336         OUT_CB_REG(R300_GA_OFFSET, 0);
  337         OUT_CB_REG(R300_SU_TEX_WRAP, 0);
  338         OUT_CB_REG(R300_SU_DEPTH_SCALE, 0x4B7FFFFF);
  339         OUT_CB_REG(R300_SU_DEPTH_OFFSET, 0);
  340         OUT_CB_REG(R300_SC_EDGERULE, 0x2DA49525);
  341 
  342         if (r300->screen->caps.is_rv350) {
  343             OUT_CB_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x01010101);
  344             OUT_CB_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFEFEFEFE);
  345         }
  346 
  347         if (r300->screen->caps.is_r500) {
  348             OUT_CB_REG(R500_GA_COLOR_CONTROL_PS3, 0);
  349             OUT_CB_REG(R500_SU_TEX_WRAP_PS3, 0);
  350         }
  351         END_CB;
  352     }
  353 
  354     /* Initialize the hyperz state. */
  355     {
  356         struct r300_hyperz_state *hyperz =
  357             (struct r300_hyperz_state*)r300->hyperz_state.state;
  358         BEGIN_CB(&hyperz->cb_flush_begin, r300->hyperz_state.size);
  359         OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT,
  360                    R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
  361         OUT_CB_REG(R300_ZB_BW_CNTL, 0);
  362         OUT_CB_REG(R300_ZB_DEPTHCLEARVALUE, 0);
  363         OUT_CB_REG(R300_SC_HYPERZ, R300_SC_HYPERZ_ADJ_2);
  364 
  365         if (r300->screen->caps.is_r500 || r300->screen->caps.is_rv350) {
  366             OUT_CB_REG(R300_GB_Z_PEQ_CONFIG, 0);
  367         }
  368         END_CB;
  369     }
  370 }
  371 
  372 struct pipe_context* r300_create_context(struct pipe_screen* screen,
  373                                          void *priv, unsigned flags)
  374 {
  375     struct r300_context* r300 = CALLOC_STRUCT(r300_context);
  376     struct r300_screen* r300screen = r300_screen(screen);
  377     struct radeon_winsys *rws = r300screen->rws;
  378 
  379     if (!r300)
  380         return NULL;
  381 
  382     r300->rws = rws;
  383     r300->screen = r300screen;
  384 
  385     r300->context.screen = screen;
  386     r300->context.priv = priv;
  387 
  388     r300->context.destroy = r300_destroy_context;
  389 
  390     slab_create_child(&r300->pool_transfers, &r300screen->pool_transfers);
  391 
  392     r300->ctx = rws->ctx_create(rws);
  393     if (!r300->ctx)
  394         goto fail;
  395 
  396     r300->cs = rws->cs_create(r300->ctx, RING_GFX, r300_flush_callback, r300, false);
  397     if (r300->cs == NULL)
  398         goto fail;
  399 
  400     if (!r300screen->caps.has_tcl) {
  401         /* Create a Draw. This is used for SW TCL. */
  402         r300->draw = draw_create(&r300->context);
  403         if (r300->draw == NULL)
  404             goto fail;
  405         /* Enable our renderer. */
  406         draw_set_rasterize_stage(r300->draw, r300_draw_stage(r300));
  407         /* Disable converting points/lines to triangles. */
  408         draw_wide_line_threshold(r300->draw, 10000000.f);
  409         draw_wide_point_threshold(r300->draw, 10000000.f);
  410         draw_wide_point_sprites(r300->draw, FALSE);
  411         draw_enable_line_stipple(r300->draw, TRUE);
  412         draw_enable_point_sprites(r300->draw, FALSE);
  413     }
  414 
  415     if (!r300_setup_atoms(r300))
  416         goto fail;
  417 
  418     r300_init_blit_functions(r300);
  419     r300_init_flush_functions(r300);
  420     r300_init_query_functions(r300);
  421     r300_init_state_functions(r300);
  422     r300_init_resource_functions(r300);
  423     r300_init_render_functions(r300);
  424     r300_init_states(&r300->context);
  425 
  426     r300->context.create_video_codec = vl_create_decoder;
  427     r300->context.create_video_buffer = vl_video_buffer_create;
  428 
  429     r300->uploader = u_upload_create(&r300->context, 128 * 1024,
  430                                      PIPE_BIND_CUSTOM, PIPE_USAGE_STREAM, 0);
  431     r300->context.stream_uploader = u_upload_create(&r300->context, 1024 * 1024,
  432                                                     0, PIPE_USAGE_STREAM, 0);
  433     r300->context.const_uploader = r300->context.stream_uploader;
  434 
  435     r300->blitter = util_blitter_create(&r300->context);
  436     if (r300->blitter == NULL)
  437         goto fail;
  438     r300->blitter->draw_rectangle = r300_blitter_draw_rectangle;
  439 
  440     /* The KIL opcode needs the first texture unit to be enabled
  441      * on r3xx-r4xx. In order to calm down the CS checker, we bind this
  442      * dummy texture there. */
  443     if (!r300->screen->caps.is_r500) {
  444         struct pipe_resource *tex;
  445         struct pipe_resource rtempl = {{0}};
  446         struct pipe_sampler_view vtempl = {{0}};
  447 
  448         rtempl.target = PIPE_TEXTURE_2D;
  449         rtempl.format = PIPE_FORMAT_I8_UNORM;
  450         rtempl.usage = PIPE_USAGE_IMMUTABLE;
  451         rtempl.width0 = 1;
  452         rtempl.height0 = 1;
  453         rtempl.depth0 = 1;
  454         tex = screen->resource_create(screen, &rtempl);
  455 
  456         u_sampler_view_default_template(&vtempl, tex, tex->format);
  457 
  458         r300->texkill_sampler = (struct r300_sampler_view*)
  459             r300->context.create_sampler_view(&r300->context, tex, &vtempl);
  460 
  461         pipe_resource_reference(&tex, NULL);
  462     }
  463 
  464     if (r300screen->caps.has_tcl) {
  465         struct pipe_resource vb;
  466         memset(&vb, 0, sizeof(vb));
  467         vb.target = PIPE_BUFFER;
  468         vb.format = PIPE_FORMAT_R8_UNORM;
  469         vb.usage = PIPE_USAGE_DEFAULT;
  470         vb.width0 = sizeof(float) * 16;
  471         vb.height0 = 1;
  472         vb.depth0 = 1;
  473 
  474         r300->dummy_vb.buffer.resource = screen->resource_create(screen, &vb);
  475         r300->context.set_vertex_buffers(&r300->context, 0, 1, &r300->dummy_vb);
  476     }
  477 
  478     {
  479         struct pipe_depth_stencil_alpha_state dsa;
  480         memset(&dsa, 0, sizeof(dsa));
  481         dsa.depth.writemask = 1;
  482 
  483         r300->dsa_decompress_zmask =
  484             r300->context.create_depth_stencil_alpha_state(&r300->context,
  485                                                            &dsa);
  486     }
  487 
  488     r300->hyperz_time_of_last_flush = os_time_get();
  489 
  490     /* Register allocator state */
  491     rc_init_regalloc_state(&r300->fs_regalloc_state);
  492 
  493     /* Print driver info. */
  494 #ifdef DEBUG
  495     {
  496 #else
  497     if (DBG_ON(r300, DBG_INFO)) {
  498 #endif
  499         fprintf(stderr,
  500                 "r300: DRM version: %d.%d.%d, Name: %s, ID: 0x%04x, GB: %d, Z: %d\n"
  501                 "r300: GART size: %"PRIu64" MB, VRAM size: %"PRIu64" MB\n"
  502                 "r300: AA compression RAM: %s, Z compression RAM: %s, HiZ RAM: %s\n",
  503                 r300->screen->info.drm_major,
  504                 r300->screen->info.drm_minor,
  505                 r300->screen->info.drm_patchlevel,
  506                 screen->get_name(screen),
  507                 r300->screen->info.pci_id,
  508                 r300->screen->info.r300_num_gb_pipes,
  509                 r300->screen->info.r300_num_z_pipes,
  510                 r300->screen->info.gart_size >> 20,
  511                 r300->screen->info.vram_size >> 20,
  512                 "YES", /* XXX really? */
  513                 r300->screen->caps.zmask_ram ? "YES" : "NO",
  514                 r300->screen->caps.hiz_ram ? "YES" : "NO");
  515     }
  516 
  517     return &r300->context;
  518 
  519 fail:
  520     r300_destroy_context(&r300->context);
  521     return NULL;
  522 }