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Member "mesa-20.1.8/src/gallium/drivers/panfrost/pan_assemble.c" (16 Sep 2020, 9742 Bytes) of package /linux/misc/mesa-20.1.8.tar.xz:


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    1 /*
    2  * © Copyright 2018 Alyssa Rosenzweig
    3  *
    4  * Permission is hereby granted, free of charge, to any person obtaining a
    5  * copy of this software and associated documentation files (the "Software"),
    6  * to deal in the Software without restriction, including without limitation
    7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
    8  * and/or sell copies of the Software, and to permit persons to whom the
    9  * Software is furnished to do so, subject to the following conditions:
   10  *
   11  * The above copyright notice and this permission notice (including the next
   12  * paragraph) shall be included in all copies or substantial portions of the
   13  * Software.
   14  *
   15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
   18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
   21  * SOFTWARE.
   22  *
   23  */
   24 
   25 #include <stdio.h>
   26 #include <stdlib.h>
   27 #include <string.h>
   28 #include "pan_bo.h"
   29 #include "pan_context.h"
   30 #include "pan_util.h"
   31 #include "panfrost-quirks.h"
   32 
   33 #include "compiler/nir/nir.h"
   34 #include "nir/tgsi_to_nir.h"
   35 #include "midgard/midgard_compile.h"
   36 #include "bifrost/bifrost_compile.h"
   37 #include "util/u_dynarray.h"
   38 
   39 #include "tgsi/tgsi_dump.h"
   40 
   41 static unsigned
   42 pan_format_from_nir_base(nir_alu_type base)
   43 {
   44         switch (base) {
   45         case nir_type_int:
   46                 return MALI_FORMAT_SINT;
   47         case nir_type_uint:
   48         case nir_type_bool:
   49                 return MALI_FORMAT_UINT;
   50         case nir_type_float:
   51                 return MALI_CHANNEL_FLOAT;
   52         default:
   53                 unreachable("Invalid base");
   54         }
   55 }
   56 
   57 static unsigned
   58 pan_format_from_nir_size(nir_alu_type base, unsigned size)
   59 {
   60         if (base == nir_type_float) {
   61                 switch (size) {
   62                 case 16: return MALI_FORMAT_SINT;
   63                 case 32: return MALI_FORMAT_UNORM;
   64                 default:
   65                         unreachable("Invalid float size for format");
   66                 }
   67         } else {
   68                 switch (size) {
   69                 case 1:
   70                 case 8:  return MALI_CHANNEL_8;
   71                 case 16: return MALI_CHANNEL_16;
   72                 case 32: return MALI_CHANNEL_32;
   73                 default:
   74                          unreachable("Invalid int size for format");
   75                 }
   76         }
   77 }
   78 
   79 static enum mali_format
   80 pan_format_from_glsl(const struct glsl_type *type)
   81 {
   82         enum glsl_base_type glsl_base = glsl_get_base_type(glsl_without_array(type));
   83         nir_alu_type t = nir_get_nir_type_for_glsl_base_type(glsl_base);
   84 
   85         unsigned base = nir_alu_type_get_base_type(t);
   86         unsigned size = nir_alu_type_get_type_size(t);
   87 
   88         return pan_format_from_nir_base(base) |
   89                 pan_format_from_nir_size(base, size) |
   90                 MALI_NR_CHANNELS(4);
   91 }
   92 
   93 void
   94 panfrost_shader_compile(struct panfrost_context *ctx,
   95                         enum pipe_shader_ir ir_type,
   96                         const void *ir,
   97                         gl_shader_stage stage,
   98                         struct panfrost_shader_state *state,
   99                         uint64_t *outputs_written)
  100 {
  101         struct panfrost_device *dev = pan_device(ctx->base.screen);
  102         uint8_t *dst;
  103 
  104         nir_shader *s;
  105 
  106         if (ir_type == PIPE_SHADER_IR_NIR) {
  107                 s = nir_shader_clone(NULL, ir);
  108         } else {
  109                 assert (ir_type == PIPE_SHADER_IR_TGSI);
  110                 s = tgsi_to_nir(ir, ctx->base.screen);
  111         }
  112 
  113         s->info.stage = stage;
  114 
  115         /* Call out to Midgard compiler given the above NIR */
  116 
  117         panfrost_program program = {
  118                 .alpha_ref = state->alpha_state.ref_value
  119         };
  120 
  121         if (dev->quirks & IS_BIFROST) {
  122                 bifrost_compile_shader_nir(s, &program, dev->gpu_id);
  123         } else {
  124                 midgard_compile_shader_nir(s, &program, false, 0, dev->gpu_id,
  125                                 pan_debug & PAN_DBG_PRECOMPILE);
  126         }
  127 
  128         /* Prepare the compiled binary for upload */
  129         int size = program.compiled.size;
  130         dst = program.compiled.data;
  131 
  132         /* Upload the shader. The lookahead tag is ORed on as a tagged pointer.
  133          * I bet someone just thought that would be a cute pun. At least,
  134          * that's how I'd do it. */
  135 
  136         if (size) {
  137                 state->bo = pan_bo_create(dev, size, PAN_BO_EXECUTE);
  138                 memcpy(state->bo->cpu, dst, size);
  139         }
  140 
  141         if (!(dev->quirks & IS_BIFROST)) {
  142                 /* If size = 0, no shader. Use dummy tag to avoid
  143                  * INSTR_INVALID_ENC */
  144                 state->first_tag = size ? program.first_tag : 1;
  145         }
  146 
  147         util_dynarray_fini(&program.compiled);
  148 
  149         state->sysval_count = program.sysval_count;
  150         memcpy(state->sysval, program.sysvals, sizeof(state->sysval[0]) * state->sysval_count);
  151 
  152         bool vertex_id = s->info.system_values_read & (1 << SYSTEM_VALUE_VERTEX_ID);
  153         bool instance_id = s->info.system_values_read & (1 << SYSTEM_VALUE_INSTANCE_ID);
  154 
  155         switch (stage) {
  156         case MESA_SHADER_VERTEX:
  157                 state->attribute_count = util_bitcount64(s->info.inputs_read);
  158                 state->varying_count = util_bitcount64(s->info.outputs_written);
  159 
  160                 if (vertex_id)
  161                         state->attribute_count = MAX2(state->attribute_count, PAN_VERTEX_ID + 1);
  162 
  163                 if (instance_id)
  164                         state->attribute_count = MAX2(state->attribute_count, PAN_INSTANCE_ID + 1);
  165 
  166                 break;
  167         case MESA_SHADER_FRAGMENT:
  168                 state->attribute_count = 0;
  169                 state->varying_count = util_bitcount64(s->info.inputs_read);
  170                 if (s->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
  171                         state->writes_depth = true;
  172                 if (s->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL))
  173                         state->writes_stencil = true;
  174                 break;
  175         case MESA_SHADER_COMPUTE:
  176                 /* TODO: images */
  177                 state->attribute_count = 0;
  178                 state->varying_count = 0;
  179                 state->shared_size = s->info.cs.shared_size;
  180                 break;
  181         default:
  182                 unreachable("Unknown shader state");
  183         }
  184 
  185         state->can_discard = s->info.fs.uses_discard;
  186         state->writes_point_size = program.writes_point_size;
  187         state->reads_point_coord = false;
  188         state->helper_invocations = s->info.fs.needs_helper_invocations;
  189         state->stack_size = program.tls_size;
  190 
  191         if (outputs_written)
  192                 *outputs_written = s->info.outputs_written;
  193 
  194         /* Separate as primary uniform count is truncated. Sysvals are prefix
  195          * uniforms */
  196         state->uniform_count = s->num_uniforms + program.sysval_count;
  197         state->uniform_cutoff = program.uniform_cutoff;
  198         state->work_reg_count = program.work_register_count;
  199 
  200         unsigned default_vec1_swizzle = panfrost_get_default_swizzle(1);
  201         unsigned default_vec2_swizzle = panfrost_get_default_swizzle(2);
  202         unsigned default_vec4_swizzle = panfrost_get_default_swizzle(4);
  203 
  204         /* Record the varying mapping for the command stream's bookkeeping */
  205 
  206         unsigned p_varyings[32];
  207         enum mali_format p_varying_type[32];
  208 
  209         struct exec_list *l_varyings =
  210                         stage == MESA_SHADER_VERTEX ? &s->outputs : &s->inputs;
  211 
  212         nir_foreach_variable(var, l_varyings) {
  213                 unsigned loc = var->data.driver_location;
  214                 unsigned sz = glsl_count_attribute_slots(var->type, FALSE);
  215 
  216                 for (int c = 0; c < sz; ++c) {
  217                         p_varyings[loc + c] = var->data.location + c;
  218                         p_varying_type[loc + c] = pan_format_from_glsl(var->type);
  219                 }
  220         }
  221 
  222         /* Iterate the varyings and emit the corresponding descriptor */
  223         for (unsigned i = 0; i < state->varying_count; ++i) {
  224                 unsigned location = p_varyings[i];
  225 
  226                 /* Default to a vec4 varying */
  227                 struct mali_attr_meta v = {
  228                         .format = p_varying_type[i],
  229                         .swizzle = default_vec4_swizzle,
  230                         .unknown1 = 0x2,
  231                 };
  232 
  233                 /* Check for special cases, otherwise assume general varying */
  234 
  235                 if (location == VARYING_SLOT_POS) {
  236                         if (stage == MESA_SHADER_FRAGMENT)
  237                                 state->reads_frag_coord = true;
  238                         else
  239                                 v.format = MALI_VARYING_POS;
  240                 } else if (location == VARYING_SLOT_PSIZ) {
  241                         v.format = MALI_R16F;
  242                         v.swizzle = default_vec1_swizzle;
  243 
  244                         state->writes_point_size = true;
  245                 } else if (location == VARYING_SLOT_PNTC) {
  246                         v.format = MALI_RG16F;
  247                         v.swizzle = default_vec2_swizzle;
  248 
  249                         state->reads_point_coord = true;
  250                 } else if (location == VARYING_SLOT_FACE) {
  251                         v.format = MALI_R32I;
  252                         v.swizzle = default_vec1_swizzle;
  253 
  254                         state->reads_face = true;
  255                 }
  256 
  257                 state->varyings[i] = v;
  258                 state->varyings_loc[i] = location;
  259         }
  260 }