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Member "mesa-20.1.8/src/gallium/drivers/lima/ir/gp/codegen.h" (16 Sep 2020, 6535 Bytes) of package /linux/misc/mesa-20.1.8.tar.xz:


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    1 /*
    2  * Copyright (c) 2017 Lima Project
    3  * Copyright (c) 2013 Ben Brewer (ben.brewer@codethink.co.uk)
    4  * Copyright (c) 2013 Connor Abbott (connor@abbott.cx)
    5  *
    6  * Permission is hereby granted, free of charge, to any person obtaining a
    7  * copy of this software and associated documentation files (the "Software"),
    8  * to deal in the Software without restriction, including without limitation
    9  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   10  * and/or sell copies of the Software, and to permit persons to whom the
   11  * Software is furnished to do so, subject to the following conditions:
   12  *
   13  * The above copyright notice and this permission notice (including the
   14  * next paragraph) shall be included in all copies or substantial portions
   15  * of the Software.
   16  *
   17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
   20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
   22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
   23  * DEALINGS IN THE SOFTWARE.
   24  *
   25  */
   26 
   27 #ifndef LIMA_IR_GP_CODEGEN_H
   28 #define LIMA_IR_GP_CODEGEN_H
   29 
   30 typedef enum {
   31    gpir_codegen_src_attrib_x     =  0,
   32    gpir_codegen_src_attrib_y     =  1,
   33    gpir_codegen_src_attrib_z     =  2,
   34    gpir_codegen_src_attrib_w     =  3,
   35    gpir_codegen_src_register_x   =  4,
   36    gpir_codegen_src_register_y   =  5,
   37    gpir_codegen_src_register_z   =  6,
   38    gpir_codegen_src_register_w   =  7,
   39    gpir_codegen_src_unknown_0    =  8,
   40    gpir_codegen_src_unknown_1    =  9,
   41    gpir_codegen_src_unknown_2    = 10,
   42    gpir_codegen_src_unknown_3    = 11,
   43    gpir_codegen_src_load_x       = 12,
   44    gpir_codegen_src_load_y       = 13,
   45    gpir_codegen_src_load_z       = 14,
   46    gpir_codegen_src_load_w       = 15,
   47    gpir_codegen_src_p1_acc_0     = 16,
   48    gpir_codegen_src_p1_acc_1     = 17,
   49    gpir_codegen_src_p1_mul_0     = 18,
   50    gpir_codegen_src_p1_mul_1     = 19,
   51    gpir_codegen_src_p1_pass      = 20,
   52    gpir_codegen_src_unused       = 21,
   53    gpir_codegen_src_ident        = 22,
   54    gpir_codegen_src_p1_complex   = 22,
   55    gpir_codegen_src_p2_pass      = 23,
   56    gpir_codegen_src_p2_acc_0     = 24,
   57    gpir_codegen_src_p2_acc_1     = 25,
   58    gpir_codegen_src_p2_mul_0     = 26,
   59    gpir_codegen_src_p2_mul_1     = 27,
   60    gpir_codegen_src_p1_attrib_x  = 28,
   61    gpir_codegen_src_p1_attrib_y  = 29,
   62    gpir_codegen_src_p1_attrib_z  = 30,
   63    gpir_codegen_src_p1_attrib_w  = 31,
   64 } gpir_codegen_src;
   65 
   66 typedef enum {
   67    gpir_codegen_load_off_ld_addr_0 = 1,
   68    gpir_codegen_load_off_ld_addr_1 = 2,
   69    gpir_codegen_load_off_ld_addr_2 = 3,
   70    gpir_codegen_load_off_none      = 7,
   71 } gpir_codegen_load_off;
   72 
   73 typedef enum {
   74    gpir_codegen_store_src_acc_0   = 0,
   75    gpir_codegen_store_src_acc_1   = 1,
   76    gpir_codegen_store_src_mul_0   = 2,
   77    gpir_codegen_store_src_mul_1   = 3,
   78    gpir_codegen_store_src_pass    = 4,
   79    gpir_codegen_store_src_unknown = 5,
   80    gpir_codegen_store_src_complex = 6,
   81    gpir_codegen_store_src_none    = 7,
   82 } gpir_codegen_store_src;
   83 
   84 typedef enum {
   85    gpir_codegen_acc_op_add   = 0,
   86    gpir_codegen_acc_op_floor = 1,
   87    gpir_codegen_acc_op_sign  = 2,
   88    gpir_codegen_acc_op_ge    = 4,
   89    gpir_codegen_acc_op_lt    = 5,
   90    gpir_codegen_acc_op_min   = 6,
   91    gpir_codegen_acc_op_max   = 7,
   92 } gpir_codegen_acc_op;
   93 
   94 typedef enum {
   95    gpir_codegen_complex_op_nop   = 0,
   96    gpir_codegen_complex_op_exp2  = 2,
   97    gpir_codegen_complex_op_log2  = 3,
   98    gpir_codegen_complex_op_rsqrt = 4,
   99    gpir_codegen_complex_op_rcp   = 5,
  100    gpir_codegen_complex_op_pass  = 9,
  101    gpir_codegen_complex_op_temp_store_addr  = 12,
  102    gpir_codegen_complex_op_temp_load_addr_0 = 13,
  103    gpir_codegen_complex_op_temp_load_addr_1 = 14,
  104    gpir_codegen_complex_op_temp_load_addr_2 = 15,
  105 } gpir_codegen_complex_op;
  106 
  107 typedef enum {
  108    gpir_codegen_mul_op_mul  = 0,
  109    gpir_codegen_mul_op_complex1 = 1,
  110    gpir_codegen_mul_op_complex2 = 3,
  111    gpir_codegen_mul_op_select   = 4,
  112 } gpir_codegen_mul_op;
  113 
  114 typedef enum {
  115    gpir_codegen_pass_op_pass     = 2,
  116    gpir_codegen_pass_op_preexp2  = 4,
  117    gpir_codegen_pass_op_postlog2 = 5,
  118    gpir_codegen_pass_op_clamp    = 6,
  119 } gpir_codegen_pass_op;
  120 
  121 
  122 typedef struct __attribute__((__packed__)) {
  123    gpir_codegen_src        mul0_src0           : 5;
  124    gpir_codegen_src        mul0_src1           : 5;
  125    gpir_codegen_src        mul1_src0           : 5;
  126    gpir_codegen_src        mul1_src1           : 5;
  127    bool                    mul0_neg            : 1;
  128    bool                    mul1_neg            : 1;
  129    gpir_codegen_src        acc0_src0           : 5;
  130    gpir_codegen_src        acc0_src1           : 5;
  131    gpir_codegen_src        acc1_src0           : 5;
  132    gpir_codegen_src        acc1_src1           : 5;
  133    bool                    acc0_src0_neg       : 1;
  134    bool                    acc0_src1_neg       : 1;
  135    bool                    acc1_src0_neg       : 1;
  136    bool                    acc1_src1_neg       : 1;
  137    unsigned                load_addr           : 9;
  138    gpir_codegen_load_off   load_offset         : 3;
  139    unsigned                register0_addr      : 4;
  140    bool                    register0_attribute : 1;
  141    unsigned                register1_addr      : 4;
  142    bool                    store0_temporary    : 1;
  143    bool                    store1_temporary    : 1;
  144    bool                    branch              : 1;
  145    bool                    branch_target_lo    : 1;
  146    gpir_codegen_store_src  store0_src_x        : 3;
  147    gpir_codegen_store_src  store0_src_y        : 3;
  148    gpir_codegen_store_src  store1_src_z        : 3;
  149    gpir_codegen_store_src  store1_src_w        : 3;
  150    gpir_codegen_acc_op     acc_op              : 3;
  151    gpir_codegen_complex_op complex_op          : 4;
  152    unsigned                store0_addr         : 4;
  153    bool                    store0_varying      : 1;
  154    unsigned                store1_addr         : 4;
  155    bool                    store1_varying      : 1;
  156    gpir_codegen_mul_op     mul_op              : 3;
  157    gpir_codegen_pass_op    pass_op             : 3;
  158    gpir_codegen_src        complex_src         : 5;
  159    gpir_codegen_src        pass_src            : 5;
  160    unsigned                unknown_1           : 4; /* 12: tmp_st, 13: branch */
  161    unsigned                branch_target       : 8;
  162 } gpir_codegen_instr;
  163 
  164 void gpir_disassemble_program(gpir_codegen_instr *code, unsigned num_instr);
  165 
  166 #endif