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    1 /*
    2  * Copyright © 2017 Intel Corporation
    3  *
    4  * Permission is hereby granted, free of charge, to any person obtaining a
    5  * copy of this software and associated documentation files (the "Software"),
    6  * to deal in the Software without restriction, including without limitation
    7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
    8  * and/or sell copies of the Software, and to permit persons to whom the
    9  * Software is furnished to do so, subject to the following conditions:
   10  *
   11  * The above copyright notice and this permission notice (including the next
   12  * paragraph) shall be included in all copies or substantial portions of the
   13  * Software.
   14  *
   15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
   18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
   20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
   21  * IN THE SOFTWARE.
   22  */
   23 
   24 #ifndef IRIS_BUFMGR_H
   25 #define IRIS_BUFMGR_H
   26 
   27 #include <stdbool.h>
   28 #include <stdint.h>
   29 #include <stdio.h>
   30 #include <sys/types.h>
   31 #include "c11/threads.h"
   32 #include "util/macros.h"
   33 #include "util/u_atomic.h"
   34 #include "util/list.h"
   35 #include "pipe/p_defines.h"
   36 
   37 struct iris_batch;
   38 struct gen_device_info;
   39 struct pipe_debug_callback;
   40 
   41 /**
   42  * Memory zones.  When allocating a buffer, you can request that it is
   43  * placed into a specific region of the virtual address space (PPGTT).
   44  *
   45  * Most buffers can go anywhere (IRIS_MEMZONE_OTHER).  Some buffers are
   46  * accessed via an offset from a base address.  STATE_BASE_ADDRESS has
   47  * a maximum 4GB size for each region, so we need to restrict those
   48  * buffers to be within 4GB of the base.  Each memory zone corresponds
   49  * to a particular base address.
   50  *
   51  * We lay out the virtual address space as follows:
   52  *
   53  * - [0,   4K): Nothing            (empty page for null address)
   54  * - [4K,  4G): Shaders            (Instruction Base Address)
   55  * - [4G,  8G): Surfaces & Binders (Surface State Base Address, Bindless ...)
   56  * - [8G, 12G): Dynamic            (Dynamic State Base Address)
   57  * - [12G, *):  Other              (everything else in the full 48-bit VMA)
   58  *
   59  * A special buffer for border color lives at the start of the dynamic state
   60  * memory zone.  This unfortunately has to be handled specially because the
   61  * SAMPLER_STATE "Indirect State Pointer" field is only a 24-bit pointer.
   62  *
   63  * Each GL context uses a separate GEM context, which technically gives them
   64  * each a separate VMA.  However, we assign address globally, so buffers will
   65  * have the same address in all GEM contexts.  This lets us have a single BO
   66  * field for the address, which is easy and cheap.
   67  */
   68 enum iris_memory_zone {
   69    IRIS_MEMZONE_SHADER,
   70    IRIS_MEMZONE_BINDER,
   71    IRIS_MEMZONE_SURFACE,
   72    IRIS_MEMZONE_DYNAMIC,
   73    IRIS_MEMZONE_OTHER,
   74 
   75    IRIS_MEMZONE_BORDER_COLOR_POOL,
   76 };
   77 
   78 /* Intentionally exclude single buffer "zones" */
   79 #define IRIS_MEMZONE_COUNT (IRIS_MEMZONE_OTHER + 1)
   80 
   81 #define IRIS_BINDER_SIZE (64 * 1024)
   82 #define IRIS_MAX_BINDERS 100
   83 
   84 #define IRIS_MEMZONE_SHADER_START     (0ull * (1ull << 32))
   85 #define IRIS_MEMZONE_BINDER_START     (1ull * (1ull << 32))
   86 #define IRIS_MEMZONE_SURFACE_START    (IRIS_MEMZONE_BINDER_START + IRIS_MAX_BINDERS * IRIS_BINDER_SIZE)
   87 #define IRIS_MEMZONE_DYNAMIC_START    (2ull * (1ull << 32))
   88 #define IRIS_MEMZONE_OTHER_START      (3ull * (1ull << 32))
   89 
   90 #define IRIS_BORDER_COLOR_POOL_ADDRESS IRIS_MEMZONE_DYNAMIC_START
   91 #define IRIS_BORDER_COLOR_POOL_SIZE (64 * 1024)
   92 
   93 struct iris_bo {
   94    /**
   95     * Size in bytes of the buffer object.
   96     *
   97     * The size may be larger than the size originally requested for the
   98     * allocation, such as being aligned to page size.
   99     */
  100    uint64_t size;
  101 
  102    /** Buffer manager context associated with this buffer object */
  103    struct iris_bufmgr *bufmgr;
  104 
  105    /** Pre-computed hash using _mesa_hash_pointer for cache tracking sets */
  106    uint32_t hash;
  107 
  108    /** The GEM handle for this buffer object. */
  109    uint32_t gem_handle;
  110 
  111    /**
  112     * Virtual address of the buffer inside the PPGTT (Per-Process Graphics
  113     * Translation Table).
  114     *
  115     * Although each hardware context has its own VMA, we assign BO's to the
  116     * same address in all contexts, for simplicity.
  117     */
  118    uint64_t gtt_offset;
  119 
  120    /**
  121     * If non-zero, then this bo has an aux-map translation to this address.
  122     */
  123    uint64_t aux_map_address;
  124 
  125    /**
  126     * The validation list index for this buffer, or -1 when not in a batch.
  127     * Note that a single buffer may be in multiple batches (contexts), and
  128     * this is a global field, which refers to the last batch using the BO.
  129     * It should not be considered authoritative, but can be used to avoid a
  130     * linear walk of the validation list in the common case by guessing that
  131     * exec_bos[bo->index] == bo and confirming whether that's the case.
  132     *
  133     * XXX: this is not ideal now that we have more than one batch per context,
  134     * XXX: as the index will flop back and forth between the render index and
  135     * XXX: compute index...
  136     */
  137    unsigned index;
  138 
  139    int refcount;
  140    const char *name;
  141 
  142    uint64_t kflags;
  143 
  144    /**
  145     * Kenel-assigned global name for this object
  146     *
  147     * List contains both flink named and prime fd'd objects
  148     */
  149    unsigned global_name;
  150 
  151    /**
  152     * Current tiling mode
  153     */
  154    uint32_t tiling_mode;
  155    uint32_t swizzle_mode;
  156    uint32_t stride;
  157 
  158    time_t free_time;
  159 
  160    /** Mapped address for the buffer, saved across map/unmap cycles */
  161    void *map_cpu;
  162    /** GTT virtual address for the buffer, saved across map/unmap cycles */
  163    void *map_gtt;
  164    /** WC CPU address for the buffer, saved across map/unmap cycles */
  165    void *map_wc;
  166 
  167    /** BO cache list */
  168    struct list_head head;
  169 
  170    /** List of GEM handle exports of this buffer (bo_export) */
  171    struct list_head exports;
  172 
  173    /**
  174     * Boolean of whether the GPU is definitely not accessing the buffer.
  175     *
  176     * This is only valid when reusable, since non-reusable
  177     * buffers are those that have been shared with other
  178     * processes, so we don't know their state.
  179     */
  180    bool idle;
  181 
  182    /**
  183     * Boolean of whether this buffer can be re-used
  184     */
  185    bool reusable;
  186 
  187    /**
  188     * Boolean of whether this buffer has been shared with an external client.
  189     */
  190    bool external;
  191 
  192    /**
  193     * Boolean of whether this buffer is cache coherent
  194     */
  195    bool cache_coherent;
  196 
  197    /**
  198     * Boolean of whether this buffer points into user memory
  199     */
  200    bool userptr;
  201 };
  202 
  203 #define BO_ALLOC_ZEROED     (1<<0)
  204 #define BO_ALLOC_COHERENT   (1<<1)
  205 
  206 /**
  207  * Allocate a buffer object.
  208  *
  209  * Buffer objects are not necessarily initially mapped into CPU virtual
  210  * address space or graphics device aperture.  They must be mapped
  211  * using iris_bo_map() to be used by the CPU.
  212  */
  213 struct iris_bo *iris_bo_alloc(struct iris_bufmgr *bufmgr,
  214                               const char *name,
  215                               uint64_t size,
  216                               enum iris_memory_zone memzone);
  217 
  218 /**
  219  * Allocate a tiled buffer object.
  220  *
  221  * Alignment for tiled objects is set automatically; the 'flags'
  222  * argument provides a hint about how the object will be used initially.
  223  *
  224  * Valid tiling formats are:
  225  *  I915_TILING_NONE
  226  *  I915_TILING_X
  227  *  I915_TILING_Y
  228  */
  229 struct iris_bo *iris_bo_alloc_tiled(struct iris_bufmgr *bufmgr,
  230                                     const char *name,
  231                                     uint64_t size,
  232                                     uint32_t alignment,
  233                                     enum iris_memory_zone memzone,
  234                                     uint32_t tiling_mode,
  235                                     uint32_t pitch,
  236                                     unsigned flags);
  237 
  238 struct iris_bo *
  239 iris_bo_create_userptr(struct iris_bufmgr *bufmgr, const char *name,
  240                        void *ptr, size_t size,
  241                        enum iris_memory_zone memzone);
  242 
  243 /** Takes a reference on a buffer object */
  244 static inline void
  245 iris_bo_reference(struct iris_bo *bo)
  246 {
  247    p_atomic_inc(&bo->refcount);
  248 }
  249 
  250 /**
  251  * Releases a reference on a buffer object, freeing the data if
  252  * no references remain.
  253  */
  254 void iris_bo_unreference(struct iris_bo *bo);
  255 
  256 #define MAP_READ          PIPE_TRANSFER_READ
  257 #define MAP_WRITE         PIPE_TRANSFER_WRITE
  258 #define MAP_ASYNC         PIPE_TRANSFER_UNSYNCHRONIZED
  259 #define MAP_PERSISTENT    PIPE_TRANSFER_PERSISTENT
  260 #define MAP_COHERENT      PIPE_TRANSFER_COHERENT
  261 /* internal */
  262 #define MAP_INTERNAL_MASK (0xffu << 24)
  263 #define MAP_RAW           (0x01 << 24)
  264 
  265 #define MAP_FLAGS         (MAP_READ | MAP_WRITE | MAP_ASYNC | \
  266                            MAP_PERSISTENT | MAP_COHERENT | MAP_INTERNAL_MASK)
  267 
  268 /**
  269  * Maps the buffer into userspace.
  270  *
  271  * This function will block waiting for any existing execution on the
  272  * buffer to complete, first.  The resulting mapping is returned.
  273  */
  274 MUST_CHECK void *iris_bo_map(struct pipe_debug_callback *dbg,
  275                              struct iris_bo *bo, unsigned flags);
  276 
  277 /**
  278  * Reduces the refcount on the userspace mapping of the buffer
  279  * object.
  280  */
  281 static inline int iris_bo_unmap(struct iris_bo *bo) { return 0; }
  282 
  283 /**
  284  * Waits for rendering to an object by the GPU to have completed.
  285  *
  286  * This is not required for any access to the BO by bo_map,
  287  * bo_subdata, etc.  It is merely a way for the driver to implement
  288  * glFinish.
  289  */
  290 void iris_bo_wait_rendering(struct iris_bo *bo);
  291 
  292 
  293 /**
  294  * Unref a buffer manager instance.
  295  */
  296 void iris_bufmgr_unref(struct iris_bufmgr *bufmgr);
  297 
  298 /**
  299  * Get the current tiling (and resulting swizzling) mode for the bo.
  300  *
  301  * \param buf Buffer to get tiling mode for
  302  * \param tiling_mode returned tiling mode
  303  * \param swizzle_mode returned swizzling mode
  304  */
  305 int iris_bo_get_tiling(struct iris_bo *bo, uint32_t *tiling_mode,
  306                       uint32_t *swizzle_mode);
  307 
  308 /**
  309  * Create a visible name for a buffer which can be used by other apps
  310  *
  311  * \param buf Buffer to create a name for
  312  * \param name Returned name
  313  */
  314 int iris_bo_flink(struct iris_bo *bo, uint32_t *name);
  315 
  316 /**
  317  * Make a BO externally accessible.
  318  *
  319  * \param bo Buffer to make external
  320  */
  321 void iris_bo_make_external(struct iris_bo *bo);
  322 
  323 /**
  324  * Returns 1 if mapping the buffer for write could cause the process
  325  * to block, due to the object being active in the GPU.
  326  */
  327 int iris_bo_busy(struct iris_bo *bo);
  328 
  329 /**
  330  * Specify the volatility of the buffer.
  331  * \param bo Buffer to create a name for
  332  * \param madv The purgeable status
  333  *
  334  * Use I915_MADV_DONTNEED to mark the buffer as purgeable, and it will be
  335  * reclaimed under memory pressure. If you subsequently require the buffer,
  336  * then you must pass I915_MADV_WILLNEED to mark the buffer as required.
  337  *
  338  * Returns 1 if the buffer was retained, or 0 if it was discarded whilst
  339  * marked as I915_MADV_DONTNEED.
  340  */
  341 int iris_bo_madvise(struct iris_bo *bo, int madv);
  342 
  343 /* drm_bacon_bufmgr_gem.c */
  344 struct iris_bufmgr *iris_bufmgr_get_for_fd(struct gen_device_info *devinfo, int fd,
  345                                            bool bo_reuse);
  346 int iris_bufmgr_get_fd(struct iris_bufmgr *bufmgr);
  347 
  348 struct iris_bo *iris_bo_gem_create_from_name(struct iris_bufmgr *bufmgr,
  349                                              const char *name,
  350                                              unsigned handle);
  351 
  352 void* iris_bufmgr_get_aux_map_context(struct iris_bufmgr *bufmgr);
  353 
  354 int iris_bo_wait(struct iris_bo *bo, int64_t timeout_ns);
  355 
  356 uint32_t iris_create_hw_context(struct iris_bufmgr *bufmgr);
  357 uint32_t iris_clone_hw_context(struct iris_bufmgr *bufmgr, uint32_t ctx_id);
  358 
  359 #define IRIS_CONTEXT_LOW_PRIORITY    ((I915_CONTEXT_MIN_USER_PRIORITY-1)/2)
  360 #define IRIS_CONTEXT_MEDIUM_PRIORITY (I915_CONTEXT_DEFAULT_PRIORITY)
  361 #define IRIS_CONTEXT_HIGH_PRIORITY   ((I915_CONTEXT_MAX_USER_PRIORITY+1)/2)
  362 
  363 int iris_hw_context_set_priority(struct iris_bufmgr *bufmgr,
  364                                  uint32_t ctx_id, int priority);
  365 
  366 void iris_destroy_hw_context(struct iris_bufmgr *bufmgr, uint32_t ctx_id);
  367 
  368 int iris_bo_export_dmabuf(struct iris_bo *bo, int *prime_fd);
  369 struct iris_bo *iris_bo_import_dmabuf(struct iris_bufmgr *bufmgr, int prime_fd,
  370                                       uint32_t tiling, uint32_t stride);
  371 
  372 /**
  373  * Exports a bo as a GEM handle into a given DRM file descriptor
  374  * \param bo Buffer to export
  375  * \param drm_fd File descriptor where the new handle is created
  376  * \param out_handle Pointer to store the new handle
  377  *
  378  * Returns 0 if the buffer was successfully exported, a non zero error code
  379  * otherwise.
  380  */
  381 int iris_bo_export_gem_handle_for_device(struct iris_bo *bo, int drm_fd,
  382                                          uint32_t *out_handle);
  383 
  384 uint32_t iris_bo_export_gem_handle(struct iris_bo *bo);
  385 
  386 int iris_reg_read(struct iris_bufmgr *bufmgr, uint32_t offset, uint64_t *out);
  387 
  388 int drm_ioctl(int fd, unsigned long request, void *arg);
  389 
  390 /**
  391  * Returns the BO's address relative to the appropriate base address.
  392  *
  393  * All of our base addresses are programmed to the start of a 4GB region,
  394  * so simply returning the bottom 32 bits of the BO address will give us
  395  * the offset from whatever base address corresponds to that memory region.
  396  */
  397 static inline uint32_t
  398 iris_bo_offset_from_base_address(struct iris_bo *bo)
  399 {
  400    /* This only works for buffers in the memory zones corresponding to a
  401     * base address - the top, unbounded memory zone doesn't have a base.
  402     */
  403    assert(bo->gtt_offset < IRIS_MEMZONE_OTHER_START);
  404    return bo->gtt_offset;
  405 }
  406 
  407 enum iris_memory_zone iris_memzone_for_address(uint64_t address);
  408 
  409 #endif /* IRIS_BUFMGR_H */