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Member "mesa-20.1.8/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c" (16 Sep 2020, 47073 Bytes) of package /linux/misc/mesa-20.1.8.tar.xz:


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    1 /*
    2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
    3  * Copyright © 2018 Google, Inc.
    4  *
    5  * Permission is hereby granted, free of charge, to any person obtaining a
    6  * copy of this software and associated documentation files (the "Software"),
    7  * to deal in the Software without restriction, including without limitation
    8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
    9  * and/or sell copies of the Software, and to permit persons to whom the
   10  * Software is furnished to do so, subject to the following conditions:
   11  *
   12  * The above copyright notice and this permission notice (including the next
   13  * paragraph) shall be included in all copies or substantial portions of the
   14  * Software.
   15  *
   16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
   19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
   22  * SOFTWARE.
   23  *
   24  * Authors:
   25  *    Rob Clark <robclark@freedesktop.org>
   26  */
   27 
   28 #include <stdio.h>
   29 
   30 #include "pipe/p_state.h"
   31 #include "util/u_string.h"
   32 #include "util/u_memory.h"
   33 #include "util/u_inlines.h"
   34 #include "util/format/u_format.h"
   35 
   36 #include "freedreno_draw.h"
   37 #include "freedreno_log.h"
   38 #include "freedreno_state.h"
   39 #include "freedreno_resource.h"
   40 
   41 #include "fd6_blitter.h"
   42 #include "fd6_gmem.h"
   43 #include "fd6_context.h"
   44 #include "fd6_draw.h"
   45 #include "fd6_emit.h"
   46 #include "fd6_program.h"
   47 #include "fd6_format.h"
   48 #include "fd6_resource.h"
   49 #include "fd6_zsa.h"
   50 #include "fd6_pack.h"
   51 
   52 /**
   53  * Emits the flags registers, suitable for RB_MRT_FLAG_BUFFER,
   54  * RB_DEPTH_FLAG_BUFFER, SP_PS_2D_SRC_FLAGS, and RB_BLIT_FLAG_DST.
   55  */
   56 void
   57 fd6_emit_flag_reference(struct fd_ringbuffer *ring, struct fd_resource *rsc,
   58         int level, int layer)
   59 {
   60     if (fd_resource_ubwc_enabled(rsc, level)) {
   61         OUT_RELOCW(ring, rsc->bo, fd_resource_ubwc_offset(rsc, level, layer), 0, 0);
   62         OUT_RING(ring,
   63                 A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->layout.ubwc_slices[level].pitch) |
   64                 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->layout.ubwc_layer_size >> 2));
   65     } else {
   66         OUT_RING(ring, 0x00000000);    /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
   67         OUT_RING(ring, 0x00000000);    /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
   68         OUT_RING(ring, 0x00000000);
   69     }
   70 }
   71 
   72 static void
   73 emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
   74         const struct fd_gmem_stateobj *gmem)
   75 {
   76     unsigned char mrt_comp[A6XX_MAX_RENDER_TARGETS] = {0};
   77     unsigned srgb_cntl = 0;
   78     unsigned i;
   79 
   80     unsigned max_layer_index = 0;
   81 
   82     for (i = 0; i < pfb->nr_cbufs; i++) {
   83         enum a6xx_format format = 0;
   84         enum a3xx_color_swap swap = WZYX;
   85         bool sint = false, uint = false;
   86         struct fd_resource *rsc = NULL;
   87         struct fdl_slice *slice = NULL;
   88         uint32_t stride = 0;
   89         uint32_t offset;
   90         uint32_t tile_mode;
   91 
   92         if (!pfb->cbufs[i])
   93             continue;
   94 
   95         mrt_comp[i] = 0xf;
   96 
   97         struct pipe_surface *psurf = pfb->cbufs[i];
   98         enum pipe_format pformat = psurf->format;
   99         rsc = fd_resource(psurf->texture);
  100         if (!rsc->bo)
  101             continue;
  102                 
  103         uint32_t base = gmem ? gmem->cbuf_base[i] : 0;
  104         slice = fd_resource_slice(rsc, psurf->u.tex.level);
  105         format = fd6_pipe2color(pformat);
  106         sint = util_format_is_pure_sint(pformat);
  107         uint = util_format_is_pure_uint(pformat);
  108 
  109         if (util_format_is_srgb(pformat))
  110             srgb_cntl |= (1 << i);
  111 
  112         offset = fd_resource_offset(rsc, psurf->u.tex.level,
  113                 psurf->u.tex.first_layer);
  114 
  115         stride = slice->pitch;
  116         swap = fd6_resource_swap(rsc, pformat);
  117 
  118         tile_mode = fd_resource_tile_mode(psurf->texture, psurf->u.tex.level);
  119         max_layer_index = psurf->u.tex.last_layer - psurf->u.tex.first_layer;
  120 
  121         debug_assert((offset + slice->size0) <= fd_bo_size(rsc->bo));
  122 
  123         OUT_REG(ring,
  124             A6XX_RB_MRT_BUF_INFO(i,
  125                 .color_format = format,
  126                 .color_tile_mode = tile_mode,
  127                 .color_swap = swap),
  128             A6XX_RB_MRT_PITCH(i, .a6xx_rb_mrt_pitch = stride),
  129             A6XX_RB_MRT_ARRAY_PITCH(i, .a6xx_rb_mrt_array_pitch = slice->size0),
  130             A6XX_RB_MRT_BASE(i, .bo = rsc->bo, .bo_offset = offset),
  131             A6XX_RB_MRT_BASE_GMEM(i, .unknown = base));
  132 
  133         OUT_REG(ring,
  134                 A6XX_SP_FS_MRT_REG(i, .color_format = format,
  135                         .color_sint = sint, .color_uint = uint));
  136 
  137         OUT_PKT4(ring, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
  138         fd6_emit_flag_reference(ring, rsc,
  139                 psurf->u.tex.level, psurf->u.tex.first_layer);
  140     }
  141 
  142     OUT_REG(ring, A6XX_RB_SRGB_CNTL(.dword = srgb_cntl));
  143     OUT_REG(ring, A6XX_SP_SRGB_CNTL(.dword = srgb_cntl));
  144 
  145     OUT_REG(ring, A6XX_RB_RENDER_COMPONENTS(
  146         .rt0 = mrt_comp[0],
  147         .rt1 = mrt_comp[1],
  148         .rt2 = mrt_comp[2],
  149         .rt3 = mrt_comp[3],
  150         .rt4 = mrt_comp[4],
  151         .rt5 = mrt_comp[5],
  152         .rt6 = mrt_comp[6],
  153         .rt7 = mrt_comp[7]));
  154 
  155     OUT_REG(ring, A6XX_SP_FS_RENDER_COMPONENTS(
  156         .rt0 = mrt_comp[0],
  157         .rt1 = mrt_comp[1],
  158         .rt2 = mrt_comp[2],
  159         .rt3 = mrt_comp[3],
  160         .rt4 = mrt_comp[4],
  161         .rt5 = mrt_comp[5],
  162         .rt6 = mrt_comp[6],
  163         .rt7 = mrt_comp[7]));
  164 
  165     OUT_REG(ring, A6XX_GRAS_MAX_LAYER_INDEX(max_layer_index));
  166 }
  167 
  168 static void
  169 emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
  170         const struct fd_gmem_stateobj *gmem)
  171 {
  172     if (zsbuf) {
  173         struct fd_resource *rsc = fd_resource(zsbuf->texture);
  174         enum a6xx_depth_format fmt = fd6_pipe2depth(zsbuf->format);
  175         struct fdl_slice *slice = fd_resource_slice(rsc, 0);
  176         uint32_t stride = slice->pitch;
  177         uint32_t size = slice->size0;
  178         uint32_t base = gmem ? gmem->zsbuf_base[0] : 0;
  179         uint32_t offset = fd_resource_offset(rsc, zsbuf->u.tex.level,
  180                 zsbuf->u.tex.first_layer);
  181 
  182         OUT_REG(ring,
  183             A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt),
  184             A6XX_RB_DEPTH_BUFFER_PITCH(.a6xx_rb_depth_buffer_pitch = stride),
  185             A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(.a6xx_rb_depth_buffer_array_pitch = size),
  186             A6XX_RB_DEPTH_BUFFER_BASE(.bo = rsc->bo, .bo_offset = offset),
  187             A6XX_RB_DEPTH_BUFFER_BASE_GMEM(.dword = base));
  188 
  189         OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
  190 
  191         OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
  192         fd6_emit_flag_reference(ring, rsc,
  193                 zsbuf->u.tex.level, zsbuf->u.tex.first_layer);
  194 
  195         if (rsc->lrz) {
  196             OUT_REG(ring, 
  197                 A6XX_GRAS_LRZ_BUFFER_BASE(.bo = rsc->lrz),
  198                 A6XX_GRAS_LRZ_BUFFER_PITCH(.pitch = rsc->lrz_pitch),
  199                 // XXX a6xx seems to use a different buffer here.. not sure what for..
  200                 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO(0),
  201                 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI(0));
  202         } else {
  203             OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
  204             OUT_RING(ring, 0x00000000);
  205             OUT_RING(ring, 0x00000000);
  206             OUT_RING(ring, 0x00000000);     /* GRAS_LRZ_BUFFER_PITCH */
  207             OUT_RING(ring, 0x00000000);     /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
  208             OUT_RING(ring, 0x00000000);
  209         }
  210 
  211         /* NOTE: blob emits GRAS_LRZ_CNTL plus GRAZ_LRZ_BUFFER_BASE
  212          * plus this CP_EVENT_WRITE at the end in it's own IB..
  213          */
  214         OUT_PKT7(ring, CP_EVENT_WRITE, 1);
  215         OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(UNK_25));
  216 
  217         if (rsc->stencil) {
  218             struct fdl_slice *slice = fd_resource_slice(rsc->stencil, 0);
  219             stride = slice->pitch;
  220             size = slice->size0;
  221             uint32_t base = gmem ? gmem->zsbuf_base[1] : 0;
  222 
  223             OUT_REG(ring,
  224                 A6XX_RB_STENCIL_INFO(.separate_stencil = true),
  225                 A6XX_RB_STENCIL_BUFFER_PITCH(.a6xx_rb_stencil_buffer_pitch = stride),
  226                 A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(.a6xx_rb_stencil_buffer_array_pitch = size),
  227                 A6XX_RB_STENCIL_BUFFER_BASE(.bo = rsc->stencil->bo),
  228                 A6XX_RB_STENCIL_BUFFER_BASE_GMEM(.dword = base));
  229         } else {
  230             OUT_REG(ring, A6XX_RB_STENCIL_INFO(0));
  231         }
  232     } else {
  233         OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
  234         OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
  235         OUT_RING(ring, 0x00000000);    /* RB_DEPTH_BUFFER_PITCH */
  236         OUT_RING(ring, 0x00000000);    /* RB_DEPTH_BUFFER_ARRAY_PITCH */
  237         OUT_RING(ring, 0x00000000);    /* RB_DEPTH_BUFFER_BASE_LO */
  238         OUT_RING(ring, 0x00000000);    /* RB_DEPTH_BUFFER_BASE_HI */
  239         OUT_RING(ring, 0x00000000);    /* RB_DEPTH_BUFFER_BASE_GMEM */
  240 
  241         OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
  242 
  243         OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
  244         OUT_RING(ring, 0x00000000);    /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
  245         OUT_RING(ring, 0x00000000);    /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
  246         OUT_RING(ring, 0x00000000);    /* GRAS_LRZ_BUFFER_PITCH */
  247         OUT_RING(ring, 0x00000000);    /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
  248         OUT_RING(ring, 0x00000000);    /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
  249 
  250         OUT_REG(ring, A6XX_RB_STENCIL_INFO(0));
  251     }
  252 }
  253 
  254 static bool
  255 use_hw_binning(struct fd_batch *batch)
  256 {
  257     const struct fd_gmem_stateobj *gmem = batch->gmem_state;
  258 
  259     // TODO figure out hw limits for binning
  260 
  261     return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) >= 2) &&
  262             (batch->num_draws > 0);
  263 }
  264 
  265 static void
  266 patch_fb_read(struct fd_batch *batch)
  267 {
  268     const struct fd_gmem_stateobj *gmem = batch->gmem_state;
  269 
  270     for (unsigned i = 0; i < fd_patch_num_elements(&batch->fb_read_patches); i++) {
  271         struct fd_cs_patch *patch = fd_patch_element(&batch->fb_read_patches, i);
  272         *patch->cs = patch->val | A6XX_TEX_CONST_2_PITCH(gmem->bin_w * gmem->cbuf_cpp[0]);
  273     }
  274     util_dynarray_clear(&batch->fb_read_patches);
  275 }
  276 
  277 static void
  278 update_render_cntl(struct fd_batch *batch, struct pipe_framebuffer_state *pfb, bool binning)
  279 {
  280     struct fd_ringbuffer *ring = batch->gmem;
  281     uint32_t cntl = 0;
  282     bool depth_ubwc_enable = false;
  283     uint32_t mrts_ubwc_enable = 0;
  284     int i;
  285 
  286     if (pfb->zsbuf) {
  287         struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
  288         depth_ubwc_enable = fd_resource_ubwc_enabled(rsc, pfb->zsbuf->u.tex.level);
  289     }
  290 
  291     for (i = 0; i < pfb->nr_cbufs; i++) {
  292         if (!pfb->cbufs[i])
  293             continue;
  294 
  295         struct pipe_surface *psurf = pfb->cbufs[i];
  296         struct fd_resource *rsc = fd_resource(psurf->texture);
  297         if (!rsc->bo)
  298             continue;
  299 
  300         if (fd_resource_ubwc_enabled(rsc, psurf->u.tex.level))
  301             mrts_ubwc_enable |= 1 << i;
  302     }
  303 
  304     cntl |= A6XX_RB_RENDER_CNTL_UNK4;
  305     if (binning)
  306         cntl |= A6XX_RB_RENDER_CNTL_BINNING;
  307 
  308     OUT_PKT7(ring, CP_REG_WRITE, 3);
  309     OUT_RING(ring, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
  310     OUT_RING(ring, REG_A6XX_RB_RENDER_CNTL);
  311     OUT_RING(ring, cntl |
  312         COND(depth_ubwc_enable, A6XX_RB_RENDER_CNTL_FLAG_DEPTH) |
  313         A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable));
  314 }
  315 
  316 /* extra size to store VSC_DRAW_STRM_SIZE: */
  317 #define VSC_DRAW_STRM_SIZE(pitch)  ((pitch) * 32 + 0x100)
  318 #define VSC_PRIM_STRM_SIZE(pitch) ((pitch) * 32)
  319 
  320 static void
  321 update_vsc_pipe(struct fd_batch *batch)
  322 {
  323     struct fd_context *ctx = batch->ctx;
  324     struct fd6_context *fd6_ctx = fd6_context(ctx);
  325     const struct fd_gmem_stateobj *gmem = batch->gmem_state;
  326     struct fd_ringbuffer *ring = batch->gmem;
  327     int i;
  328 
  329     if (batch->draw_strm_bits/8 > fd6_ctx->vsc_draw_strm_pitch) {
  330         if (fd6_ctx->vsc_draw_strm)
  331             fd_bo_del(fd6_ctx->vsc_draw_strm);
  332         fd6_ctx->vsc_draw_strm = NULL;
  333         /* Note: probably only need to align to 0x40, but aligning stronger
  334          * reduces the odds that we will have to realloc again on the next
  335          * frame:
  336          */
  337         fd6_ctx->vsc_draw_strm_pitch = align(batch->draw_strm_bits/8, 0x4000);
  338         debug_printf("pre-resize VSC_DRAW_STRM_PITCH to: 0x%x\n",
  339                 fd6_ctx->vsc_draw_strm_pitch);
  340     }
  341 
  342     if (batch->prim_strm_bits/8 > fd6_ctx->vsc_prim_strm_pitch) {
  343         if (fd6_ctx->vsc_prim_strm)
  344             fd_bo_del(fd6_ctx->vsc_prim_strm);
  345         fd6_ctx->vsc_prim_strm = NULL;
  346         fd6_ctx->vsc_prim_strm_pitch = align(batch->prim_strm_bits/8, 0x4000);
  347         debug_printf("pre-resize VSC_PRIM_STRM_PITCH to: 0x%x\n",
  348                 fd6_ctx->vsc_prim_strm_pitch);
  349     }
  350 
  351     if (!fd6_ctx->vsc_draw_strm) {
  352         fd6_ctx->vsc_draw_strm = fd_bo_new(ctx->screen->dev,
  353             VSC_DRAW_STRM_SIZE(fd6_ctx->vsc_draw_strm_pitch),
  354             DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_draw_strm");
  355     }
  356 
  357     if (!fd6_ctx->vsc_prim_strm) {
  358         fd6_ctx->vsc_prim_strm = fd_bo_new(ctx->screen->dev,
  359             VSC_PRIM_STRM_SIZE(fd6_ctx->vsc_prim_strm_pitch),
  360             DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_prim_strm");
  361     }
  362 
  363     OUT_REG(ring,
  364         A6XX_VSC_BIN_SIZE(.width = gmem->bin_w, .height = gmem->bin_h),
  365         A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(
  366             .bo = fd6_ctx->vsc_draw_strm,
  367             .bo_offset = 32 * fd6_ctx->vsc_draw_strm_pitch));
  368 
  369     OUT_REG(ring, A6XX_VSC_BIN_COUNT(.nx = gmem->nbins_x,
  370                     .ny = gmem->nbins_y));
  371 
  372     OUT_PKT4(ring, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
  373     for (i = 0; i < 32; i++) {
  374         const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[i];
  375         OUT_RING(ring, A6XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
  376                 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
  377                 A6XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
  378                 A6XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
  379     }
  380 
  381     OUT_REG(ring,
  382         A6XX_VSC_PRIM_STRM_ADDRESS(.bo = fd6_ctx->vsc_prim_strm),
  383         A6XX_VSC_PRIM_STRM_PITCH(.dword = fd6_ctx->vsc_prim_strm_pitch),
  384         A6XX_VSC_PRIM_STRM_ARRAY_PITCH(.dword = fd_bo_size(fd6_ctx->vsc_prim_strm)));
  385 
  386     OUT_REG(ring,
  387         A6XX_VSC_DRAW_STRM_ADDRESS(.bo = fd6_ctx->vsc_draw_strm),
  388         A6XX_VSC_DRAW_STRM_PITCH(.dword = fd6_ctx->vsc_draw_strm_pitch),
  389         A6XX_VSC_DRAW_STRM_ARRAY_PITCH(.dword = fd_bo_size(fd6_ctx->vsc_draw_strm)));
  390 }
  391 
  392 /* TODO we probably have more than 8 scratch regs.. although the first
  393  * 8 is what kernel dumps, and it is kinda useful to be able to see
  394  * the value in kernel traces
  395  */
  396 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
  397 
  398 /*
  399  * If overflow is detected, either 0x1 (VSC_DRAW_STRM overflow) or 0x3
  400  * (VSC_PRIM_STRM overflow) plus the size of the overflowed buffer is
  401  * written to control->vsc_overflow.  This allows the CPU to
  402  * detect which buffer overflowed (and, since the current size is
  403  * encoded as well, this protects against already-submitted but
  404  * not executed batches from fooling the CPU into increasing the
  405  * size again unnecessarily).
  406  *
  407  * To conditionally use VSC data in draw pass only if there is no
  408  * overflow, we use a scratch reg (OVERFLOW_FLAG_REG) to hold 1
  409  * if no overflow, or 0 in case of overflow.  The value is inverted
  410  * to make the CP_COND_REG_EXEC stuff easier.
  411  */
  412 static void
  413 emit_vsc_overflow_test(struct fd_batch *batch)
  414 {
  415     struct fd_ringbuffer *ring = batch->gmem;
  416     const struct fd_gmem_stateobj *gmem = batch->gmem_state;
  417     struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
  418 
  419     debug_assert((fd6_ctx->vsc_draw_strm_pitch & 0x3) == 0);
  420     debug_assert((fd6_ctx->vsc_prim_strm_pitch & 0x3) == 0);
  421 
  422     /* Clear vsc_scratch: */
  423     OUT_PKT7(ring, CP_MEM_WRITE, 3);
  424     OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_scratch));
  425     OUT_RING(ring, 0x0);
  426 
  427     /* Check for overflow, write vsc_scratch if detected: */
  428     for (int i = 0; i < gmem->num_vsc_pipes; i++) {
  429         OUT_PKT7(ring, CP_COND_WRITE5, 8);
  430         OUT_RING(ring, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
  431                 CP_COND_WRITE5_0_WRITE_MEMORY);
  432         OUT_RING(ring, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i)));
  433         OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
  434         OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_draw_strm_pitch));
  435         OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
  436         OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_scratch));  /* WRITE_ADDR_LO/HI */
  437         OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(1 + fd6_ctx->vsc_draw_strm_pitch));
  438 
  439         OUT_PKT7(ring, CP_COND_WRITE5, 8);
  440         OUT_RING(ring, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
  441                 CP_COND_WRITE5_0_WRITE_MEMORY);
  442         OUT_RING(ring, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i)));
  443         OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
  444         OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_prim_strm_pitch));
  445         OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
  446         OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_scratch));  /* WRITE_ADDR_LO/HI */
  447         OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(3 + fd6_ctx->vsc_prim_strm_pitch));
  448     }
  449 
  450     OUT_PKT7(ring, CP_WAIT_MEM_WRITES, 0);
  451 
  452     OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
  453 
  454     OUT_PKT7(ring, CP_MEM_TO_REG, 3);
  455     OUT_RING(ring, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
  456             CP_MEM_TO_REG_0_CNT(0));
  457     OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_scratch));  /* SRC_LO/HI */
  458 
  459     /*
  460      * This is a bit awkward, we really want a way to invert the
  461      * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
  462      * execute cmds to use hwbinning when a bit is *not* set.  This
  463      * dance is to invert OVERFLOW_FLAG_REG
  464      *
  465      * A CP_NOP packet is used to skip executing the 'else' clause
  466      * if (b0 set)..
  467      */
  468 
  469     BEGIN_RING(ring, 10);  /* ensure if/else doesn't get split */
  470 
  471     /* b0 will be set if VSC_DRAW_STRM or VSC_PRIM_STRM overflow: */
  472     OUT_PKT7(ring, CP_REG_TEST, 1);
  473     OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
  474             A6XX_CP_REG_TEST_0_BIT(0) |
  475             A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
  476 
  477     OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
  478     OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
  479     OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(7));
  480 
  481     /* if (b0 set) */ {
  482         /*
  483          * On overflow, mirror the value to control->vsc_overflow
  484          * which CPU is checking to detect overflow (see
  485          * check_vsc_overflow())
  486          */
  487         OUT_PKT7(ring, CP_REG_TO_MEM, 3);
  488         OUT_RING(ring, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
  489                 CP_REG_TO_MEM_0_CNT(1 - 1));
  490         OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_overflow));
  491 
  492         OUT_PKT4(ring, OVERFLOW_FLAG_REG, 1);
  493         OUT_RING(ring, 0x0);
  494 
  495         OUT_PKT7(ring, CP_NOP, 2);  /* skip 'else' when 'if' is taken */
  496     } /* else */ {
  497         OUT_PKT4(ring, OVERFLOW_FLAG_REG, 1);
  498         OUT_RING(ring, 0x1);
  499     }
  500 }
  501 
  502 static void
  503 check_vsc_overflow(struct fd_context *ctx)
  504 {
  505     struct fd6_context *fd6_ctx = fd6_context(ctx);
  506     struct fd6_control *control = fd_bo_map(fd6_ctx->control_mem);
  507     uint32_t vsc_overflow = control->vsc_overflow;
  508 
  509     if (!vsc_overflow)
  510         return;
  511 
  512     /* clear overflow flag: */
  513     control->vsc_overflow = 0;
  514 
  515     unsigned buffer = vsc_overflow & 0x3;
  516     unsigned size = vsc_overflow & ~0x3;
  517 
  518     if (buffer == 0x1) {
  519         /* VSC_DRAW_STRM overflow: */
  520 
  521         if (size < fd6_ctx->vsc_draw_strm_pitch) {
  522             /* we've already increased the size, this overflow is
  523              * from a batch submitted before resize, but executed
  524              * after
  525              */
  526             return;
  527         }
  528 
  529         fd_bo_del(fd6_ctx->vsc_draw_strm);
  530         fd6_ctx->vsc_draw_strm = NULL;
  531         fd6_ctx->vsc_draw_strm_pitch *= 2;
  532 
  533         debug_printf("resized VSC_DRAW_STRM_PITCH to: 0x%x\n",
  534                 fd6_ctx->vsc_draw_strm_pitch);
  535 
  536     } else if (buffer == 0x3) {
  537         /* VSC_PRIM_STRM overflow: */
  538 
  539         if (size < fd6_ctx->vsc_prim_strm_pitch) {
  540             /* we've already increased the size */
  541             return;
  542         }
  543 
  544         fd_bo_del(fd6_ctx->vsc_prim_strm);
  545         fd6_ctx->vsc_prim_strm = NULL;
  546         fd6_ctx->vsc_prim_strm_pitch *= 2;
  547 
  548         debug_printf("resized VSC_PRIM_STRM_PITCH to: 0x%x\n",
  549                 fd6_ctx->vsc_prim_strm_pitch);
  550 
  551     } else {
  552         /* NOTE: it's possible, for example, for overflow to corrupt the
  553          * control page.  I mostly just see this hit if I set initial VSC
  554          * buffer size extremely small.  Things still seem to recover,
  555          * but maybe we should pre-emptively realloc vsc_data/vsc_data2
  556          * and hope for different memory placement?
  557          */
  558         DBG("invalid vsc_overflow value: 0x%08x", vsc_overflow);
  559     }
  560 }
  561 
  562 /*
  563  * Emit conditional CP_INDIRECT_BRANCH based on VSC_STATE[p], ie. the IB
  564  * is skipped for tiles that have no visible geometry.
  565  */
  566 static void
  567 emit_conditional_ib(struct fd_batch *batch, const struct fd_tile *tile,
  568         struct fd_ringbuffer *target)
  569 {
  570     struct fd_ringbuffer *ring = batch->gmem;
  571 
  572     if (target->cur == target->start)
  573         return;
  574 
  575     emit_marker6(ring, 6);
  576 
  577     unsigned count = fd_ringbuffer_cmd_count(target);
  578 
  579     BEGIN_RING(ring, 5 + 4 * count);  /* ensure conditional doesn't get split */
  580 
  581     OUT_PKT7(ring, CP_REG_TEST, 1);
  582     OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(REG_A6XX_VSC_STATE_REG(tile->p)) |
  583             A6XX_CP_REG_TEST_0_BIT(tile->n) |
  584             A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
  585 
  586     OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
  587     OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
  588     OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(4 * count));
  589 
  590     for (unsigned i = 0; i < count; i++) {
  591         uint32_t dwords;
  592         OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
  593         dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
  594         assert(dwords > 0);
  595         OUT_RING(ring, dwords);
  596     }
  597 
  598     emit_marker6(ring, 6);
  599 }
  600 
  601 static void
  602 set_scissor(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2)
  603 {
  604     OUT_REG(ring,
  605             A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1),
  606             A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
  607 
  608     OUT_REG(ring,
  609             A6XX_GRAS_RESOLVE_CNTL_1(.x = x1, .y = y1),
  610             A6XX_GRAS_RESOLVE_CNTL_2(.x = x2, .y = y2));
  611 }
  612 
  613 static void
  614 set_bin_size(struct fd_ringbuffer *ring, uint32_t w, uint32_t h, uint32_t flag)
  615 {
  616     OUT_REG(ring, A6XX_GRAS_BIN_CONTROL(.binw = w, .binh = h, .dword = flag));
  617     OUT_REG(ring, A6XX_RB_BIN_CONTROL(.binw = w, .binh = h, .dword = flag));
  618     /* no flag for RB_BIN_CONTROL2... */
  619     OUT_REG(ring, A6XX_RB_BIN_CONTROL2(.binw = w, .binh = h));
  620 }
  621 
  622 static void
  623 emit_binning_pass(struct fd_batch *batch)
  624 {
  625     struct fd_ringbuffer *ring = batch->gmem;
  626     const struct fd_gmem_stateobj *gmem = batch->gmem_state;
  627     struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
  628 
  629     uint32_t x1 = gmem->minx;
  630     uint32_t y1 = gmem->miny;
  631     uint32_t x2 = gmem->minx + gmem->width - 1;
  632     uint32_t y2 = gmem->miny + gmem->height - 1;
  633 
  634     debug_assert(!batch->tessellation);
  635 
  636     set_scissor(ring, x1, y1, x2, y2);
  637 
  638     emit_marker6(ring, 7);
  639     OUT_PKT7(ring, CP_SET_MARKER, 1);
  640     OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
  641     emit_marker6(ring, 7);
  642 
  643     OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
  644     OUT_RING(ring, 0x1);
  645 
  646     OUT_PKT7(ring, CP_SET_MODE, 1);
  647     OUT_RING(ring, 0x1);
  648 
  649     OUT_WFI5(ring);
  650 
  651     OUT_REG(ring, A6XX_VFD_MODE_CNTL(.binning_pass = true));
  652 
  653     update_vsc_pipe(batch);
  654 
  655     OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
  656     OUT_RING(ring, fd6_ctx->magic.PC_UNKNOWN_9805);
  657 
  658     OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
  659     OUT_RING(ring, fd6_ctx->magic.SP_UNKNOWN_A0F8);
  660 
  661     OUT_PKT7(ring, CP_EVENT_WRITE, 1);
  662     OUT_RING(ring, UNK_2C);
  663 
  664     OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
  665     OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(0) |
  666             A6XX_RB_WINDOW_OFFSET_Y(0));
  667 
  668     OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
  669     OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
  670             A6XX_SP_TP_WINDOW_OFFSET_Y(0));
  671 
  672     /* emit IB to binning drawcmds: */
  673     fd_log(batch, "GMEM: START BINNING IB");
  674     fd6_emit_ib(ring, batch->draw);
  675     fd_log(batch, "GMEM: END BINNING IB");
  676 
  677     fd_reset_wfi(batch);
  678 
  679     OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
  680     OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
  681             CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
  682             CP_SET_DRAW_STATE__0_GROUP_ID(0));
  683     OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
  684     OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
  685 
  686     OUT_PKT7(ring, CP_EVENT_WRITE, 1);
  687     OUT_RING(ring, UNK_2D);
  688 
  689     fd6_cache_inv(batch, ring);
  690     fd6_cache_flush(batch, ring);
  691     fd_wfi(batch, ring);
  692 
  693     OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
  694 
  695     fd_log(batch, "START VSC OVERFLOW TEST");
  696     emit_vsc_overflow_test(batch);
  697     fd_log(batch, "END VSC OVERFLOW TEST");
  698 
  699     OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
  700     OUT_RING(ring, 0x0);
  701 
  702     OUT_PKT7(ring, CP_SET_MODE, 1);
  703     OUT_RING(ring, 0x0);
  704 
  705     OUT_WFI5(ring);
  706 
  707     OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
  708     OUT_RING(ring, fd6_ctx->magic.RB_CCU_CNTL_gmem);
  709 }
  710 
  711 static void
  712 emit_msaa(struct fd_ringbuffer *ring, unsigned nr)
  713 {
  714     enum a3xx_msaa_samples samples = fd_msaa_samples(nr);
  715 
  716     OUT_PKT4(ring, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
  717     OUT_RING(ring, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
  718     OUT_RING(ring, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
  719              COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
  720 
  721     OUT_PKT4(ring, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
  722     OUT_RING(ring, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
  723     OUT_RING(ring, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
  724              COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
  725 
  726     OUT_PKT4(ring, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
  727     OUT_RING(ring, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
  728     OUT_RING(ring, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
  729              COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
  730 
  731     OUT_PKT4(ring, REG_A6XX_RB_MSAA_CNTL, 1);
  732     OUT_RING(ring, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
  733 }
  734 
  735 static void prepare_tile_setup_ib(struct fd_batch *batch);
  736 static void prepare_tile_fini_ib(struct fd_batch *batch);
  737 
  738 /* before first tile */
  739 static void
  740 fd6_emit_tile_init(struct fd_batch *batch)
  741 {
  742     struct fd_context *ctx = batch->ctx;
  743     struct fd_ringbuffer *ring = batch->gmem;
  744     struct pipe_framebuffer_state *pfb = &batch->framebuffer;
  745     const struct fd_gmem_stateobj *gmem = batch->gmem_state;
  746 
  747     fd6_emit_restore(batch, ring);
  748 
  749     fd6_emit_lrz_flush(ring);
  750 
  751     if (batch->lrz_clear) {
  752         fd_log(batch, "START LRZ CLEAR");
  753         fd6_emit_ib(ring, batch->lrz_clear);
  754         fd_log(batch, "END LRZ CLEAR");
  755     }
  756 
  757     fd6_cache_inv(batch, ring);
  758 
  759     prepare_tile_setup_ib(batch);
  760     prepare_tile_fini_ib(batch);
  761 
  762     OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
  763     OUT_RING(ring, 0x0);
  764 
  765     /* blob controls "local" in IB2, but I think that is not required */
  766     OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_LOCAL, 1);
  767     OUT_RING(ring, 0x1);
  768 
  769     fd_wfi(batch, ring);
  770     OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
  771     OUT_RING(ring, fd6_context(ctx)->magic.RB_CCU_CNTL_gmem);
  772 
  773     emit_zs(ring, pfb->zsbuf, batch->gmem_state);
  774     emit_mrt(ring, pfb, batch->gmem_state);
  775     emit_msaa(ring, pfb->samples);
  776     patch_fb_read(batch);
  777 
  778     if (use_hw_binning(batch)) {
  779         /* enable stream-out during binning pass: */
  780         OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
  781         OUT_RING(ring, 0);
  782 
  783         set_bin_size(ring, gmem->bin_w, gmem->bin_h,
  784                 A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
  785         update_render_cntl(batch, pfb, true);
  786         emit_binning_pass(batch);
  787 
  788         /* and disable stream-out for draw pass: */
  789         OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
  790         OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
  791 
  792         /*
  793          * NOTE: even if we detect VSC overflow and disable use of
  794          * visibility stream in draw pass, it is still safe to execute
  795          * the reset of these cmds:
  796          */
  797 
  798 // NOTE a618 not setting .USE_VIZ .. from a quick check on a630, it
  799 // does not appear that this bit changes much (ie. it isn't actually
  800 // .USE_VIZ like previous gens)
  801         set_bin_size(ring, gmem->bin_w, gmem->bin_h,
  802                 A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
  803 
  804         OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
  805         OUT_RING(ring, 0x0);
  806 
  807         OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
  808         OUT_RING(ring, fd6_context(ctx)->magic.PC_UNKNOWN_9805);
  809 
  810         OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
  811         OUT_RING(ring, fd6_context(ctx)->magic.SP_UNKNOWN_A0F8);
  812 
  813         OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
  814         OUT_RING(ring, 0x1);
  815     } else {
  816         /* no binning pass, so enable stream-out for draw pass:: */
  817         OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
  818         OUT_RING(ring, 0);
  819 
  820         set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
  821     }
  822 
  823     update_render_cntl(batch, pfb, false);
  824 }
  825 
  826 static void
  827 set_window_offset(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1)
  828 {
  829     OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
  830     OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(x1) |
  831             A6XX_RB_WINDOW_OFFSET_Y(y1));
  832 
  833     OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET2, 1);
  834     OUT_RING(ring, A6XX_RB_WINDOW_OFFSET2_X(x1) |
  835             A6XX_RB_WINDOW_OFFSET2_Y(y1));
  836 
  837     OUT_PKT4(ring, REG_A6XX_SP_WINDOW_OFFSET, 1);
  838     OUT_RING(ring, A6XX_SP_WINDOW_OFFSET_X(x1) |
  839             A6XX_SP_WINDOW_OFFSET_Y(y1));
  840 
  841     OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
  842     OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(x1) |
  843             A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
  844 }
  845 
  846 /* before mem2gmem */
  847 static void
  848 fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
  849 {
  850     struct fd_context *ctx = batch->ctx;
  851     const struct fd_gmem_stateobj *gmem = batch->gmem_state;
  852     struct fd6_context *fd6_ctx = fd6_context(ctx);
  853     struct fd_ringbuffer *ring = batch->gmem;
  854 
  855     emit_marker6(ring, 7);
  856     OUT_PKT7(ring, CP_SET_MARKER, 1);
  857     OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
  858     emit_marker6(ring, 7);
  859 
  860     uint32_t x1 = tile->xoff;
  861     uint32_t y1 = tile->yoff;
  862     uint32_t x2 = tile->xoff + tile->bin_w - 1;
  863     uint32_t y2 = tile->yoff + tile->bin_h - 1;
  864 
  865     set_scissor(ring, x1, y1, x2, y2);
  866 
  867     if (use_hw_binning(batch)) {
  868         const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[tile->p];
  869 
  870         OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
  871 
  872         OUT_PKT7(ring, CP_SET_MODE, 1);
  873         OUT_RING(ring, 0x0);
  874 
  875         /*
  876          * Conditionally execute if no VSC overflow:
  877          */
  878 
  879         BEGIN_RING(ring, 18);  /* ensure if/else doesn't get split */
  880 
  881         OUT_PKT7(ring, CP_REG_TEST, 1);
  882         OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
  883                 A6XX_CP_REG_TEST_0_BIT(0) |
  884                 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
  885 
  886         OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
  887         OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
  888         OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(11));
  889 
  890         /* if (no overflow) */ {
  891             OUT_PKT7(ring, CP_SET_BIN_DATA5, 7);
  892             OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
  893                     CP_SET_BIN_DATA5_0_VSC_N(tile->n));
  894             OUT_RELOC(ring, fd6_ctx->vsc_draw_strm,       /* per-pipe draw-stream address */
  895                     (tile->p * fd6_ctx->vsc_draw_strm_pitch), 0, 0);
  896             OUT_RELOC(ring, fd6_ctx->vsc_draw_strm,       /* VSC_DRAW_STRM_ADDRESS + (p * 4) */
  897                     (tile->p * 4) + (32 * fd6_ctx->vsc_draw_strm_pitch), 0, 0);
  898             OUT_RELOC(ring, fd6_ctx->vsc_prim_strm,
  899                     (tile->p * fd6_ctx->vsc_prim_strm_pitch), 0, 0);
  900 
  901             OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
  902             OUT_RING(ring, 0x0);
  903 
  904             /* use a NOP packet to skip over the 'else' side: */
  905             OUT_PKT7(ring, CP_NOP, 2);
  906         } /* else */ {
  907             OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
  908             OUT_RING(ring, 0x1);
  909         }
  910 
  911         set_window_offset(ring, x1, y1);
  912 
  913         const struct fd_gmem_stateobj *gmem = batch->gmem_state;
  914         set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
  915 
  916         OUT_PKT7(ring, CP_SET_MODE, 1);
  917         OUT_RING(ring, 0x0);
  918     } else {
  919         set_window_offset(ring, x1, y1);
  920 
  921         OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
  922         OUT_RING(ring, 0x1);
  923 
  924         OUT_PKT7(ring, CP_SET_MODE, 1);
  925         OUT_RING(ring, 0x0);
  926     }
  927 }
  928 
  929 static void
  930 set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
  931 {
  932     struct pipe_scissor_state blit_scissor;
  933     struct pipe_framebuffer_state *pfb = &batch->framebuffer;
  934 
  935     blit_scissor.minx = 0;
  936     blit_scissor.miny = 0;
  937     blit_scissor.maxx = align(pfb->width, batch->ctx->screen->gmem_alignw);
  938     blit_scissor.maxy = align(pfb->height, batch->ctx->screen->gmem_alignh);
  939 
  940     OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
  941     OUT_RING(ring,
  942              A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |
  943              A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor.miny));
  944     OUT_RING(ring,
  945              A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor.maxx - 1) |
  946              A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor.maxy - 1));
  947 }
  948 
  949 static void
  950 emit_blit(struct fd_batch *batch,
  951           struct fd_ringbuffer *ring,
  952           uint32_t base,
  953           struct pipe_surface *psurf,
  954           bool stencil)
  955 {
  956     struct fdl_slice *slice;
  957     struct fd_resource *rsc = fd_resource(psurf->texture);
  958     enum pipe_format pfmt = psurf->format;
  959     uint32_t offset;
  960     bool ubwc_enabled;
  961 
  962     debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
  963 
  964     /* separate stencil case: */
  965     if (stencil) {
  966         rsc = rsc->stencil;
  967         pfmt = rsc->base.format;
  968     }
  969 
  970     slice = fd_resource_slice(rsc, psurf->u.tex.level);
  971     offset = fd_resource_offset(rsc, psurf->u.tex.level,
  972             psurf->u.tex.first_layer);
  973     ubwc_enabled = fd_resource_ubwc_enabled(rsc, psurf->u.tex.level);
  974 
  975     debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
  976 
  977     enum a6xx_format format = fd6_pipe2color(pfmt);
  978     uint32_t stride = slice->pitch;
  979     uint32_t size = slice->size0;
  980     enum a3xx_color_swap swap = fd6_resource_swap(rsc, pfmt);
  981     enum a3xx_msaa_samples samples =
  982             fd_msaa_samples(rsc->base.nr_samples);
  983     uint32_t tile_mode = fd_resource_tile_mode(&rsc->base, psurf->u.tex.level);
  984 
  985     OUT_REG(ring,
  986         A6XX_RB_BLIT_DST_INFO(.tile_mode = tile_mode, .samples = samples,
  987             .color_format = format, .color_swap = swap, .flags = ubwc_enabled),
  988         A6XX_RB_BLIT_DST(.bo = rsc->bo, .bo_offset = offset),
  989         A6XX_RB_BLIT_DST_PITCH(.a6xx_rb_blit_dst_pitch = stride),
  990         A6XX_RB_BLIT_DST_ARRAY_PITCH(.a6xx_rb_blit_dst_array_pitch = size));
  991 
  992     OUT_REG(ring, A6XX_RB_BLIT_BASE_GMEM(.dword = base));
  993 
  994     if (ubwc_enabled) {
  995         OUT_PKT4(ring, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
  996         fd6_emit_flag_reference(ring, rsc,
  997                 psurf->u.tex.level, psurf->u.tex.first_layer);
  998     }
  999 
 1000     fd6_emit_blit(batch, ring);
 1001 }
 1002 
 1003 static void
 1004 emit_restore_blit(struct fd_batch *batch,
 1005                   struct fd_ringbuffer *ring,
 1006                   uint32_t base,
 1007                   struct pipe_surface *psurf,
 1008                   unsigned buffer)
 1009 {
 1010     bool stencil = (buffer == FD_BUFFER_STENCIL);
 1011 
 1012     OUT_REG(ring, A6XX_RB_BLIT_INFO(
 1013         .gmem = true, .unk0 = true,
 1014         .depth = (buffer == FD_BUFFER_DEPTH),
 1015         .integer = util_format_is_pure_integer(psurf->format)));
 1016 
 1017     emit_blit(batch, ring, base, psurf, stencil);
 1018 }
 1019 
 1020 static void
 1021 emit_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
 1022 {
 1023     struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 1024     const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 1025     enum a3xx_msaa_samples samples = fd_msaa_samples(pfb->samples);
 1026 
 1027     uint32_t buffers = batch->fast_cleared;
 1028 
 1029     if (buffers & PIPE_CLEAR_COLOR) {
 1030 
 1031         for (int i = 0; i < pfb->nr_cbufs; i++) {
 1032             union pipe_color_union *color = &batch->clear_color[i];
 1033             union util_color uc = {0};
 1034 
 1035             if (!pfb->cbufs[i])
 1036                 continue;
 1037 
 1038             if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
 1039                 continue;
 1040 
 1041             enum pipe_format pfmt = pfb->cbufs[i]->format;
 1042 
 1043             // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
 1044             union pipe_color_union swapped;
 1045             switch (fd6_pipe2swap(pfmt)) {
 1046             case WZYX:
 1047                 swapped.ui[0] = color->ui[0];
 1048                 swapped.ui[1] = color->ui[1];
 1049                 swapped.ui[2] = color->ui[2];
 1050                 swapped.ui[3] = color->ui[3];
 1051                 break;
 1052             case WXYZ:
 1053                 swapped.ui[2] = color->ui[0];
 1054                 swapped.ui[1] = color->ui[1];
 1055                 swapped.ui[0] = color->ui[2];
 1056                 swapped.ui[3] = color->ui[3];
 1057                 break;
 1058             case ZYXW:
 1059                 swapped.ui[3] = color->ui[0];
 1060                 swapped.ui[0] = color->ui[1];
 1061                 swapped.ui[1] = color->ui[2];
 1062                 swapped.ui[2] = color->ui[3];
 1063                 break;
 1064             case XYZW:
 1065                 swapped.ui[3] = color->ui[0];
 1066                 swapped.ui[2] = color->ui[1];
 1067                 swapped.ui[1] = color->ui[2];
 1068                 swapped.ui[0] = color->ui[3];
 1069                 break;
 1070             }
 1071 
 1072             util_pack_color_union(pfmt, &uc, &swapped);
 1073 
 1074             OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
 1075             OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 1076                 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
 1077                 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
 1078 
 1079             OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
 1080             OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
 1081                 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
 1082 
 1083             OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
 1084             OUT_RING(ring, gmem->cbuf_base[i]);
 1085 
 1086             OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
 1087             OUT_RING(ring, 0);
 1088 
 1089             OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
 1090             OUT_RING(ring, uc.ui[0]);
 1091             OUT_RING(ring, uc.ui[1]);
 1092             OUT_RING(ring, uc.ui[2]);
 1093             OUT_RING(ring, uc.ui[3]);
 1094 
 1095             fd6_emit_blit(batch, ring);
 1096         }
 1097     }
 1098 
 1099     const bool has_depth = pfb->zsbuf;
 1100     const bool has_separate_stencil =
 1101         has_depth && fd_resource(pfb->zsbuf->texture)->stencil;
 1102 
 1103     /* First clear depth or combined depth/stencil. */
 1104     if ((has_depth && (buffers & PIPE_CLEAR_DEPTH)) ||
 1105         (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))) {
 1106         enum pipe_format pfmt = pfb->zsbuf->format;
 1107         uint32_t clear_value;
 1108         uint32_t mask = 0;
 1109 
 1110         if (has_separate_stencil) {
 1111             pfmt = util_format_get_depth_only(pfb->zsbuf->format);
 1112             clear_value = util_pack_z(pfmt, batch->clear_depth);
 1113         } else {
 1114             pfmt = pfb->zsbuf->format;
 1115             clear_value = util_pack_z_stencil(pfmt, batch->clear_depth,
 1116                                               batch->clear_stencil);
 1117         }
 1118 
 1119         if (buffers & PIPE_CLEAR_DEPTH)
 1120             mask |= 0x1;
 1121 
 1122         if (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))
 1123             mask |= 0x2;
 1124 
 1125         OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
 1126         OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 1127             A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
 1128             A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
 1129 
 1130         OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
 1131         OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
 1132             // XXX UNK0 for separate stencil ??
 1133             A6XX_RB_BLIT_INFO_DEPTH |
 1134             A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
 1135 
 1136         OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
 1137         OUT_RING(ring, gmem->zsbuf_base[0]);
 1138 
 1139         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
 1140         OUT_RING(ring, 0);
 1141 
 1142         OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
 1143         OUT_RING(ring, clear_value);
 1144 
 1145         fd6_emit_blit(batch, ring);
 1146     }
 1147 
 1148     /* Then clear the separate stencil buffer in case of 32 bit depth
 1149      * formats with separate stencil. */
 1150     if (has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL)) {
 1151         OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
 1152         OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 1153                  A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
 1154                  A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(FMT6_8_UINT));
 1155 
 1156         OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
 1157         OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
 1158                  //A6XX_RB_BLIT_INFO_UNK0 |
 1159                  A6XX_RB_BLIT_INFO_DEPTH |
 1160                  A6XX_RB_BLIT_INFO_CLEAR_MASK(0x1));
 1161 
 1162         OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
 1163         OUT_RING(ring, gmem->zsbuf_base[1]);
 1164 
 1165         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
 1166         OUT_RING(ring, 0);
 1167 
 1168         OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
 1169         OUT_RING(ring, batch->clear_stencil & 0xff);
 1170 
 1171         fd6_emit_blit(batch, ring);
 1172     }
 1173 }
 1174 
 1175 /*
 1176  * transfer from system memory to gmem
 1177  */
 1178 static void
 1179 emit_restore_blits(struct fd_batch *batch, struct fd_ringbuffer *ring)
 1180 {
 1181     const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 1182     struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 1183 
 1184     if (batch->restore & FD_BUFFER_COLOR) {
 1185         unsigned i;
 1186         for (i = 0; i < pfb->nr_cbufs; i++) {
 1187             if (!pfb->cbufs[i])
 1188                 continue;
 1189             if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
 1190                 continue;
 1191             emit_restore_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
 1192                               FD_BUFFER_COLOR);
 1193         }
 1194     }
 1195 
 1196     if (batch->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
 1197         struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
 1198 
 1199         if (!rsc->stencil || (batch->restore & FD_BUFFER_DEPTH)) {
 1200             emit_restore_blit(batch, ring, gmem->zsbuf_base[0], pfb->zsbuf,
 1201                               FD_BUFFER_DEPTH);
 1202         }
 1203         if (rsc->stencil && (batch->restore & FD_BUFFER_STENCIL)) {
 1204             emit_restore_blit(batch, ring, gmem->zsbuf_base[1], pfb->zsbuf,
 1205                               FD_BUFFER_STENCIL);
 1206         }
 1207     }
 1208 }
 1209 
 1210 static void
 1211 prepare_tile_setup_ib(struct fd_batch *batch)
 1212 {
 1213     batch->tile_setup = fd_submit_new_ringbuffer(batch->submit, 0x1000,
 1214             FD_RINGBUFFER_STREAMING);
 1215 
 1216     set_blit_scissor(batch, batch->tile_setup);
 1217 
 1218     emit_restore_blits(batch, batch->tile_setup);
 1219     emit_clears(batch, batch->tile_setup);
 1220 }
 1221 
 1222 /*
 1223  * transfer from system memory to gmem
 1224  */
 1225 static void
 1226 fd6_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
 1227 {
 1228 }
 1229 
 1230 /* before IB to rendering cmds: */
 1231 static void
 1232 fd6_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
 1233 {
 1234     fd_log(batch, "TILE: START CLEAR/RESTORE");
 1235     if (batch->fast_cleared || !use_hw_binning(batch)) {
 1236         fd6_emit_ib(batch->gmem, batch->tile_setup);
 1237     } else {
 1238         emit_conditional_ib(batch, tile, batch->tile_setup);
 1239     }
 1240     fd_log(batch, "TILE: END CLEAR/RESTORE");
 1241 }
 1242 
 1243 static void
 1244 emit_resolve_blit(struct fd_batch *batch,
 1245                   struct fd_ringbuffer *ring,
 1246                   uint32_t base,
 1247                   struct pipe_surface *psurf,
 1248                   unsigned buffer)
 1249 {
 1250     uint32_t info = 0;
 1251     bool stencil = false;
 1252 
 1253     if (!fd_resource(psurf->texture)->valid)
 1254         return;
 1255 
 1256     switch (buffer) {
 1257     case FD_BUFFER_COLOR:
 1258         break;
 1259     case FD_BUFFER_STENCIL:
 1260         info |= A6XX_RB_BLIT_INFO_UNK0;
 1261         stencil = true;
 1262         break;
 1263     case FD_BUFFER_DEPTH:
 1264         info |= A6XX_RB_BLIT_INFO_DEPTH;
 1265         break;
 1266     }
 1267 
 1268     if (util_format_is_pure_integer(psurf->format))
 1269         info |= A6XX_RB_BLIT_INFO_INTEGER;
 1270 
 1271     OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
 1272     OUT_RING(ring, info);
 1273 
 1274     emit_blit(batch, ring, base, psurf, stencil);
 1275 }
 1276 
 1277 /*
 1278  * transfer from gmem to system memory (ie. normal RAM)
 1279  */
 1280 
 1281 static void
 1282 prepare_tile_fini_ib(struct fd_batch *batch)
 1283 {
 1284     const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 1285     struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 1286     struct fd_ringbuffer *ring;
 1287 
 1288     batch->tile_fini = fd_submit_new_ringbuffer(batch->submit, 0x1000,
 1289             FD_RINGBUFFER_STREAMING);
 1290     ring = batch->tile_fini;
 1291 
 1292     set_blit_scissor(batch, ring);
 1293 
 1294     if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
 1295         struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
 1296 
 1297         if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH)) {
 1298             emit_resolve_blit(batch, ring,
 1299                               gmem->zsbuf_base[0], pfb->zsbuf,
 1300                               FD_BUFFER_DEPTH);
 1301         }
 1302         if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL)) {
 1303             emit_resolve_blit(batch, ring,
 1304                               gmem->zsbuf_base[1], pfb->zsbuf,
 1305                               FD_BUFFER_STENCIL);
 1306         }
 1307     }
 1308 
 1309     if (batch->resolve & FD_BUFFER_COLOR) {
 1310         unsigned i;
 1311         for (i = 0; i < pfb->nr_cbufs; i++) {
 1312             if (!pfb->cbufs[i])
 1313                 continue;
 1314             if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
 1315                 continue;
 1316             emit_resolve_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
 1317                               FD_BUFFER_COLOR);
 1318         }
 1319     }
 1320 }
 1321 
 1322 static void
 1323 fd6_emit_tile(struct fd_batch *batch, const struct fd_tile *tile)
 1324 {
 1325     if (!use_hw_binning(batch)) {
 1326         fd6_emit_ib(batch->gmem, batch->draw);
 1327     } else {
 1328         emit_conditional_ib(batch, tile, batch->draw);
 1329     }
 1330 }
 1331 
 1332 static void
 1333 fd6_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
 1334 {
 1335     struct fd_ringbuffer *ring = batch->gmem;
 1336 
 1337     if (use_hw_binning(batch)) {
 1338         /* Conditionally execute if no VSC overflow: */
 1339 
 1340         BEGIN_RING(ring, 7);  /* ensure if/else doesn't get split */
 1341 
 1342         OUT_PKT7(ring, CP_REG_TEST, 1);
 1343         OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
 1344                 A6XX_CP_REG_TEST_0_BIT(0) |
 1345                 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
 1346 
 1347         OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
 1348         OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
 1349         OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(2));
 1350 
 1351         /* if (no overflow) */ {
 1352             OUT_PKT7(ring, CP_SET_MARKER, 1);
 1353             OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
 1354         }
 1355     }
 1356 
 1357     OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
 1358     OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
 1359             CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
 1360             CP_SET_DRAW_STATE__0_GROUP_ID(0));
 1361     OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
 1362     OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
 1363 
 1364     OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_LOCAL, 1);
 1365     OUT_RING(ring, 0x0);
 1366 
 1367     emit_marker6(ring, 7);
 1368     OUT_PKT7(ring, CP_SET_MARKER, 1);
 1369     OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
 1370     emit_marker6(ring, 7);
 1371 
 1372     fd_log(batch, "TILE: START RESOLVE");
 1373     if (batch->fast_cleared || !use_hw_binning(batch)) {
 1374         fd6_emit_ib(batch->gmem, batch->tile_fini);
 1375     } else {
 1376         emit_conditional_ib(batch, tile, batch->tile_fini);
 1377     }
 1378     fd_log(batch, "TILE: END RESOLVE");
 1379 }
 1380 
 1381 static void
 1382 fd6_emit_tile_fini(struct fd_batch *batch)
 1383 {
 1384     struct fd_ringbuffer *ring = batch->gmem;
 1385 
 1386     OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
 1387     OUT_RING(ring, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
 1388 
 1389     fd6_emit_lrz_flush(ring);
 1390 
 1391     fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
 1392 
 1393     if (use_hw_binning(batch)) {
 1394         check_vsc_overflow(batch->ctx);
 1395     }
 1396 }
 1397 
 1398 static void
 1399 emit_sysmem_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
 1400 {
 1401     struct fd_context *ctx = batch->ctx;
 1402     struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 1403 
 1404     uint32_t buffers = batch->fast_cleared;
 1405 
 1406     if (buffers & PIPE_CLEAR_COLOR) {
 1407         for (int i = 0; i < pfb->nr_cbufs; i++) {
 1408             union pipe_color_union *color = &batch->clear_color[i];
 1409 
 1410             if (!pfb->cbufs[i])
 1411                 continue;
 1412 
 1413             if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
 1414                 continue;
 1415 
 1416             fd6_clear_surface(ctx, ring,
 1417                     pfb->cbufs[i], pfb->width, pfb->height, color);
 1418         }
 1419     }
 1420     if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
 1421         union pipe_color_union value = {};
 1422 
 1423         const bool has_depth = pfb->zsbuf;
 1424         struct pipe_resource *separate_stencil =
 1425             has_depth && fd_resource(pfb->zsbuf->texture)->stencil ?
 1426             &fd_resource(pfb->zsbuf->texture)->stencil->base : NULL;
 1427 
 1428         if ((has_depth && (buffers & PIPE_CLEAR_DEPTH)) ||
 1429                 (!separate_stencil && (buffers & PIPE_CLEAR_STENCIL))) {
 1430             value.f[0] = batch->clear_depth;
 1431             value.ui[1] = batch->clear_stencil;
 1432             fd6_clear_surface(ctx, ring,
 1433                     pfb->zsbuf, pfb->width, pfb->height, &value);
 1434         }
 1435 
 1436         if (separate_stencil && (buffers & PIPE_CLEAR_STENCIL)) {
 1437             value.ui[0] = batch->clear_stencil;
 1438 
 1439             struct pipe_surface stencil_surf = *pfb->zsbuf;
 1440             stencil_surf.texture = separate_stencil;
 1441 
 1442             fd6_clear_surface(ctx, ring,
 1443                     &stencil_surf, pfb->width, pfb->height, &value);
 1444         }
 1445     }
 1446 
 1447     fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
 1448 }
 1449 
 1450 static void
 1451 setup_tess_buffers(struct fd_batch *batch, struct fd_ringbuffer *ring)
 1452 {
 1453     struct fd_context *ctx = batch->ctx;
 1454 
 1455     batch->tessfactor_bo = fd_bo_new(ctx->screen->dev,
 1456             batch->tessfactor_size,
 1457             DRM_FREEDRENO_GEM_TYPE_KMEM, "tessfactor");
 1458 
 1459     batch->tessparam_bo = fd_bo_new(ctx->screen->dev,
 1460             batch->tessparam_size,
 1461             DRM_FREEDRENO_GEM_TYPE_KMEM, "tessparam");
 1462 
 1463     OUT_PKT4(ring, REG_A6XX_PC_TESSFACTOR_ADDR_LO, 2);
 1464     OUT_RELOCW(ring, batch->tessfactor_bo, 0, 0, 0);
 1465 
 1466     batch->tess_addrs_constobj->cur = batch->tess_addrs_constobj->start;
 1467     OUT_RELOCW(batch->tess_addrs_constobj, batch->tessparam_bo, 0, 0, 0);
 1468     OUT_RELOCW(batch->tess_addrs_constobj, batch->tessfactor_bo, 0, 0, 0);
 1469 }
 1470 
 1471 static void
 1472 fd6_emit_sysmem_prep(struct fd_batch *batch)
 1473 {
 1474     struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 1475     struct fd_ringbuffer *ring = batch->gmem;
 1476 
 1477     fd6_emit_restore(batch, ring);
 1478 
 1479     if (pfb->width > 0 && pfb->height > 0)
 1480         set_scissor(ring, 0, 0, pfb->width - 1, pfb->height - 1);
 1481     else
 1482         set_scissor(ring, 0, 0, 0, 0);
 1483 
 1484     set_window_offset(ring, 0, 0);
 1485 
 1486     set_bin_size(ring, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
 1487 
 1488     emit_sysmem_clears(batch, ring);
 1489 
 1490     fd6_emit_lrz_flush(ring);
 1491 
 1492     if (batch->lrz_clear)
 1493         fd6_emit_ib(ring, batch->lrz_clear);
 1494 
 1495     emit_marker6(ring, 7);
 1496     OUT_PKT7(ring, CP_SET_MARKER, 1);
 1497     OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
 1498     emit_marker6(ring, 7);
 1499 
 1500     if (batch->tessellation)
 1501         setup_tess_buffers(batch, ring);
 1502 
 1503     OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
 1504     OUT_RING(ring, 0x0);
 1505 
 1506     /* blob controls "local" in IB2, but I think that is not required */
 1507     OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_LOCAL, 1);
 1508     OUT_RING(ring, 0x1);
 1509 
 1510     fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
 1511     fd6_cache_inv(batch, ring);
 1512 
 1513     fd_wfi(batch, ring);
 1514     OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
 1515     OUT_RING(ring, fd6_context(batch->ctx)->magic.RB_CCU_CNTL_bypass);
 1516 
 1517     /* enable stream-out, with sysmem there is only one pass: */
 1518     OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
 1519     OUT_RING(ring, 0);
 1520 
 1521     OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
 1522     OUT_RING(ring, 0x1);
 1523 
 1524     emit_zs(ring, pfb->zsbuf, NULL);
 1525     emit_mrt(ring, pfb, NULL);
 1526     emit_msaa(ring, pfb->samples);
 1527 
 1528     update_render_cntl(batch, pfb, false);
 1529 }
 1530 
 1531 static void
 1532 fd6_emit_sysmem_fini(struct fd_batch *batch)
 1533 {
 1534     struct fd_ringbuffer *ring = batch->gmem;
 1535 
 1536     OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
 1537     OUT_RING(ring, 0x0);
 1538 
 1539     fd6_emit_lrz_flush(ring);
 1540 
 1541     fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
 1542 }
 1543 
 1544 void
 1545 fd6_gmem_init(struct pipe_context *pctx)
 1546 {
 1547     struct fd_context *ctx = fd_context(pctx);
 1548 
 1549     ctx->emit_tile_init = fd6_emit_tile_init;
 1550     ctx->emit_tile_prep = fd6_emit_tile_prep;
 1551     ctx->emit_tile_mem2gmem = fd6_emit_tile_mem2gmem;
 1552     ctx->emit_tile_renderprep = fd6_emit_tile_renderprep;
 1553     ctx->emit_tile = fd6_emit_tile;
 1554     ctx->emit_tile_gmem2mem = fd6_emit_tile_gmem2mem;
 1555     ctx->emit_tile_fini = fd6_emit_tile_fini;
 1556     ctx->emit_sysmem_prep = fd6_emit_sysmem_prep;
 1557     ctx->emit_sysmem_fini = fd6_emit_sysmem_fini;
 1558 }