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Member "mesa-20.1.8/src/freedreno/registers/adreno_pm4.xml" (16 Sep 2020, 60420 Bytes) of package /linux/misc/mesa-20.1.8.tar.xz:


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    1 <?xml version="1.0" encoding="UTF-8"?>
    2 <database xmlns="http://nouveau.freedesktop.org/"
    3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
    4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
    5 
    6 <enum name="vgt_event_type">
    7     <value name="VS_DEALLOC" value="0"/>
    8     <value name="PS_DEALLOC" value="1"/>
    9     <value name="VS_DONE_TS" value="2"/>
   10     <value name="PS_DONE_TS" value="3"/>
   11     <value name="CACHE_FLUSH_TS" value="4"/>
   12     <value name="CONTEXT_DONE" value="5"/>
   13     <value name="CACHE_FLUSH" value="6"/>
   14     <value name="VIZQUERY_START" value="7" variants="A2XX"/>
   15     <value name="HLSQ_FLUSH" value="7" variants="A3XX,A4XX"/>
   16     <value name="VIZQUERY_END" value="8" variants="A2XX"/>
   17     <value name="SC_WAIT_WC" value="9"/>
   18     <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/>
   19     <value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX"/>
   20     <value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX"/>
   21     <value name="RST_PIX_CNT" value="13"/>
   22     <value name="RST_VTX_CNT" value="14"/>
   23     <value name="TILE_FLUSH" value="15"/>
   24     <value name="STAT_EVENT" value="16"/>
   25     <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX,A3XX,A4XX"/>
   26     <value name="ZPASS_DONE" value="21"/>
   27     <value name="CACHE_FLUSH_AND_INV_EVENT" value="22" variants="A2XX"/>
   28     <value name="RB_DONE_TS" value="22" variants="A3XX-"/>
   29     <value name="PERFCOUNTER_START" value="23" variants="A2XX,A3XX,A4XX"/>
   30     <value name="PERFCOUNTER_STOP" value="24" variants="A2XX,A3XX,A4XX"/>
   31     <value name="VS_FETCH_DONE" value="27"/>
   32     <value name="FACENESS_FLUSH" value="28" variants="A2XX,A3XX,A4XX"/>
   33 
   34     <!-- a5xx events -->
   35     <value name="WT_DONE_TS" value="8" variants="A5XX,A6XX"/>
   36     <value name="FLUSH_SO_0" value="17" variants="A5XX,A6XX"/>
   37     <value name="FLUSH_SO_1" value="18" variants="A5XX,A6XX"/>
   38     <value name="FLUSH_SO_2" value="19" variants="A5XX,A6XX"/>
   39     <value name="FLUSH_SO_3" value="20" variants="A5XX,A6XX"/>
   40     <value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX,A6XX"/>
   41     <value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX,A6XX"/>
   42     <value name="PC_CCU_RESOLVE_TS" value="26" variants="A6XX"/>
   43     <value name="PC_CCU_FLUSH_DEPTH_TS" value="28" variants="A5XX,A6XX"/>
   44     <value name="PC_CCU_FLUSH_COLOR_TS" value="29" variants="A5XX,A6XX"/>
   45     <value name="BLIT" value="30" variants="A5XX,A6XX"/>
   46     <value name="UNK_25" value="37" variants="A5XX"/>
   47     <value name="LRZ_FLUSH" value="38" variants="A5XX,A6XX"/>
   48     <value name="UNK_2C" value="44" variants="A5XX"/>
   49     <value name="UNK_2D" value="45" variants="A5XX"/>
   50 
   51     <!-- a6xx events -->
   52     <value name="CACHE_INVALIDATE" value="49" variants="A6XX"/>
   53 </enum>
   54 
   55 <enum name="pc_di_primtype">
   56     <value name="DI_PT_NONE" value="0"/>
   57     <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: -->
   58     <value name="DI_PT_POINTLIST_PSIZE" value="1"/>
   59     <value name="DI_PT_LINELIST" value="2"/>
   60     <value name="DI_PT_LINESTRIP" value="3"/>
   61     <value name="DI_PT_TRILIST" value="4"/>
   62     <value name="DI_PT_TRIFAN" value="5"/>
   63     <value name="DI_PT_TRISTRIP" value="6"/>
   64     <value name="DI_PT_LINELOOP" value="7"/>  <!-- a22x, a3xx -->
   65     <value name="DI_PT_RECTLIST" value="8"/>
   66     <value name="DI_PT_POINTLIST" value="9"/>
   67     <value name="DI_PT_LINE_ADJ" value="0xa"/>
   68     <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/>
   69     <value name="DI_PT_TRI_ADJ" value="0xc"/>
   70     <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/>
   71 
   72     <value name="DI_PT_PATCHES0" value="0x1f"/>
   73     <value name="DI_PT_PATCHES1" value="0x20"/>
   74     <value name="DI_PT_PATCHES2" value="0x21"/>
   75     <value name="DI_PT_PATCHES3" value="0x22"/>
   76     <value name="DI_PT_PATCHES4" value="0x23"/>
   77     <value name="DI_PT_PATCHES5" value="0x24"/>
   78     <value name="DI_PT_PATCHES6" value="0x25"/>
   79     <value name="DI_PT_PATCHES7" value="0x26"/>
   80     <value name="DI_PT_PATCHES8" value="0x27"/>
   81     <value name="DI_PT_PATCHES9" value="0x28"/>
   82     <value name="DI_PT_PATCHES10" value="0x29"/>
   83     <value name="DI_PT_PATCHES11" value="0x2a"/>
   84     <value name="DI_PT_PATCHES12" value="0x2b"/>
   85     <value name="DI_PT_PATCHES13" value="0x2c"/>
   86     <value name="DI_PT_PATCHES14" value="0x2d"/>
   87     <value name="DI_PT_PATCHES15" value="0x2e"/>
   88     <value name="DI_PT_PATCHES16" value="0x2f"/>
   89     <value name="DI_PT_PATCHES17" value="0x30"/>
   90     <value name="DI_PT_PATCHES18" value="0x31"/>
   91     <value name="DI_PT_PATCHES19" value="0x32"/>
   92     <value name="DI_PT_PATCHES20" value="0x33"/>
   93     <value name="DI_PT_PATCHES21" value="0x34"/>
   94     <value name="DI_PT_PATCHES22" value="0x35"/>
   95     <value name="DI_PT_PATCHES23" value="0x36"/>
   96     <value name="DI_PT_PATCHES24" value="0x37"/>
   97     <value name="DI_PT_PATCHES25" value="0x38"/>
   98     <value name="DI_PT_PATCHES26" value="0x39"/>
   99     <value name="DI_PT_PATCHES27" value="0x3a"/>
  100     <value name="DI_PT_PATCHES28" value="0x3b"/>
  101     <value name="DI_PT_PATCHES29" value="0x3c"/>
  102     <value name="DI_PT_PATCHES30" value="0x3d"/>
  103     <value name="DI_PT_PATCHES31" value="0x3e"/>
  104 </enum>
  105 
  106 <enum name="pc_di_src_sel">
  107     <value name="DI_SRC_SEL_DMA" value="0"/>
  108     <value name="DI_SRC_SEL_IMMEDIATE" value="1"/>
  109     <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/>
  110     <value name="DI_SRC_SEL_RESERVED" value="3"/>
  111 </enum>
  112 
  113 <enum name="pc_di_face_cull_sel">
  114     <value name="DI_FACE_CULL_NONE" value="0"/>
  115     <value name="DI_FACE_CULL_FETCH" value="1"/>
  116     <value name="DI_FACE_BACKFACE_CULL" value="2"/>
  117     <value name="DI_FACE_FRONTFACE_CULL" value="3"/>
  118 </enum>
  119 
  120 <enum name="pc_di_index_size">
  121     <value name="INDEX_SIZE_IGN" value="0"/>
  122     <value name="INDEX_SIZE_16_BIT" value="0"/>
  123     <value name="INDEX_SIZE_32_BIT" value="1"/>
  124     <value name="INDEX_SIZE_8_BIT" value="2"/>
  125     <value name="INDEX_SIZE_INVALID"/>
  126 </enum>
  127 
  128 <enum name="pc_di_vis_cull_mode">
  129     <value name="IGNORE_VISIBILITY" value="0"/>
  130     <value name="USE_VISIBILITY" value="1"/>
  131 </enum>
  132 
  133 <enum name="adreno_pm4_packet_type">
  134     <value name="CP_TYPE0_PKT" value="0x00000000"/>
  135     <value name="CP_TYPE1_PKT" value="0x40000000"/>
  136     <value name="CP_TYPE2_PKT" value="0x80000000"/>
  137     <value name="CP_TYPE3_PKT" value="0xc0000000"/>
  138     <value name="CP_TYPE4_PKT" value="0x40000000"/>
  139     <value name="CP_TYPE7_PKT" value="0x70000000"/>
  140 </enum>
  141 
  142 <!--
  143    Note that in some cases, the same packet id is recycled on a later
  144    generation, so variants attribute is used to distinguish.   They
  145    may not be completely accurate, we would probably have to analyze
  146    the pfp and me/pm4 firmware to verify the packet is actually
  147    handled on a particular generation.  But it is at least enough to
  148    disambiguate the packet-id's that were re-used for different
  149    packets starting with a5xx.
  150  -->
  151 <enum name="adreno_pm4_type3_packets">
  152     <doc>initialize CP's micro-engine</doc>
  153     <value name="CP_ME_INIT" value="0x48"/>
  154     <doc>skip N 32-bit words to get to the next packet</doc>
  155     <value name="CP_NOP" value="0x10"/>
  156     <doc>
  157         indirect buffer dispatch.  prefetch parser uses this packet
  158         type to determine whether to pre-fetch the IB
  159     </doc>
  160     <value name="CP_PREEMPT_ENABLE" value="0x1c"/>
  161     <value name="CP_PREEMPT_TOKEN" value="0x1e"/>
  162     <value name="CP_INDIRECT_BUFFER" value="0x3f"/>
  163     <doc>
  164         Takes the same arguments as CP_INDIRECT_BUFFER, but jumps to
  165         another buffer at the same level. Must be at the end of IB, and
  166         doesn't work with draw state IB's.
  167     </doc>
  168     <value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" variants="A5XX-"/>
  169     <doc>indirect buffer dispatch.  same as IB, but init is pipelined</doc>
  170     <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/>
  171     <doc>wait for the IDLE state of the engine</doc>
  172     <value name="CP_WAIT_FOR_IDLE" value="0x26"/>
  173     <doc>wait until a register or memory location is a specific value</doc>
  174     <value name="CP_WAIT_REG_MEM" value="0x3c"/>
  175     <doc>wait until a register location is equal to a specific value</doc>
  176     <value name="CP_WAIT_REG_EQ" value="0x52"/>
  177     <doc>wait until a register location is >= a specific value</doc>
  178     <value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX,A3XX,A4XX"/>
  179     <doc>wait until a read completes</doc>
  180     <value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX,A3XX,A4XX"/>
  181     <doc>wait until all base/size writes from an IB_PFD packet have completed</doc>
  182     <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d"/>
  183     <doc>register read/modify/write</doc>
  184     <value name="CP_REG_RMW" value="0x21"/>
  185     <doc>Set binning configuration registers</doc>
  186     <value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX,A3XX,A4XX"/>
  187     <value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX,A6XX"/>
  188     <doc>reads register in chip and writes to memory</doc>
  189     <value name="CP_REG_TO_MEM" value="0x3e"/>
  190     <doc>write N 32-bit words to memory</doc>
  191     <value name="CP_MEM_WRITE" value="0x3d"/>
  192     <doc>write CP_PROG_COUNTER value to memory</doc>
  193     <value name="CP_MEM_WRITE_CNTR" value="0x4f"/>
  194     <doc>conditional execution of a sequence of packets</doc>
  195     <value name="CP_COND_EXEC" value="0x44"/>
  196     <doc>conditional write to memory or register</doc>
  197     <value name="CP_COND_WRITE" value="0x45" variants="A2XX,A3XX,A4XX"/>
  198     <value name="CP_COND_WRITE5" value="0x45" variants="A5XX,A6XX"/>
  199     <doc>generate an event that creates a write to memory when completed</doc>
  200     <value name="CP_EVENT_WRITE" value="0x46"/>
  201     <doc>generate a VS|PS_done event</doc>
  202     <value name="CP_EVENT_WRITE_SHD" value="0x58"/>
  203     <doc>generate a cache flush done event</doc>
  204     <value name="CP_EVENT_WRITE_CFL" value="0x59"/>
  205     <doc>generate a z_pass done event</doc>
  206     <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
  207     <doc>
  208         not sure the real name, but this seems to be what is used for
  209         opencl, instead of CP_DRAW_INDX..
  210     </doc>
  211     <value name="CP_RUN_OPENCL" value="0x31"/>
  212     <doc>initiate fetch of index buffer and draw</doc>
  213     <value name="CP_DRAW_INDX" value="0x22"/>
  214     <doc>draw using supplied indices in packet</doc>
  215     <value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX,A3XX,A4XX"/>  <!-- this is something different on a6xx and unused on a5xx -->
  216     <doc>initiate fetch of index buffer and binIDs and draw</doc>
  217     <value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX,A3XX,A4XX"/>
  218     <doc>initiate fetch of bin IDs and draw using supplied indices</doc>
  219     <value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX,A3XX,A4XX"/>
  220     <doc>begin/end initiator for viz query extent processing</doc>
  221     <value name="CP_VIZ_QUERY" value="0x23" variants="A2XX,A3XX,A4XX"/>
  222     <doc>fetch state sub-blocks and initiate shader code DMAs</doc>
  223     <value name="CP_SET_STATE" value="0x25"/>
  224     <doc>load constant into chip and to memory</doc>
  225     <value name="CP_SET_CONSTANT" value="0x2d"/>
  226     <doc>load sequencer instruction memory (pointer-based)</doc>
  227     <value name="CP_IM_LOAD" value="0x27"/>
  228     <doc>load sequencer instruction memory (code embedded in packet)</doc>
  229     <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
  230     <doc>load constants from a location in memory</doc>
  231     <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/>
  232     <doc>selective invalidation of state pointers</doc>
  233     <value name="CP_INVALIDATE_STATE" value="0x3b"/>
  234     <doc>dynamically changes shader instruction memory partition</doc>
  235     <value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX,A3XX,A4XX"/>
  236     <doc>sets the 64-bit BIN_MASK register in the PFP</doc>
  237     <value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX,A3XX,A4XX"/>
  238     <doc>sets the 64-bit BIN_SELECT register in the PFP</doc>
  239     <value name="CP_SET_BIN_SELECT" value="0x51"/>
  240     <doc>updates the current context, if needed</doc>
  241     <value name="CP_CONTEXT_UPDATE" value="0x5e"/>
  242     <doc>generate interrupt from the command stream</doc>
  243     <value name="CP_INTERRUPT" value="0x40"/>
  244     <doc>copy sequencer instruction memory to system memory</doc>
  245     <value name="CP_IM_STORE" value="0x2c" variants="A2XX"/>
  246 
  247     <!-- For a20x -->
  248 <!-- TODO handle variants..
  249     <doc>
  250         Program an offset that will added to the BIN_BASE value of
  251         the 3D_DRAW_INDX_BIN packet
  252     </doc>
  253     <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/>
  254  -->
  255 
  256     <!-- for a22x -->
  257     <doc>
  258         sets draw initiator flags register in PFP, gets bitwise-ORed into
  259         every draw initiator
  260     </doc>
  261     <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/>
  262     <doc>sets the register protection mode</doc>
  263     <value name="CP_SET_PROTECTED_MODE" value="0x5f"/>
  264 
  265     <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/>
  266 
  267     <!-- for a3xx -->
  268     <doc>load high level sequencer command</doc>
  269     <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/>
  270     <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX,A5XX"/>
  271     <doc>Conditionally load a IB based on a flag, prefetch enabled</doc>
  272     <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/>
  273     <doc>Conditionally load a IB based on a flag, prefetch disabled</doc>
  274     <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/>
  275     <doc>Load a buffer with pre-fetch enabled</doc>
  276     <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/>
  277     <doc>Set bin (?)</doc>
  278     <value name="CP_SET_BIN" value="0x4c" variants="A2XX"/>
  279 
  280     <doc>test 2 memory locations to dword values specified</doc>
  281     <value name="CP_TEST_TWO_MEMS" value="0x71"/>
  282 
  283     <doc>Write register, ignoring context state for context sensitive registers</doc>
  284     <value name="CP_REG_WR_NO_CTXT" value="0x78"/>
  285 
  286     <doc>Record the real-time when this packet is processed by PFP</doc>
  287     <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/>
  288 
  289     <!-- Used to switch GPU between secure and non-secure modes -->
  290     <value name="CP_SET_SECURE_MODE" value="0x66"/>
  291 
  292     <doc>PFP waits until the FIFO between the PFP and the ME is empty</doc>
  293     <value name="CP_WAIT_FOR_ME" value="0x13"/>
  294 
  295     <!-- for a4xx -->
  296     <doc>
  297         Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple
  298         groups of registers.  Looks like it can be used to create state
  299         objects in GPU memory, and on state change only emit pointer
  300         (via CP_SET_DRAW_STATE), which should be nice for reducing CPU
  301         overhead:
  302 
  303         (A4x) save PM4 stream pointers to execute upon a visible draw
  304     </doc>
  305     <value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX,A5XX,A6XX"/>
  306     <value name="CP_DRAW_INDX_OFFSET" value="0x38"/>
  307     <value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX,A5XX,A6XX"/>
  308     <value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX,A5XX,A6XX"/>
  309     <value name="CP_DRAW_AUTO" value="0x24"/>
  310 
  311     <value name="CP_UNKNOWN_19" value="0x19"/>
  312 
  313     <doc>set to 1 for fastclear..:</doc>
  314     <value name="CP_UNKNOWN_1A" value="0x1a"/>
  315 
  316     <value name="CP_UNKNOWN_4E" value="0x4e"/>
  317 
  318     <doc>
  319         for A4xx
  320         Write to register with address that does not fit into type-0 pkt
  321     </doc>
  322     <value name="CP_WIDE_REG_WRITE" value="0x74" variants="A4XX"/>
  323 
  324     <doc>copy from ME scratch RAM to a register</doc>
  325     <value name="CP_SCRATCH_TO_REG" value="0x4d"/>
  326 
  327     <doc>Copy from REG to ME scratch RAM</doc>
  328     <value name="CP_REG_TO_SCRATCH" value="0x4a"/>
  329 
  330     <doc>Wait for memory writes to complete</doc>
  331     <value name="CP_WAIT_MEM_WRITES" value="0x12"/>
  332 
  333     <doc>Conditional execution based on register comparison</doc>
  334     <value name="CP_COND_REG_EXEC" value="0x47"/>
  335 
  336     <doc>Memory to REG copy</doc>
  337     <value name="CP_MEM_TO_REG" value="0x42"/>
  338 
  339     <value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX,A5XX,A6XX"/>
  340     <value name="CP_EXEC_CS" value="0x33"/>
  341 
  342     <doc>
  343         for a5xx
  344     </doc>
  345     <value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/>
  346     <!-- switches SMMU pagetable, used on a5xx only -->
  347     <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX,A6XX"/>
  348     <!-- for a6xx -->
  349     <doc>Tells CP the current mode of GPU operation</doc>
  350     <value name="CP_SET_MARKER" value="0x65" variants="A6XX"/>
  351     <doc>Instruct CP to set a few internal CP registers</doc>
  352     <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX"/>
  353     <!--
  354     pairs of regid and value.. seems to be used to program some TF
  355     related regs:
  356      -->
  357     <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX,A6XX"/>
  358     <!-- A5XX Enable yield in RB only -->
  359     <value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/>
  360     <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX,A6XX"/>
  361     <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX,A6XX"/>
  362     <value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX,A6XX"/>
  363     <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX,A6XX"/>
  364     <!-- Enable/Disable/Defer A5x global preemption model -->
  365     <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/>
  366     <!-- Enable/Disable A5x local preemption model -->
  367     <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/>
  368     <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx -->
  369     <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX"/>
  370     <!-- Inform CP about current render mode (needed for a5xx preemption) -->
  371     <value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/>
  372     <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/>
  373     <!-- check if this works on earlier.. -->
  374     <value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX,A6XX"/>
  375     <value name="CP_BLIT" value="0x2c" variants="A5XX,A6XX"/>
  376 
  377     <!-- Test specified bit in specified register and set predicate -->
  378     <value name="CP_REG_TEST" value="0x39" variants="A5XX,A6XX"/>
  379 
  380     <!--
  381     Seems to set the mode flags which control which CP_SET_DRAW_STATE
  382     packets are executed, based on their ENABLE_MASK values
  383     
  384     CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE
  385     packets w/ ENABLE_MASK & 0x6 to execute immediately
  386      -->
  387     <value name="CP_SET_MODE" value="0x63" variants="A6XX"/>
  388 
  389     <!--
  390     Seems like there are now separate blocks of state for VS vs FS/CS
  391     (probably these amounts to geometry vs fragments so that geometry
  392     stage of the pipeline for next draw can start while fragment stage
  393     of current draw is still running.  The format of the payload of the
  394     packets is the same, the only difference is the offsets of the regs
  395     the firmware code that handles the packet writes.
  396 
  397     Note that for CL, starting with a6xx, the preferred # of local
  398     threads is no longer the same as the max, implying that the shader
  399     core can now run warps from unrelated shaders (ie.
  400     CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs
  401     CL_KERNEL_WORK_GROUP_SIZE)
  402      -->
  403     <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX"/>
  404     <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX"/>
  405     <!--
  406     Note: For IBO state (Image/SSBOs) which have shared state across
  407     shader stages, for 3d pipeline CP_LOAD_STATE6 is used.  But for
  408     compute shaders, CP_LOAD_STATE6_FRAG is used.  Possibly they are
  409     interchangable.
  410      -->
  411     <value name="CP_LOAD_STATE6" value="0x36" variants="A6XX"/>
  412 
  413     <!-- internal packets: -->
  414     <value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/>
  415     <value name="IN_SUBBLK_PREFETCH" value="0x1f" variants="A2XX"/>
  416     <value name="IN_INSTR_PREFETCH" value="0x20" variants="A2XX"/>
  417     <value name="IN_INSTR_MATCH" value="0x47" variants="A2XX"/>
  418     <value name="IN_CONST_PREFETCH" value="0x49" variants="A2XX"/>
  419     <value name="IN_INCR_UPDT_STATE" value="0x55" variants="A2XX"/>
  420     <value name="IN_INCR_UPDT_CONST" value="0x56" variants="A2XX"/>
  421     <value name="IN_INCR_UPDT_INSTR" value="0x57" variants="A2XX"/>
  422 
  423     <!-- jmptable entry used to handle type4 packet on a5xx+: -->
  424     <value name="PKT4" value="0x04" variants="A5XX,A6XX"/>
  425 
  426     <!-- TODO do these exist on A5xx? -->
  427     <value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX"/>
  428     <value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX"/>
  429     <value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX"/>
  430     <value name="CP_WAIT_MEM_GTE" value="0x14" variants="A6XX"/>
  431     <value name="CP_WAIT_TWO_REGS" value="0x70" variants="A6XX"/>
  432     <value name="CP_MEMCPY" value="0x75" variants="A6XX"/>
  433     <value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" variants="A6XX"/>
  434     <value name="CP_SET_CTXSWITCH_IB" value="0x55" variants="A6XX"/>
  435 
  436     <!--
  437     Seems to always have the payload:
  438       00000002 00008801 00004010
  439     or:
  440       00000002 00008801 00004090
  441     or:
  442       00000002 00008801 00000010
  443       00000002 00008801 00010010
  444       00000002 00008801 00d64010
  445       ...
  446     Note set for compute shaders..
  447     Is 0x8801 a register offset?
  448     This appears to be a special sort of register write packet
  449     more or less, but the firmware has some special handling..
  450     Seems like it intercepts/modifies certain register offsets,
  451     but others are treated like a normal PKT4 reg write.  I
  452     guess there are some registers that the fw controls certain
  453     bits.
  454      -->
  455     <value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/>
  456 
  457 </enum>
  458 
  459 
  460 <domain name="CP_LOAD_STATE" width="32">
  461     <doc>Load state, a3xx (and later?)</doc>
  462     <enum name="adreno_state_block">
  463         <value name="SB_VERT_TEX" value="0"/>
  464         <value name="SB_VERT_MIPADDR" value="1"/>
  465         <value name="SB_FRAG_TEX" value="2"/>
  466         <value name="SB_FRAG_MIPADDR" value="3"/>
  467         <value name="SB_VERT_SHADER" value="4"/>
  468         <value name="SB_GEOM_SHADER" value="5"/>
  469         <value name="SB_FRAG_SHADER" value="6"/>
  470         <value name="SB_COMPUTE_SHADER" value="7"/>
  471     </enum>
  472     <enum name="adreno_state_type">
  473         <value name="ST_SHADER" value="0"/>
  474         <value name="ST_CONSTANTS" value="1"/>
  475     </enum>
  476     <enum name="adreno_state_src">
  477         <value name="SS_DIRECT" value="0">
  478             <doc>inline with the CP_LOAD_STATE packet</doc>
  479         </value>
  480         <value name="SS_INVALID_ALL_IC" value="2"/>
  481         <value name="SS_INVALID_PART_IC" value="3"/>
  482         <value name="SS_INDIRECT" value="4">
  483             <doc>in buffer pointed to by EXT_SRC_ADDR</doc>
  484         </value>
  485         <value name="SS_INDIRECT_TCM" value="5"/>
  486         <value name="SS_INDIRECT_STM" value="6"/>
  487     </enum>
  488     <reg32 offset="0" name="0">
  489         <bitfield name="DST_OFF" low="0" high="15" type="uint"/>
  490         <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/>
  491         <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/>
  492         <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
  493     </reg32>
  494     <reg32 offset="1" name="1">
  495         <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/>
  496         <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
  497     </reg32>
  498 </domain>
  499 
  500 <domain name="CP_LOAD_STATE4" width="32" varset="chip">
  501     <doc>Load state, a4xx+</doc>
  502     <enum name="a4xx_state_block">
  503         <!--
  504         unknown: 0x7 and 0xf <- seen in compute shader
  505 
  506         STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption?
  507         Seen in some GL shaders.  Payload is NUM_UNIT dwords, and it contains
  508         the gpuaddr of the following shader constants block.  DST_OFF seems
  509         to specify which shader stage:
  510 
  511             16 -> vert
  512             36 -> tcs
  513             56 -> tes
  514             76 -> geom
  515             96 -> frag
  516 
  517         Example:
  518 
  519 opcode: CP_LOAD_STATE4 (30) (12 dwords)
  520         { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 }
  521         { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 }
  522         { EXT_SRC_ADDR_HI = 0 }
  523                         0000: c0264100 00000000 00000000 00000000
  524                 0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000
  525 
  526 opcode: CP_LOAD_STATE4 (30) (4 dwords)
  527         { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
  528         { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 }
  529         { EXT_SRC_ADDR_HI = 0 }
  530                         0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
  531                         0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
  532                         0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000
  533 
  534         STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader.  NUM_UNITS * 2 dwords.
  535 
  536          -->
  537         <value name="SB4_VS_TEX"    value="0x0"/>
  538         <value name="SB4_HS_TEX"    value="0x1"/>    <!-- aka. TCS -->
  539         <value name="SB4_DS_TEX"    value="0x2"/>    <!-- aka. TES -->
  540         <value name="SB4_GS_TEX"    value="0x3"/>
  541         <value name="SB4_FS_TEX"    value="0x4"/>
  542         <value name="SB4_CS_TEX"    value="0x5"/>
  543         <value name="SB4_VS_SHADER" value="0x8"/>
  544         <value name="SB4_HS_SHADER" value="0x9"/>
  545         <value name="SB4_DS_SHADER" value="0xa"/>
  546         <value name="SB4_GS_SHADER" value="0xb"/>
  547         <value name="SB4_FS_SHADER" value="0xc"/>
  548         <value name="SB4_CS_SHADER" value="0xd"/>
  549         <!--
  550         for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each),
  551         STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each)
  552 
  553         Compute has it's own dedicated SSBO state, it seems, but the rest
  554         of the stages share state
  555          -->
  556         <value name="SB4_SSBO"   value="0xe"/>
  557         <value name="SB4_CS_SSBO"   value="0xf"/>
  558     </enum>
  559     <enum name="a4xx_state_type">
  560         <value name="ST4_SHADER" value="0"/>
  561         <value name="ST4_CONSTANTS" value="1"/>
  562         <value name="ST4_UBO" value="2"/>
  563     </enum>
  564     <enum name="a4xx_state_src">
  565         <value name="SS4_DIRECT" value="0"/>
  566         <value name="SS4_INDIRECT" value="2"/>
  567     </enum>
  568     <reg32 offset="0" name="0">
  569         <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
  570         <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/>
  571         <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/>
  572         <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
  573     </reg32>
  574     <reg32 offset="1" name="1">
  575         <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/>
  576         <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
  577     </reg32>
  578     <reg32 offset="2" name="2" variants="A5XX-">
  579         <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
  580     </reg32>
  581 </domain>
  582 
  583 <!-- looks basically same CP_LOAD_STATE4 -->
  584 <domain name="CP_LOAD_STATE6" width="32" varset="chip">
  585     <doc>Load state, a6xx+</doc>
  586     <enum name="a6xx_state_block">
  587         <value name="SB6_VS_TEX"    value="0x0"/>
  588         <value name="SB6_HS_TEX"    value="0x1"/>    <!-- aka. TCS -->
  589         <value name="SB6_DS_TEX"    value="0x2"/>    <!-- aka. TES -->
  590         <value name="SB6_GS_TEX"    value="0x3"/>
  591         <value name="SB6_FS_TEX"    value="0x4"/>
  592         <value name="SB6_CS_TEX"    value="0x5"/>
  593         <value name="SB6_VS_SHADER" value="0x8"/>
  594         <value name="SB6_HS_SHADER" value="0x9"/>
  595         <value name="SB6_DS_SHADER" value="0xa"/>
  596         <value name="SB6_GS_SHADER" value="0xb"/>
  597         <value name="SB6_FS_SHADER" value="0xc"/>
  598         <value name="SB6_CS_SHADER" value="0xd"/>
  599         <value name="SB6_IBO"       value="0xe"/>
  600         <value name="SB6_CS_IBO"    value="0xf"/>
  601     </enum>
  602     <enum name="a6xx_state_type">
  603         <value name="ST6_SHADER" value="0"/>
  604         <value name="ST6_CONSTANTS" value="1"/>
  605         <value name="ST6_UBO" value="2"/>
  606         <value name="ST6_IBO" value="3"/>
  607     </enum>
  608     <enum name="a6xx_state_src">
  609         <value name="SS6_DIRECT" value="0"/>
  610         <value name="SS6_BINDLESS" value="1"/> <!-- TODO does this exist on a4xx/a5xx? -->
  611         <value name="SS6_INDIRECT" value="2"/>
  612     </enum>
  613     <reg32 offset="0" name="0">
  614         <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
  615         <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/>
  616         <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/>
  617         <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/>
  618         <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
  619     </reg32>
  620     <reg32 offset="1" name="1">
  621         <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
  622     </reg32>
  623     <reg32 offset="2" name="2">
  624         <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
  625     </reg32>
  626 </domain>
  627 
  628 <bitset name="vgt_draw_initiator" inline="yes">
  629     <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
  630     <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
  631     <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/>
  632     <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/>
  633     <bitfield name="NOT_EOP" pos="12" type="boolean"/>
  634     <bitfield name="SMALL_INDEX" pos="13" type="boolean"/>
  635     <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/>
  636     <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/>
  637 </bitset>
  638 
  639 <!-- changed on a4xx: -->
  640 <enum name="a4xx_index_size">
  641     <value name="INDEX4_SIZE_8_BIT" value="0"/>
  642     <value name="INDEX4_SIZE_16_BIT" value="1"/>
  643     <value name="INDEX4_SIZE_32_BIT" value="2"/>
  644 </enum>
  645 
  646 <enum name="a6xx_patch_type">
  647   <value name="TESS_QUADS" value="0"/>
  648   <value name="TESS_TRIANGLES" value="1"/>
  649   <value name="TESS_ISOLINES" value="2"/>
  650 </enum>
  651 
  652 <bitset name="vgt_draw_initiator_a4xx" inline="yes">
  653     <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 -->
  654     <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
  655     <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
  656     <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/>
  657     <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/>
  658     <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/>
  659     <bitfield name="GS_ENABLE" pos="16" type="boolean"/>
  660     <bitfield name="TESS_ENABLE" pos="17" type="boolean"/>
  661 </bitset>
  662 
  663 <domain name="CP_DRAW_INDX" width="32">
  664     <reg32 offset="0" name="0">
  665         <bitfield name="VIZ_QUERY" low="0" high="31"/>
  666     </reg32>
  667     <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
  668     <reg32 offset="2" name="2">
  669         <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
  670     </reg32>
  671     <reg32 offset="3" name="3">
  672         <bitfield name="INDX_BASE" low="0" high="31"/>
  673     </reg32>
  674     <reg32 offset="4" name="4">
  675         <bitfield name="INDX_SIZE" low="0" high="31"/>
  676     </reg32>
  677 </domain>
  678 
  679 <domain name="CP_DRAW_INDX_2" width="32">
  680     <reg32 offset="0" name="0">
  681         <bitfield name="VIZ_QUERY" low="0" high="31"/>
  682     </reg32>
  683     <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
  684     <reg32 offset="2" name="2">
  685         <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
  686     </reg32>
  687     <!-- followed by NUM_INDICES indices.. -->
  688 </domain>
  689 
  690 <domain name="CP_DRAW_INDX_OFFSET" width="32">
  691     <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
  692     <reg32 offset="1" name="1">
  693         <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
  694     </reg32>
  695     <reg32 offset="2" name="2">
  696         <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
  697     </reg32>
  698     <reg32 offset="3" name="3">
  699     </reg32>
  700 
  701     <stripe variants="A5XX-">
  702         <reg32 offset="4" name="4">
  703             <bitfield name="INDX_BASE_LO" low="0" high="31"/>
  704         </reg32>
  705         <reg32 offset="5" name="5">
  706             <bitfield name="INDX_BASE_HI" low="0" high="31"/>
  707         </reg32>
  708         <reg32 offset="6" name="6">
  709             <bitfield name="INDX_SIZE" low="0" high="31"/>
  710         </reg32>
  711     </stripe>
  712 
  713     <reg32 offset="4" name="4">
  714         <bitfield name="INDX_BASE" low="0" high="31"/>
  715     </reg32>
  716 
  717     <reg32 offset="5" name="5">
  718         <bitfield name="INDX_SIZE" low="0" high="31"/>
  719     </reg32>
  720 </domain>
  721 
  722 <domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
  723     <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
  724     <reg32 offset="1" name="1">
  725         <bitfield name="INDIRECT" low="0" high="31"/>
  726     </reg32>
  727     <stripe variants="A5XX-">
  728         <reg32 offset="2" name="2">
  729             <bitfield name="INDIRECT_HI" low="0" high="31"/>
  730         </reg32>
  731     </stripe>
  732 </domain>
  733 
  734 <domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
  735     <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
  736     <stripe variants="A4XX">
  737         <reg32 offset="1" name="1">
  738             <bitfield name="INDX_BASE" low="0" high="31"/>
  739         </reg32>
  740         <reg32 offset="2" name="2">
  741             <!-- max # of bytes in index buffer -->
  742             <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
  743         </reg32>
  744         <reg32 offset="3" name="3">
  745             <bitfield name="INDIRECT" low="0" high="31"/>
  746         </reg32>
  747     </stripe>
  748     <stripe variants="A5XX-">
  749         <reg32 offset="1" name="1">
  750             <bitfield name="INDX_BASE_LO" low="0" high="31"/>
  751         </reg32>
  752         <reg32 offset="2" name="2">
  753             <bitfield name="INDX_BASE_HI" low="0" high="31"/>
  754         </reg32>
  755         <reg32 offset="3" name="3">
  756             <!-- max # of elements in index buffer -->
  757             <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/>
  758         </reg32>
  759         <reg32 offset="4" name="4">
  760             <bitfield name="INDIRECT_LO" low="0" high="31"/>
  761         </reg32>
  762         <reg32 offset="5" name="5">
  763             <bitfield name="INDIRECT_HI" low="0" high="31"/>
  764         </reg32>
  765     </stripe>
  766 </domain>
  767 
  768 <domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-">
  769     <array offset="0" name="" stride="3" length="100">
  770         <reg32 offset="0" name="0">
  771             <bitfield name="COUNT" low="0" high="15" type="uint"/>
  772             <bitfield name="DIRTY" pos="16" type="boolean"/>
  773             <bitfield name="DISABLE" pos="17" type="boolean"/>
  774             <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/>
  775             <bitfield name="LOAD_IMMED" pos="19" type="boolean"/>
  776             <bitfield name="BINNING" pos="20" variants="A6XX-" type="boolean"/>
  777             <bitfield name="GMEM" pos="21" variants="A6XX-" type="boolean"/>
  778             <bitfield name="SYSMEM" pos="22" variants="A6XX-" type="boolean"/>
  779             <bitfield name="GROUP_ID" low="24" high="28" type="uint"/>
  780         </reg32>
  781         <reg32 offset="1" name="1">
  782             <bitfield name="ADDR_LO" low="0" high="31" type="hex"/>
  783         </reg32>
  784         <reg32 offset="2" name="2" variants="A5XX-">
  785             <bitfield name="ADDR_HI" low="0" high="31" type="hex"/>
  786         </reg32>
  787     </array>
  788 </domain>
  789 
  790 <domain name="CP_SET_BIN" width="32">
  791     <doc>value at offset 0 always seems to be 0x00000000..</doc>
  792     <reg32 offset="0" name="0"/>
  793     <reg32 offset="1" name="1">
  794         <bitfield name="X1" low="0" high="15" type="uint"/>
  795         <bitfield name="Y1" low="16" high="31" type="uint"/>
  796     </reg32>
  797     <reg32 offset="2" name="2">
  798         <bitfield name="X2" low="0" high="15" type="uint"/>
  799         <bitfield name="Y2" low="16" high="31" type="uint"/>
  800     </reg32>
  801 </domain>
  802 
  803 <domain name="CP_SET_BIN_DATA" width="32">
  804     <reg32 offset="0" name="0">
  805         <!-- corresponds to VSC_PIPE[n].DATA_ADDR -->
  806         <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/>
  807     </reg32>
  808     <reg32 offset="1" name="1">
  809         <!-- seesm to correspond to VSC_SIZE_ADDRESS -->
  810         <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/>
  811     </reg32>
  812 </domain>
  813 
  814 <domain name="CP_SET_BIN_DATA5" width="32">
  815     <reg32 offset="0" name="0">
  816         <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
  817         <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
  818         <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
  819         <bitfield name="VSC_N" low="22" high="26" type="uint"/>
  820     </reg32>
  821     <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
  822     <reg32 offset="1" name="1">
  823         <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
  824     </reg32>
  825     <reg32 offset="2" name="2">
  826         <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
  827     </reg32>
  828     <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
  829     <reg32 offset="3" name="3">
  830         <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
  831     </reg32>
  832     <reg32 offset="4" name="4">
  833         <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
  834     </reg32>
  835     <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: -->
  836     <reg32 offset="5" name="5">
  837         <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/>
  838     </reg32>
  839     <reg32 offset="6" name="6">
  840         <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/>
  841     </reg32>
  842 </domain>
  843 
  844 <domain name="CP_SET_BIN_DATA5_OFFSET" width="32">
  845     <doc>
  846                 Like CP_SET_BIN_DATA5, but set the pointers as offsets from the
  847                 pointers stored in VSC_PIPE_{DATA,DATA2,SIZE}_ADDRESS. Useful
  848                 for Vulkan where these values aren't known when the command
  849                 stream is recorded.
  850     </doc>
  851     <reg32 offset="0" name="0">
  852         <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
  853         <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
  854         <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
  855         <bitfield name="VSC_N" low="22" high="26" type="uint"/>
  856     </reg32>
  857     <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
  858     <reg32 offset="1" name="1">
  859         <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/>
  860     </reg32>
  861     <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
  862     <reg32 offset="2" name="2">
  863         <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/>
  864     </reg32>
  865     <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS -->
  866     <reg32 offset="3" name="3">
  867         <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/>
  868     </reg32>
  869 </domain>
  870 
  871 <domain name="CP_REG_RMW" width="32">
  872     <doc>
  873                 Modifies DST_REG using two sources that can either be registers
  874                 or immediates. If SRC1_ADD is set, then do the following:
  875 
  876             $dst = (($dst &amp; $src0) rot $rotate) + $src1
  877 
  878         Otherwise:
  879 
  880             $dst = (($dst &amp; $src0) rot $rotate) | $src1
  881 
  882         Here "rot" means rotate left.
  883     </doc>
  884     <reg32 offset="0" name="0">
  885         <bitfield name="DST_REG" low="0" high="17" type="hex"/>
  886         <bitfield name="ROTATE" low="24" high="28" type="uint"/>
  887         <bitfield name="SRC1_ADD" pos="29" type="boolean"/>
  888         <bitfield name="SRC1_IS_REG" pos="30" type="boolean"/>
  889         <bitfield name="SRC0_IS_REG" pos="31" type="boolean"/>
  890     </reg32>
  891     <reg32 offset="1" name="1">
  892         <bitfield name="SRC0" low="0" high="31" type="uint"/>
  893     </reg32>
  894     <reg32 offset="2" name="2">
  895         <bitfield name="SRC1" low="0" high="31" type="uint"/>
  896     </reg32>
  897 </domain>
  898 
  899 <domain name="CP_REG_TO_MEM" width="32">
  900     <reg32 offset="0" name="0">
  901         <bitfield name="REG" low="0" high="15" type="hex"/>
  902         <!-- number of registers/dwords copied is max(CNT, 1). -->
  903         <bitfield name="CNT" low="18" high="29" type="uint"/>
  904         <bitfield name="64B" pos="30" type="boolean"/>
  905         <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
  906     </reg32>
  907     <reg32 offset="1" name="1">
  908         <bitfield name="DEST" low="0" high="31"/>
  909     </reg32>
  910     <reg32 offset="2" name="2" variants="A5XX-">
  911         <bitfield name="DEST_HI" low="0" high="31"/>
  912     </reg32>
  913 </domain>
  914 
  915 <domain name="CP_REG_TO_MEM_OFFSET_REG" width="32">
  916     <doc>
  917                 Like CP_REG_TO_MEM, but the memory address to write to can be
  918                 offsetted using either one or two registers or scratch
  919                 registers.
  920     </doc>
  921     <reg32 offset="0" name="0">
  922         <bitfield name="REG" low="0" high="15" type="hex"/>
  923         <!-- number of registers/dwords copied is max(CNT, 1). -->
  924         <bitfield name="CNT" low="18" high="29" type="uint"/>
  925         <bitfield name="64B" pos="30" type="boolean"/>
  926         <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
  927     </reg32>
  928     <reg32 offset="1" name="1">
  929         <bitfield name="DEST" low="0" high="31"/>
  930     </reg32>
  931     <reg32 offset="2" name="2" variants="A5XX-">
  932         <bitfield name="DEST_HI" low="0" high="31"/>
  933     </reg32>
  934     <reg32 offset="3" name="3">
  935         <bitfield name="OFFSET0" low="0" high="17" type="hex"/>
  936         <bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/>
  937     </reg32>
  938     <!-- followed by an optional identical OFFSET1 dword -->
  939 </domain>
  940 
  941 <domain name="CP_REG_TO_MEM_OFFSET_MEM" width="32">
  942     <doc>
  943                 Like CP_REG_TO_MEM, but the memory address to write to can be
  944                 offsetted using a DWORD in memory.
  945     </doc>
  946     <reg32 offset="0" name="0">
  947         <bitfield name="REG" low="0" high="15" type="hex"/>
  948         <!-- number of registers/dwords copied is max(CNT, 1). -->
  949         <bitfield name="CNT" low="18" high="29" type="uint"/>
  950         <bitfield name="64B" pos="30" type="boolean"/>
  951         <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
  952     </reg32>
  953     <reg32 offset="1" name="1">
  954         <bitfield name="DEST" low="0" high="31"/>
  955     </reg32>
  956     <reg32 offset="2" name="2" variants="A5XX-">
  957         <bitfield name="DEST_HI" low="0" high="31"/>
  958     </reg32>
  959     <reg32 offset="3" name="3">
  960         <bitfield name="OFFSET_LO" low="0" high="31" type="hex"/>
  961     </reg32>
  962     <reg32 offset="4" name="4">
  963         <bitfield name="OFFSET_HI" low="0" high="31" type="hex"/>
  964     </reg32>
  965 </domain>
  966 
  967 <domain name="CP_MEM_TO_REG" width="32">
  968     <reg32 offset="0" name="0">
  969         <bitfield name="REG" low="0" high="15" type="hex"/>
  970         <!-- number of registers/dwords copied is max(CNT, 1). -->
  971         <bitfield name="CNT" low="19" high="29" type="uint"/>
  972         <!-- shift each DWORD left by 2 while copying -->
  973         <bitfield name="SHIFT_BY_2" pos="30" type="boolean"/>
  974         <!-- does the same thing as CP_MEM_TO_MEM::UNK31 -->
  975         <bitfield name="UNK31" pos="31" type="boolean"/>
  976     </reg32>
  977     <reg32 offset="1" name="1">
  978         <bitfield name="SRC" low="0" high="31"/>
  979     </reg32>
  980     <reg32 offset="2" name="2" variants="A5XX-">
  981         <bitfield name="SRC_HI" low="0" high="31"/>
  982     </reg32>
  983 </domain>
  984 
  985 <domain name="CP_MEM_TO_MEM" width="32">
  986     <reg32 offset="0" name="0">
  987         <!--
  988         not sure how many src operands we have, but the low
  989         bits negate the n'th src argument.
  990          -->
  991         <bitfield name="NEG_A" pos="0" type="boolean"/>
  992         <bitfield name="NEG_B" pos="1" type="boolean"/>
  993         <bitfield name="NEG_C" pos="2" type="boolean"/>
  994 
  995         <!-- if set treat src/dst as 64bit values -->
  996         <bitfield name="DOUBLE" pos="29" type="boolean"/>
  997         <!-- execute CP_WAIT_FOR_MEM_WRITES beforehand -->
  998         <bitfield name="WAIT_FOR_MEM_WRITES" pos="30" type="boolean"/>
  999         <!-- some other kind of wait -->
 1000         <bitfield name="UNK31" pos="31" type="boolean"/>
 1001     </reg32>
 1002     <!--
 1003     followed by sequence of addresses.. the first is the
 1004     destination and the rest are N src addresses which are
 1005     summed (after being negated if NEG_x bit set) allowing
 1006     to do things like 'result += end - start' (which turns
 1007     out to be useful for queries and accumulating results
 1008     across multiple tiles)
 1009      -->
 1010 </domain>
 1011 
 1012 <domain name="CP_MEMCPY" width="32">
 1013     <reg32 offset="0" name="0">
 1014         <bitfield name="DWORDS" low="0" high="31" type="uint"/>
 1015     </reg32>
 1016     <reg32 offset="1" name="1">
 1017         <bitfield name="SRC_LO" low="0" high="31" type="hex"/>
 1018     </reg32>
 1019     <reg32 offset="2" name="2">
 1020         <bitfield name="SRC_HI" low="0" high="31" type="hex"/>
 1021     </reg32>
 1022     <reg32 offset="3" name="3">
 1023         <bitfield name="DST_LO" low="0" high="31" type="hex"/>
 1024     </reg32>
 1025     <reg32 offset="4" name="4">
 1026         <bitfield name="DST_HI" low="0" high="31" type="hex"/>
 1027     </reg32>
 1028 </domain>
 1029 
 1030 <domain name="CP_REG_TO_SCRATCH" width="32">
 1031     <reg32 offset="0" name="0">
 1032         <bitfield name="REG" low="0" high="17" type="hex"/>
 1033         <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
 1034         <!-- number of registers/dwords copied is CNT + 1. -->
 1035         <bitfield name="CNT" low="24" high="26" type="uint"/>
 1036     </reg32>
 1037 </domain>
 1038 
 1039 <domain name="CP_SCRATCH_TO_REG" width="32">
 1040     <reg32 offset="0" name="0">
 1041         <bitfield name="REG" low="0" high="17" type="hex"/>
 1042         <!-- note: CP_MEM_TO_REG always sets this when writing to the register -->
 1043         <bitfield name="UNK18" pos="18" type="boolean"/>
 1044         <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
 1045         <!-- number of registers/dwords copied is CNT + 1. -->
 1046         <bitfield name="CNT" low="24" high="26" type="uint"/>
 1047     </reg32>
 1048 </domain>
 1049 
 1050 <domain name="CP_SCRATCH_WRITE" width="32">
 1051     <reg32 offset="0" name="0">
 1052         <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
 1053     </reg32>
 1054     <!-- followed by one or more DWORDs to write to scratch registers -->
 1055 </domain>
 1056 
 1057 <domain name="CP_MEM_WRITE" width="32">
 1058     <reg32 offset="0" name="0">
 1059         <bitfield name="ADDR_LO" low="0" high="31"/>
 1060     </reg32>
 1061     <reg32 offset="1" name="1">
 1062         <bitfield name="ADDR_HI" low="0" high="31"/>
 1063     </reg32>
 1064     <!-- followed by the DWORDs to write -->
 1065 </domain>
 1066 
 1067 <enum name="cp_cond_function">
 1068     <value value="0" name="WRITE_ALWAYS"/>
 1069     <value value="1" name="WRITE_LT"/>
 1070     <value value="2" name="WRITE_LE"/>
 1071     <value value="3" name="WRITE_EQ"/>
 1072     <value value="4" name="WRITE_NE"/>
 1073     <value value="5" name="WRITE_GE"/>
 1074     <value value="6" name="WRITE_GT"/>
 1075 </enum>
 1076 
 1077 <domain name="CP_COND_WRITE" width="32">
 1078     <reg32 offset="0" name="0">
 1079         <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
 1080         <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
 1081         <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
 1082     </reg32>
 1083     <reg32 offset="1" name="1">
 1084         <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/>
 1085     </reg32>
 1086     <reg32 offset="2" name="2">
 1087         <bitfield name="REF" low="0" high="31"/>
 1088     </reg32>
 1089     <reg32 offset="3" name="3">
 1090         <bitfield name="MASK" low="0" high="31"/>
 1091     </reg32>
 1092     <reg32 offset="4" name="4">
 1093         <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/>
 1094     </reg32>
 1095     <reg32 offset="5" name="5">
 1096         <bitfield name="WRITE_DATA" low="0" high="31"/>
 1097     </reg32>
 1098 </domain>
 1099 
 1100 <domain name="CP_COND_WRITE5" width="32">
 1101     <reg32 offset="0" name="0">
 1102         <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
 1103         <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
 1104                 <!-- if both POLL_MEMORY and POLL_SCRATCH are false, it polls a register at POLL_ADDR_LO instead. -->
 1105         <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
 1106         <bitfield name="POLL_SCRATCH" pos="5" type="boolean"/>
 1107         <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
 1108     </reg32>
 1109     <reg32 offset="1" name="1">
 1110         <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
 1111     </reg32>
 1112     <reg32 offset="2" name="2">
 1113         <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
 1114     </reg32>
 1115     <reg32 offset="3" name="3">
 1116         <bitfield name="REF" low="0" high="31"/>
 1117     </reg32>
 1118     <reg32 offset="4" name="4">
 1119         <bitfield name="MASK" low="0" high="31"/>
 1120     </reg32>
 1121     <reg32 offset="5" name="5">
 1122         <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/>
 1123     </reg32>
 1124     <reg32 offset="6" name="6">
 1125         <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/>
 1126     </reg32>
 1127     <reg32 offset="7" name="7">
 1128         <bitfield name="WRITE_DATA" low="0" high="31"/>
 1129     </reg32>
 1130 </domain>
 1131 
 1132 <domain name="CP_WAIT_MEM_GTE" width="32">
 1133         <doc>
 1134                 Wait until a memory value is greater than or equal to the
 1135                 reference, using signed comparison.
 1136     </doc>
 1137     <reg32 offset="0" name="0">
 1138         <!-- Reserved for flags, presumably? Unused in FW -->
 1139         <bitfield name="RESERVED" low="0" high="31" type="hex"/>
 1140     </reg32>
 1141     <reg32 offset="1" name="1">
 1142         <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
 1143     </reg32>
 1144     <reg32 offset="2" name="2">
 1145         <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
 1146     </reg32>
 1147     <reg32 offset="3" name="3">
 1148         <bitfield name="REF" low="0" high="31"/>
 1149     </reg32>
 1150 </domain>
 1151 
 1152 <domain name="CP_WAIT_REG_MEM" width="32">
 1153         <doc>
 1154                 This uses the same internal comparison as CP_COND_WRITE,
 1155                 but waits until the comparison is true instead. It busy-loops in
 1156                 the CP for the given number of cycles before trying again.
 1157     </doc>
 1158     <reg32 offset="0" name="0">
 1159         <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
 1160         <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
 1161         <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
 1162         <bitfield name="POLL_SCRATCH" pos="5" type="boolean"/>
 1163         <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
 1164     </reg32>
 1165     <reg32 offset="1" name="1">
 1166         <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
 1167     </reg32>
 1168     <reg32 offset="2" name="2">
 1169         <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
 1170     </reg32>
 1171     <reg32 offset="3" name="3">
 1172         <bitfield name="REF" low="0" high="31"/>
 1173     </reg32>
 1174     <reg32 offset="4" name="4">
 1175         <bitfield name="MASK" low="0" high="31"/>
 1176     </reg32>
 1177     <reg32 offset="5" name="5">
 1178         <bitfield name="DELAY_LOOP_CYCLES" low="0" high="31"/>
 1179     </reg32>
 1180 </domain>
 1181 
 1182 <domain name="CP_WAIT_TWO_REGS" width="32">
 1183     <doc>
 1184         Waits for REG0 to not be 0 or REG1 to not equal REF
 1185     </doc>
 1186     <reg32 offset="0" name="0">
 1187         <bitfield name="REG0" low="0" high="17" type="hex"/>
 1188     </reg32>
 1189     <reg32 offset="1" name="1">
 1190         <bitfield name="REG1" low="0" high="17" type="hex"/>
 1191     </reg32>
 1192     <reg32 offset="2" name="2">
 1193         <bitfield name="REF" low="0" high="31" type="uint"/>
 1194     </reg32>
 1195 </domain>
 1196 
 1197 <domain name="CP_DISPATCH_COMPUTE" width="32">
 1198     <reg32 offset="0" name="0"/>
 1199     <reg32 offset="1" name="1">
 1200         <bitfield name="X" low="0" high="31"/>
 1201     </reg32>
 1202     <reg32 offset="2" name="2">
 1203         <bitfield name="Y" low="0" high="31"/>
 1204     </reg32>
 1205     <reg32 offset="3" name="3">
 1206         <bitfield name="Z" low="0" high="31"/>
 1207     </reg32>
 1208 </domain>
 1209 
 1210 <domain name="CP_SET_RENDER_MODE" width="32">
 1211     <enum name="render_mode_cmd">
 1212         <value value="1" name="BYPASS"/>
 1213         <value value="2" name="BINNING"/>
 1214         <value value="3" name="GMEM"/>
 1215         <value value="5" name="BLIT2D"/>
 1216         <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? -->
 1217         <value value="7" name="BLIT2DSCALE"/>
 1218         <!-- 8 set before going back to BYPASS exiting 2D -->
 1219         <value value="8" name="END2D"/>
 1220     </enum>
 1221     <reg32 offset="0" name="0">
 1222         <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/>
 1223         <!--
 1224         normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in
 1225         0x21xx range.. possibly (at least some) a5xx variants have a
 1226         2d core?
 1227          -->
 1228     </reg32>
 1229     <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
 1230     <reg32 offset="1" name="1">
 1231         <bitfield name="ADDR_0_LO" low="0" high="31"/>
 1232     </reg32>
 1233     <reg32 offset="2" name="2">
 1234         <bitfield name="ADDR_0_HI" low="0" high="31"/>
 1235     </reg32>
 1236     <reg32 offset="3" name="3">
 1237         <!--
 1238         set when in GMEM.. maybe indicates GMEM contents need to be
 1239         preserved on ctx switch?
 1240          -->
 1241         <bitfield name="VSC_ENABLE" pos="3" type="boolean"/>
 1242         <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/>
 1243     </reg32>
 1244     <reg32 offset="4" name="4"/>
 1245     <!-- second buffer looks like some cmdstream.. length in dwords: -->
 1246     <reg32 offset="5" name="5">
 1247         <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
 1248     </reg32>
 1249     <reg32 offset="6" name="6">
 1250         <bitfield name="ADDR_1_LO" low="0" high="31"/>
 1251     </reg32>
 1252     <reg32 offset="7" name="7">
 1253         <bitfield name="ADDR_1_HI" low="0" high="31"/>"
 1254     </reg32>
 1255 </domain>
 1256 
 1257 <!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword -->
 1258 <domain name="CP_COMPUTE_CHECKPOINT" width="32">
 1259     <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
 1260     <reg32 offset="0" name="0">
 1261         <bitfield name="ADDR_0_LO" low="0" high="31"/>
 1262     </reg32>
 1263     <reg32 offset="1" name="1">
 1264         <bitfield name="ADDR_0_HI" low="0" high="31"/>
 1265     </reg32>
 1266     <reg32 offset="2" name="2">
 1267     </reg32>
 1268     <!-- second buffer looks like some cmdstream.. length in dwords: -->
 1269     <reg32 offset="3" name="3">
 1270         <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
 1271     </reg32>
 1272     <reg32 offset="4" name="4"/>
 1273     <reg32 offset="5" name="5">
 1274         <bitfield name="ADDR_1_LO" low="0" high="31"/>
 1275     </reg32>
 1276     <reg32 offset="6" name="6">
 1277         <bitfield name="ADDR_1_HI" low="0" high="31"/>"
 1278     </reg32>
 1279     <reg32 offset="7" name="7"/>
 1280 </domain>
 1281 
 1282 <domain name="CP_PERFCOUNTER_ACTION" width="32">
 1283     <reg32 offset="0" name="0">
 1284     </reg32>
 1285     <reg32 offset="1" name="1">
 1286         <bitfield name="ADDR_0_LO" low="0" high="31"/>
 1287     </reg32>
 1288     <reg32 offset="2" name="2">
 1289         <bitfield name="ADDR_0_HI" low="0" high="31"/>
 1290     </reg32>
 1291 </domain>
 1292 
 1293 <domain name="CP_EVENT_WRITE" width="32">
 1294     <reg32 offset="0" name="0">
 1295         <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
 1296         <!-- when set, write back timestamp instead of value from packet: -->
 1297         <bitfield name="TIMESTAMP" pos="30" type="boolean"/>
 1298     </reg32>
 1299     <!--
 1300     TODO what is gpuaddr for, seems to be all 0's.. maybe needed for
 1301     context switch?
 1302      -->
 1303     <reg32 offset="1" name="1">
 1304         <bitfield name="ADDR_0_LO" low="0" high="31"/>
 1305     </reg32>
 1306     <reg32 offset="2" name="2">
 1307         <bitfield name="ADDR_0_HI" low="0" high="31"/>
 1308     </reg32>
 1309     <reg32 offset="3" name="3">
 1310         <!-- ??? -->
 1311     </reg32>
 1312 </domain>
 1313 
 1314 <domain name="CP_BLIT" width="32">
 1315     <enum name="cp_blit_cmd">
 1316         <value value="0" name="BLIT_OP_FILL"/>
 1317         <value value="1" name="BLIT_OP_COPY"/>
 1318         <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation -->
 1319     </enum>
 1320     <reg32 offset="0" name="0">
 1321         <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/>
 1322     </reg32>
 1323     <reg32 offset="1" name="1">
 1324         <bitfield name="SRC_X1" low="0" high="13" type="uint"/>
 1325         <bitfield name="SRC_Y1" low="16" high="29" type="uint"/>
 1326     </reg32>
 1327     <reg32 offset="2" name="2">
 1328         <bitfield name="SRC_X2" low="0" high="13" type="uint"/>
 1329         <bitfield name="SRC_Y2" low="16" high="29" type="uint"/>
 1330     </reg32>
 1331     <reg32 offset="3" name="3">
 1332         <bitfield name="DST_X1" low="0" high="13" type="uint"/>
 1333         <bitfield name="DST_Y1" low="16" high="29" type="uint"/>
 1334     </reg32>
 1335     <reg32 offset="4" name="4">
 1336         <bitfield name="DST_X2" low="0" high="13" type="uint"/>
 1337         <bitfield name="DST_Y2" low="16" high="29" type="uint"/>
 1338     </reg32>
 1339 </domain>
 1340 
 1341 <domain name="CP_EXEC_CS" width="32">
 1342     <reg32 offset="0" name="0">
 1343     </reg32>
 1344     <reg32 offset="1" name="1">
 1345         <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/>
 1346     </reg32>
 1347     <reg32 offset="2" name="2">
 1348         <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/>
 1349     </reg32>
 1350     <reg32 offset="3" name="3">
 1351         <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/>
 1352     </reg32>
 1353 </domain>
 1354 
 1355 <domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
 1356     <reg32 offset="0" name="0">
 1357     </reg32>
 1358     <stripe variants="A4XX">
 1359         <reg32 offset="1" name="1">
 1360             <bitfield name="ADDR" low="0" high="31"/>
 1361         </reg32>
 1362         <reg32 offset="2" name="2">
 1363             <!-- localsize is value minus one: -->
 1364             <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
 1365             <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
 1366             <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
 1367         </reg32>
 1368     </stripe>
 1369     <stripe variants="A5XX-">
 1370         <reg32 offset="1" name="1">
 1371             <bitfield name="ADDR_LO" low="0" high="31"/>
 1372         </reg32>
 1373         <reg32 offset="2" name="2">
 1374             <bitfield name="ADDR_HI" low="0" high="31"/>
 1375         </reg32>
 1376         <reg32 offset="3" name="3">
 1377             <!-- localsize is value minus one: -->
 1378             <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
 1379             <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
 1380             <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
 1381         </reg32>
 1382     </stripe>
 1383 </domain>
 1384 
 1385 <domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
 1386     <doc>Tell CP the current operation mode, indicates save and restore procedure</doc>
 1387     <enum name="a6xx_render_mode">
 1388         <value value="1" name="RM6_BYPASS"/>
 1389         <value value="2" name="RM6_BINNING"/>
 1390         <value value="4" name="RM6_GMEM"/>
 1391         <value value="5" name="RM6_ENDVIS"/>
 1392         <value value="6" name="RM6_RESOLVE"/>
 1393         <value value="7" name="RM6_YIELD"/>
 1394         <value value="8" name="RM6_COMPUTE"/>
 1395         <value value="0xc" name="RM6_BLIT2DSCALE"/>  <!-- no-op (at least on current sqe fw) -->
 1396 
 1397         <!--
 1398             These values come from a6xx_set_marker() in the
 1399             downstream kernel, and they can only be set by the kernel
 1400         -->
 1401         <value value="0xd" name="RM6_IB1LIST_START"/>
 1402         <value value="0xe" name="RM6_IB1LIST_END"/>
 1403         <!-- IFPC - inter-frame power collapse -->
 1404         <value value="0x100" name="RM6_IFPC_ENABLE"/>
 1405         <value value="0x101" name="RM6_IFPC_DISABLE"/>
 1406     </enum>
 1407     <reg32 offset="0" name="0">
 1408         <!--
 1409             NOTE: blob driver and some versions of freedreno/turnip set
 1410             b4, which is unused (at least by current sqe fw), but interferes
 1411             with parsing if we extend the size of the bitfield to include
 1412             b8 (only sent by kernel mode driver).  Really, the way the
 1413             parsing works in the firmware, only b0-b3 are considered, but
 1414             if b8 is set, the low bits are interpreted differently.  To
 1415             model this, without getting confused by spurious b4, this is
 1416             described as two overlapping bitfields:
 1417          -->
 1418         <bitfield name="MODE" low="0" high="8" type="a6xx_render_mode"/>
 1419         <bitfield name="MARKER" low="0" high="3" type="a6xx_render_mode"/>
 1420     </reg32>
 1421 </domain>
 1422 
 1423 <domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
 1424     <doc>Set internal CP registers, used to indicate context save data addresses</doc>
 1425     <enum name="pseudo_reg">
 1426         <value value="0" name="SMMU_INFO"/>
 1427         <value value="1" name="NON_SECURE_SAVE_ADDR"/>
 1428         <value value="2" name="SECURE_SAVE_ADDR"/>
 1429         <value value="3" name="NON_PRIV_SAVE_ADDR"/>
 1430         <value value="4" name="COUNTER"/>
 1431     </enum>
 1432     <array offset="0" name="" stride="3" length="100">
 1433         <reg32 offset="0" name="0">
 1434             <bitfield name="PSEUDO_REG" low="0" high="2" type="pseudo_reg"/>
 1435         </reg32>
 1436         <reg32 offset="1" name="1">
 1437             <bitfield name="LO" low="0" high="31"/>
 1438         </reg32>
 1439         <reg32 offset="2" name="2">
 1440             <bitfield name="HI" low="0" high="31"/>
 1441         </reg32>
 1442     </array>
 1443 </domain>
 1444 
 1445 <domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-">
 1446     <doc>
 1447         Tests bit in specified register and sets predicate for CP_COND_REG_EXEC.
 1448         So:
 1449 
 1450             opcode: CP_REG_TEST (39) (2 dwords)
 1451                     { REG = 0xc10 | BIT = 0 }
 1452                            0000: 70b90001 00000c10
 1453             opcode: CP_COND_REG_EXEC (47) (3 dwords)
 1454                            0000: 70c70002 10000000 00000004
 1455             opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
 1456 
 1457         Will execute the CP_INDIRECT_BUFFER only if b0 in the register at
 1458         offset 0x0c10 is 1
 1459     </doc>
 1460     <reg32 offset="0" name="0">
 1461         <!-- the register to test -->
 1462         <bitfield name="REG" low="0" high="11"/>
 1463         <!-- the bit to test -->
 1464         <bitfield name="BIT" low="20" high="24" type="uint"/>
 1465         <!-- execute CP_WAIT_FOR_ME beforehand -->
 1466         <bitfield name="WAIT_FOR_ME" pos="25" type="boolean"/>
 1467     </reg32>
 1468 </domain>
 1469 
 1470 <!-- I *think* this existed at least as far back as a4xx -->
 1471 <domain name="CP_COND_REG_EXEC" width="32">
 1472     <enum name="compare_mode">
 1473         <!-- use the predicate bit set by CP_REG_TEST -->
 1474         <value value="1" name="PRED_TEST"/>
 1475         <!-- compare two registers directly for equality -->
 1476         <value value="2" name="REG_COMPARE"/>
 1477         <!-- test if certain render modes are set via CP_SET_MARKER -->
 1478         <value value="3" name="RENDER_MODE" variants="A6XX-"/>
 1479     </enum>
 1480     <reg32 offset="0" name="0">
 1481         <bitfield name="REG0" low="0" high="17" type="hex"/>
 1482 
 1483         <!--
 1484             Note: these bits have the same meaning, and use the same
 1485             internal mechanism as the bits in CP_SET_DRAW_STATE.
 1486             When RENDER_MODE is selected, they're used as
 1487             a bitmask of which modes pass the test.
 1488         -->
 1489 
 1490         <!-- RM6_BINNING -->
 1491         <bitfield name="BINNING" pos="25" variants="A6XX-" type="boolean"/>
 1492         <!-- all others -->
 1493         <bitfield name="GMEM" pos="26" variants="A6XX-" type="boolean"/>
 1494         <!-- RM6_BYPASS -->
 1495         <bitfield name="SYSMEM" pos="27" variants="A6XX-" type="boolean"/>
 1496 
 1497         <bitfield name="MODE" low="28" high="31" type="compare_mode"/>
 1498     </reg32>
 1499 
 1500     <!-- in REG_COMPARE mode, there's an extra DWORD here with REG1 -->
 1501 
 1502     <reg32 offset="1" name="1">
 1503         <bitfield name="DWORDS" low="0" high="31" type="uint"/>
 1504     </reg32>
 1505 </domain>
 1506 
 1507 <domain name="CP_COND_EXEC" width="32">
 1508     <doc>
 1509                 Executes the following DWORDs of commands if the dword at ADDR0
 1510                 is not equal to 0 and the dword at ADDR1 is less than REF
 1511                 (signed comparison).
 1512     </doc>
 1513     <reg32 offset="0" name="0">
 1514         <bitfield name="ADDR0_LO" low="0" high="31"/>
 1515     </reg32>
 1516     <reg32 offset="1" name="1">
 1517         <bitfield name="ADDR0_HI" low="0" high="31"/>
 1518     </reg32>
 1519     <reg32 offset="2" name="2">
 1520         <bitfield name="ADDR1_LO" low="0" high="31"/>
 1521     </reg32>
 1522     <reg32 offset="3" name="3">
 1523         <bitfield name="ADDR1_HI" low="0" high="31"/>
 1524     </reg32>
 1525     <reg32 offset="4" name="4">
 1526         <bitfield name="REF" low="0" high="31"/>
 1527     </reg32>
 1528     <reg32 offset="5" name="5">
 1529         <bitfield name="DWORDS" low="0" high="31" type="uint"/>
 1530     </reg32>
 1531 </domain>
 1532 
 1533 <domain name="CP_SET_CTXSWITCH_IB" width="32">
 1534     <doc>
 1535                 Used by the userspace driver to set various IB's which are
 1536                 executed during context save/restore for handling
 1537                 state that isn't restored by the
 1538                 context switch routine itself.
 1539     </doc>
 1540     <enum name="ctxswitch_ib">
 1541         <value name="RESTORE_IB" value="0">
 1542             <doc>Executed unconditionally when switching back to the context.</doc>
 1543         </value>
 1544         <value name="YIELD_RESTORE_IB" value="1">
 1545                         <doc>
 1546                 Executed when switching back after switching
 1547                 away during execution of
 1548                 a CP_SET_MARKER packet with RM6_YIELD as the
 1549                 payload *and* the normal save routine was
 1550                 bypassed for a shorter one. I think this is
 1551                 connected to the "skipsaverestore" bit set by
 1552                 the kernel when preempting.
 1553             </doc>
 1554         </value>
 1555         <value name="SAVE_IB" value="2">
 1556                         <doc>
 1557                 Executed when switching away from the context,
 1558                 except for context switches initiated via
 1559                 CP_YIELD.
 1560                         </doc>
 1561         </value>
 1562         <value name="RB_SAVE_IB" value="3">
 1563             <doc>
 1564                 This can only be set by the RB (i.e. the kernel)
 1565                 and executes with protected mode off, but
 1566                 is otherwise similar to SAVE_IB.
 1567             </doc>
 1568         </value>
 1569     </enum>
 1570     <reg32 offset="0" name="0">
 1571         <bitfield name="ADDR_LO" low="0" high="31"/>
 1572     </reg32>
 1573     <reg32 offset="1" name="1">
 1574         <bitfield name="ADDR_HI" low="0" high="31"/>
 1575     </reg32>
 1576     <reg32 offset="2" name="2">
 1577         <bitfield name="DWORDS" low="0" high="19" type="uint"/>
 1578         <bitfield name="TYPE" low="20" high="21" type="ctxswitch_ib"/>
 1579     </reg32>
 1580 </domain>
 1581 
 1582 <domain name="CP_REG_WRITE" width="32">
 1583     <enum name="reg_tracker">
 1584         <doc>
 1585             Keep shadow copies of these registers and only set them
 1586             when drawing, avoiding redundant writes:
 1587             - VPC_CNTL_0
 1588             - HLSQ_CONTROL_1_REG
 1589             - HLSQ_UNKNOWN_B980
 1590         </doc>
 1591         <value name="TRACK_CNTL_REG" value="0x1"/>
 1592         <doc>
 1593             Track RB_RENDER_CNTL, and insert a WFI in the following
 1594             situation:
 1595             - There is a write that disables binning
 1596             - There was a draw with binning left enabled, but in
 1597               BYPASS mode
 1598             Presumably this is a hang workaround?
 1599         </doc>
 1600         <value name="TRACK_RENDER_CNTL" value="0x2"/>
 1601         <doc>
 1602             Do a mysterious CP_EVENT_WRITE 0x3f when the low bit of
 1603             the data to write is 0. Used by the Vulkan blob with
 1604             PC_UNKNOWN_9B07, but this isn't predicated on particular
 1605             register(s) like the others.
 1606         </doc>
 1607         <value name="UNK_EVENT_WRITE" value="0x4"/>
 1608     </enum>
 1609     <reg32 offset="0" name="0">
 1610         <bitfield name="TRACKER" low="0" high="2" type="reg_tracker"/>
 1611     </reg32>
 1612 </domain>
 1613 
 1614 </database>
 1615