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Member "mesa-20.1.8/src/freedreno/ir3/ir3_cp.c" (16 Sep 2020, 22778 Bytes) of package /linux/misc/mesa-20.1.8.tar.xz:


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    1 /*
    2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
    3  *
    4  * Permission is hereby granted, free of charge, to any person obtaining a
    5  * copy of this software and associated documentation files (the "Software"),
    6  * to deal in the Software without restriction, including without limitation
    7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
    8  * and/or sell copies of the Software, and to permit persons to whom the
    9  * Software is furnished to do so, subject to the following conditions:
   10  *
   11  * The above copyright notice and this permission notice (including the next
   12  * paragraph) shall be included in all copies or substantial portions of the
   13  * Software.
   14  *
   15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
   18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
   21  * SOFTWARE.
   22  *
   23  * Authors:
   24  *    Rob Clark <robclark@freedesktop.org>
   25  */
   26 
   27 #include <math.h>
   28 #include "util/half_float.h"
   29 #include "util/u_math.h"
   30 
   31 #include "ir3.h"
   32 #include "ir3_compiler.h"
   33 #include "ir3_shader.h"
   34 
   35 #define swap(a, b) \
   36     do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
   37 
   38 /*
   39  * Copy Propagate:
   40  */
   41 
   42 struct ir3_cp_ctx {
   43     struct ir3 *shader;
   44     struct ir3_shader_variant *so;
   45 };
   46 
   47 /* is it a type preserving mov, with ok flags?
   48  *
   49  * @instr: the mov to consider removing
   50  * @dst_instr: the instruction consuming the mov (instr)
   51  *
   52  * TODO maybe drop allow_flags since this is only false when dst is
   53  * NULL (ie. outputs)
   54  */
   55 static bool is_eligible_mov(struct ir3_instruction *instr,
   56         struct ir3_instruction *dst_instr, bool allow_flags)
   57 {
   58     if (is_same_type_mov(instr)) {
   59         struct ir3_register *dst = instr->regs[0];
   60         struct ir3_register *src = instr->regs[1];
   61         struct ir3_instruction *src_instr = ssa(src);
   62 
   63         /* only if mov src is SSA (not const/immed): */
   64         if (!src_instr)
   65             return false;
   66 
   67         /* no indirect: */
   68         if (dst->flags & IR3_REG_RELATIV)
   69             return false;
   70         if (src->flags & IR3_REG_RELATIV)
   71             return false;
   72 
   73         if (src->flags & IR3_REG_ARRAY)
   74             return false;
   75 
   76         if (!allow_flags)
   77             if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG |
   78                     IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
   79                 return false;
   80 
   81         /* If src is coming from fanout/split (ie. one component of a
   82          * texture fetch, etc) and we have constraints on swizzle of
   83          * destination, then skip it.
   84          *
   85          * We could possibly do a bit better, and copy-propagation if
   86          * we can CP all components that are being fanned out.
   87          */
   88         if (src_instr->opc == OPC_META_SPLIT) {
   89             if (!dst_instr)
   90                 return false;
   91             if (dst_instr->opc == OPC_META_COLLECT)
   92                 return false;
   93             if (dst_instr->cp.left || dst_instr->cp.right)
   94                 return false;
   95         }
   96 
   97         return true;
   98     }
   99     return false;
  100 }
  101 
  102 static unsigned cp_flags(unsigned flags)
  103 {
  104     /* only considering these flags (at least for now): */
  105     flags &= (IR3_REG_CONST | IR3_REG_IMMED |
  106             IR3_REG_FNEG | IR3_REG_FABS |
  107             IR3_REG_SNEG | IR3_REG_SABS |
  108             IR3_REG_BNOT | IR3_REG_RELATIV);
  109     return flags;
  110 }
  111 
  112 static bool valid_flags(struct ir3_instruction *instr, unsigned n,
  113         unsigned flags)
  114 {
  115     struct ir3_compiler *compiler = instr->block->shader->compiler;
  116     unsigned valid_flags;
  117 
  118     if ((flags & IR3_REG_HIGH) &&
  119             (opc_cat(instr->opc) > 1) &&
  120             (compiler->gpu_id >= 600))
  121         return false;
  122 
  123     flags = cp_flags(flags);
  124 
  125     /* If destination is indirect, then source cannot be.. at least
  126      * I don't think so..
  127      */
  128     if ((instr->regs[0]->flags & IR3_REG_RELATIV) &&
  129             (flags & IR3_REG_RELATIV))
  130         return false;
  131 
  132     if (flags & IR3_REG_RELATIV) {
  133         /* TODO need to test on earlier gens.. pretty sure the earlier
  134          * problem was just that we didn't check that the src was from
  135          * same block (since we can't propagate address register values
  136          * across blocks currently)
  137          */
  138         if (compiler->gpu_id < 600)
  139             return false;
  140 
  141         /* NOTE in the special try_swap_mad_two_srcs() case we can be
  142          * called on a src that has already had an indirect load folded
  143          * in, in which case ssa() returns NULL
  144          */
  145         struct ir3_instruction *src = ssa(instr->regs[n+1]);
  146         if (src && src->address->block != instr->block)
  147             return false;
  148     }
  149 
  150     switch (opc_cat(instr->opc)) {
  151     case 1:
  152         valid_flags = IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_RELATIV;
  153         if (flags & ~valid_flags)
  154             return false;
  155         break;
  156     case 2:
  157         valid_flags = ir3_cat2_absneg(instr->opc) |
  158                 IR3_REG_CONST | IR3_REG_RELATIV;
  159 
  160         if (ir3_cat2_int(instr->opc))
  161             valid_flags |= IR3_REG_IMMED;
  162 
  163         if (flags & ~valid_flags)
  164             return false;
  165 
  166         if (flags & (IR3_REG_CONST | IR3_REG_IMMED)) {
  167             unsigned m = (n ^ 1) + 1;
  168             /* cannot deal w/ const in both srcs:
  169              * (note that some cat2 actually only have a single src)
  170              */
  171             if (m < instr->regs_count) {
  172                 struct ir3_register *reg = instr->regs[m];
  173                 if ((flags & IR3_REG_CONST) && (reg->flags & IR3_REG_CONST))
  174                     return false;
  175                 if ((flags & IR3_REG_IMMED) && (reg->flags & IR3_REG_IMMED))
  176                     return false;
  177             }
  178         }
  179         break;
  180     case 3:
  181         valid_flags = ir3_cat3_absneg(instr->opc) |
  182                 IR3_REG_CONST | IR3_REG_RELATIV;
  183 
  184         if (flags & ~valid_flags)
  185             return false;
  186 
  187         if (flags & (IR3_REG_CONST | IR3_REG_RELATIV)) {
  188             /* cannot deal w/ const/relativ in 2nd src: */
  189             if (n == 1)
  190                 return false;
  191         }
  192 
  193         break;
  194     case 4:
  195         /* seems like blob compiler avoids const as src.. */
  196         /* TODO double check if this is still the case on a4xx */
  197         if (flags & (IR3_REG_CONST | IR3_REG_IMMED))
  198             return false;
  199         if (flags & (IR3_REG_SABS | IR3_REG_SNEG))
  200             return false;
  201         break;
  202     case 5:
  203         /* no flags allowed */
  204         if (flags)
  205             return false;
  206         break;
  207     case 6:
  208         valid_flags = IR3_REG_IMMED;
  209         if (flags & ~valid_flags)
  210             return false;
  211 
  212         if (flags & IR3_REG_IMMED) {
  213             /* doesn't seem like we can have immediate src for store
  214              * instructions:
  215              *
  216              * TODO this restriction could also apply to load instructions,
  217              * but for load instructions this arg is the address (and not
  218              * really sure any good way to test a hard-coded immed addr src)
  219              */
  220             if (is_store(instr) && (n == 1))
  221                 return false;
  222 
  223             if ((instr->opc == OPC_LDL) && (n == 0))
  224                 return false;
  225 
  226             if ((instr->opc == OPC_STL) && (n != 2))
  227                 return false;
  228 
  229             if (instr->opc == OPC_STLW && n == 0)
  230                 return false;
  231 
  232             if (instr->opc == OPC_LDLW && n == 0)
  233                 return false;
  234 
  235             /* disallow CP into anything but the SSBO slot argument for
  236              * atomics:
  237              */
  238             if (is_atomic(instr->opc) && (n != 0))
  239                 return false;
  240 
  241             if (is_atomic(instr->opc) && !(instr->flags & IR3_INSTR_G))
  242                 return false;
  243 
  244             if (instr->opc == OPC_STG && (instr->flags & IR3_INSTR_G) && (n != 2))
  245                 return false;
  246 
  247             /* as with atomics, ldib and ldc on a6xx can only have immediate
  248              * for SSBO slot argument
  249              */
  250             if ((instr->opc == OPC_LDIB || instr->opc == OPC_LDC) && (n != 0))
  251                 return false;
  252         }
  253 
  254         break;
  255     }
  256 
  257     return true;
  258 }
  259 
  260 /* propagate register flags from src to dst.. negates need special
  261  * handling to cancel each other out.
  262  */
  263 static void combine_flags(unsigned *dstflags, struct ir3_instruction *src)
  264 {
  265     unsigned srcflags = src->regs[1]->flags;
  266 
  267     /* if what we are combining into already has (abs) flags,
  268      * we can drop (neg) from src:
  269      */
  270     if (*dstflags & IR3_REG_FABS)
  271         srcflags &= ~IR3_REG_FNEG;
  272     if (*dstflags & IR3_REG_SABS)
  273         srcflags &= ~IR3_REG_SNEG;
  274 
  275     if (srcflags & IR3_REG_FABS)
  276         *dstflags |= IR3_REG_FABS;
  277     if (srcflags & IR3_REG_SABS)
  278         *dstflags |= IR3_REG_SABS;
  279     if (srcflags & IR3_REG_FNEG)
  280         *dstflags ^= IR3_REG_FNEG;
  281     if (srcflags & IR3_REG_SNEG)
  282         *dstflags ^= IR3_REG_SNEG;
  283     if (srcflags & IR3_REG_BNOT)
  284         *dstflags ^= IR3_REG_BNOT;
  285 
  286     *dstflags &= ~IR3_REG_SSA;
  287     *dstflags |= srcflags & IR3_REG_SSA;
  288     *dstflags |= srcflags & IR3_REG_CONST;
  289     *dstflags |= srcflags & IR3_REG_IMMED;
  290     *dstflags |= srcflags & IR3_REG_RELATIV;
  291     *dstflags |= srcflags & IR3_REG_ARRAY;
  292     *dstflags |= srcflags & IR3_REG_HIGH;
  293 
  294     /* if src of the src is boolean we can drop the (abs) since we know
  295      * the source value is already a postitive integer.  This cleans
  296      * up the absnegs that get inserted when converting between nir and
  297      * native boolean (see ir3_b2n/n2b)
  298      */
  299     struct ir3_instruction *srcsrc = ssa(src->regs[1]);
  300     if (srcsrc && is_bool(srcsrc))
  301         *dstflags &= ~IR3_REG_SABS;
  302 }
  303 
  304 static struct ir3_register *
  305 lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags, bool f_opcode)
  306 {
  307     unsigned swiz, idx, i;
  308 
  309     reg = ir3_reg_clone(ctx->shader, reg);
  310 
  311     /* Half constant registers seems to handle only 32-bit values
  312      * within floating-point opcodes. So convert back to 32-bit values.
  313      */
  314     if (f_opcode && (new_flags & IR3_REG_HALF))
  315         reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
  316 
  317     /* in some cases, there are restrictions on (abs)/(neg) plus const..
  318      * so just evaluate those and clear the flags:
  319      */
  320     if (new_flags & IR3_REG_SABS) {
  321         reg->iim_val = abs(reg->iim_val);
  322         new_flags &= ~IR3_REG_SABS;
  323     }
  324 
  325     if (new_flags & IR3_REG_FABS) {
  326         reg->fim_val = fabs(reg->fim_val);
  327         new_flags &= ~IR3_REG_FABS;
  328     }
  329 
  330     if (new_flags & IR3_REG_SNEG) {
  331         reg->iim_val = -reg->iim_val;
  332         new_flags &= ~IR3_REG_SNEG;
  333     }
  334 
  335     if (new_flags & IR3_REG_FNEG) {
  336         reg->fim_val = -reg->fim_val;
  337         new_flags &= ~IR3_REG_FNEG;
  338     }
  339 
  340     /* Reallocate for 4 more elements whenever it's necessary */
  341     struct ir3_const_state *const_state = &ctx->so->shader->const_state;
  342     if (const_state->immediate_idx == const_state->immediates_size * 4) {
  343         const_state->immediates_size += 4;
  344         const_state->immediates = realloc (const_state->immediates,
  345             const_state->immediates_size * sizeof(const_state->immediates[0]));
  346     }
  347 
  348     for (i = 0; i < const_state->immediate_idx; i++) {
  349         swiz = i % 4;
  350         idx  = i / 4;
  351 
  352         if (const_state->immediates[idx].val[swiz] == reg->uim_val) {
  353             break;
  354         }
  355     }
  356 
  357     if (i == const_state->immediate_idx) {
  358         /* need to generate a new immediate: */
  359         swiz = i % 4;
  360         idx  = i / 4;
  361 
  362         const_state->immediates[idx].val[swiz] = reg->uim_val;
  363         const_state->immediates_count = idx + 1;
  364         const_state->immediate_idx++;
  365     }
  366 
  367     new_flags &= ~IR3_REG_IMMED;
  368     new_flags |= IR3_REG_CONST;
  369     reg->flags = new_flags;
  370     reg->num = i + (4 * const_state->offsets.immediate);
  371 
  372     return reg;
  373 }
  374 
  375 static void
  376 unuse(struct ir3_instruction *instr)
  377 {
  378     debug_assert(instr->use_count > 0);
  379 
  380     if (--instr->use_count == 0) {
  381         struct ir3_block *block = instr->block;
  382 
  383         instr->barrier_class = 0;
  384         instr->barrier_conflict = 0;
  385 
  386         /* we don't want to remove anything in keeps (which could
  387          * be things like array store's)
  388          */
  389         for (unsigned i = 0; i < block->keeps_count; i++) {
  390             debug_assert(block->keeps[i] != instr);
  391         }
  392     }
  393 }
  394 
  395 /**
  396  * Handles the special case of the 2nd src (n == 1) to "normal" mad
  397  * instructions, which cannot reference a constant.  See if it is
  398  * possible to swap the 1st and 2nd sources.
  399  */
  400 static bool
  401 try_swap_mad_two_srcs(struct ir3_instruction *instr, unsigned new_flags)
  402 {
  403     if (!is_mad(instr->opc))
  404         return false;
  405 
  406     /* NOTE: pre-swap first two src's before valid_flags(),
  407      * which might try to dereference the n'th src:
  408      */
  409     swap(instr->regs[0 + 1], instr->regs[1 + 1]);
  410 
  411     /* cat3 doesn't encode immediate, but we can lower immediate
  412      * to const if that helps:
  413      */
  414     if (new_flags & IR3_REG_IMMED) {
  415         new_flags &= ~IR3_REG_IMMED;
  416         new_flags |=  IR3_REG_CONST;
  417     }
  418 
  419     bool valid_swap =
  420         /* can we propagate mov if we move 2nd src to first? */
  421         valid_flags(instr, 0, new_flags) &&
  422         /* and does first src fit in second slot? */
  423         valid_flags(instr, 1, instr->regs[1 + 1]->flags);
  424 
  425     if (!valid_swap) {
  426         /* put things back the way they were: */
  427         swap(instr->regs[0 + 1], instr->regs[1 + 1]);
  428     }   /* otherwise leave things swapped */
  429 
  430     return valid_swap;
  431 }
  432 
  433 /**
  434  * Handle cp for a given src register.  This additionally handles
  435  * the cases of collapsing immedate/const (which replace the src
  436  * register with a non-ssa src) or collapsing mov's from relative
  437  * src (which needs to also fixup the address src reference by the
  438  * instruction).
  439  */
  440 static bool
  441 reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
  442         struct ir3_register *reg, unsigned n)
  443 {
  444     struct ir3_instruction *src = ssa(reg);
  445 
  446     if (is_eligible_mov(src, instr, true)) {
  447         /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
  448         struct ir3_register *src_reg = src->regs[1];
  449         unsigned new_flags = reg->flags;
  450 
  451         combine_flags(&new_flags, src);
  452 
  453         if (valid_flags(instr, n, new_flags)) {
  454             if (new_flags & IR3_REG_ARRAY) {
  455                 debug_assert(!(reg->flags & IR3_REG_ARRAY));
  456                 reg->array = src_reg->array;
  457             }
  458             reg->flags = new_flags;
  459             reg->instr = ssa(src_reg);
  460 
  461             instr->barrier_class |= src->barrier_class;
  462             instr->barrier_conflict |= src->barrier_conflict;
  463 
  464             unuse(src);
  465             reg->instr->use_count++;
  466 
  467             return true;
  468         }
  469     } else if ((is_same_type_mov(src) || is_const_mov(src)) &&
  470             /* cannot collapse const/immed/etc into meta instrs: */
  471             !is_meta(instr)) {
  472         /* immed/const/etc cases, which require some special handling: */
  473         struct ir3_register *src_reg = src->regs[1];
  474         unsigned new_flags = reg->flags;
  475 
  476         combine_flags(&new_flags, src);
  477 
  478         if (!valid_flags(instr, n, new_flags)) {
  479             /* See if lowering an immediate to const would help. */
  480             if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
  481                 bool f_opcode = (is_cat2_float(instr->opc) ||
  482                         is_cat3_float(instr->opc)) ? true : false;
  483 
  484                 debug_assert(new_flags & IR3_REG_IMMED);
  485 
  486                 instr->regs[n + 1] = lower_immed(ctx, src_reg, new_flags, f_opcode);
  487                 return true;
  488             }
  489 
  490             /* special case for "normal" mad instructions, we can
  491              * try swapping the first two args if that fits better.
  492              *
  493              * the "plain" MAD's (ie. the ones that don't shift first
  494              * src prior to multiply) can swap their first two srcs if
  495              * src[0] is !CONST and src[1] is CONST:
  496              */
  497             if ((n == 1) && try_swap_mad_two_srcs(instr, new_flags)) {
  498                 return true;
  499             } else {
  500                 return false;
  501             }
  502         }
  503 
  504         /* Here we handle the special case of mov from
  505          * CONST and/or RELATIV.  These need to be handled
  506          * specially, because in the case of move from CONST
  507          * there is no src ir3_instruction so we need to
  508          * replace the ir3_register.  And in the case of
  509          * RELATIV we need to handle the address register
  510          * dependency.
  511          */
  512         if (src_reg->flags & IR3_REG_CONST) {
  513             /* an instruction cannot reference two different
  514              * address registers:
  515              */
  516             if ((src_reg->flags & IR3_REG_RELATIV) &&
  517                     conflicts(instr->address, reg->instr->address))
  518                 return false;
  519 
  520             /* This seems to be a hw bug, or something where the timings
  521              * just somehow don't work out.  This restriction may only
  522              * apply if the first src is also CONST.
  523              */
  524             if ((opc_cat(instr->opc) == 3) && (n == 2) &&
  525                     (src_reg->flags & IR3_REG_RELATIV) &&
  526                     (src_reg->array.offset == 0))
  527                 return false;
  528 
  529             /* When narrowing constant from 32b to 16b, it seems
  530              * to work only for float. So we should do this only with
  531              * float opcodes.
  532              */
  533             if (src->cat1.dst_type == TYPE_F16) {
  534                 if (instr->opc == OPC_MOV && !type_float(instr->cat1.src_type))
  535                     return false;
  536                 if (!is_cat2_float(instr->opc) && !is_cat3_float(instr->opc))
  537                     return false;
  538             }
  539 
  540             src_reg = ir3_reg_clone(instr->block->shader, src_reg);
  541             src_reg->flags = new_flags;
  542             instr->regs[n+1] = src_reg;
  543 
  544             if (src_reg->flags & IR3_REG_RELATIV)
  545                 ir3_instr_set_address(instr, reg->instr->address);
  546 
  547             return true;
  548         }
  549 
  550         if ((src_reg->flags & IR3_REG_RELATIV) &&
  551                 !conflicts(instr->address, reg->instr->address)) {
  552             src_reg = ir3_reg_clone(instr->block->shader, src_reg);
  553             src_reg->flags = new_flags;
  554             instr->regs[n+1] = src_reg;
  555             ir3_instr_set_address(instr, reg->instr->address);
  556 
  557             return true;
  558         }
  559 
  560         /* NOTE: seems we can only do immed integers, so don't
  561          * need to care about float.  But we do need to handle
  562          * abs/neg *before* checking that the immediate requires
  563          * few enough bits to encode:
  564          *
  565          * TODO: do we need to do something to avoid accidentally
  566          * catching a float immed?
  567          */
  568         if (src_reg->flags & IR3_REG_IMMED) {
  569             int32_t iim_val = src_reg->iim_val;
  570 
  571             debug_assert((opc_cat(instr->opc) == 1) ||
  572                     (opc_cat(instr->opc) == 6) ||
  573                     ir3_cat2_int(instr->opc) ||
  574                     (is_mad(instr->opc) && (n == 0)));
  575 
  576             if (new_flags & IR3_REG_SABS)
  577                 iim_val = abs(iim_val);
  578 
  579             if (new_flags & IR3_REG_SNEG)
  580                 iim_val = -iim_val;
  581 
  582             if (new_flags & IR3_REG_BNOT)
  583                 iim_val = ~iim_val;
  584 
  585             /* other than category 1 (mov) we can only encode up to 10 bits: */
  586             if (valid_flags(instr, n, new_flags) &&
  587                     ((instr->opc == OPC_MOV) ||
  588                      !((iim_val & ~0x3ff) && (-iim_val & ~0x3ff)))) {
  589                 new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
  590                 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
  591                 src_reg->flags = new_flags;
  592                 src_reg->iim_val = iim_val;
  593                 instr->regs[n+1] = src_reg;
  594 
  595                 return true;
  596             } else if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
  597                 bool f_opcode = (is_cat2_float(instr->opc) ||
  598                         is_cat3_float(instr->opc)) ? true : false;
  599 
  600                 /* See if lowering an immediate to const would help. */
  601                 instr->regs[n+1] = lower_immed(ctx, src_reg, new_flags, f_opcode);
  602 
  603                 return true;
  604             }
  605         }
  606     }
  607 
  608     return false;
  609 }
  610 
  611 /* Handle special case of eliminating output mov, and similar cases where
  612  * there isn't a normal "consuming" instruction.  In this case we cannot
  613  * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
  614  * be eliminated)
  615  */
  616 static struct ir3_instruction *
  617 eliminate_output_mov(struct ir3_instruction *instr)
  618 {
  619     if (is_eligible_mov(instr, NULL, false)) {
  620         struct ir3_register *reg = instr->regs[1];
  621         if (!(reg->flags & IR3_REG_ARRAY)) {
  622             struct ir3_instruction *src_instr = ssa(reg);
  623             debug_assert(src_instr);
  624             return src_instr;
  625         }
  626     }
  627     return instr;
  628 }
  629 
  630 /**
  631  * Find instruction src's which are mov's that can be collapsed, replacing
  632  * the mov dst with the mov src
  633  */
  634 static void
  635 instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
  636 {
  637     struct ir3_register *reg;
  638 
  639     if (instr->regs_count == 0)
  640         return;
  641 
  642     if (ir3_instr_check_mark(instr))
  643         return;
  644 
  645     /* walk down the graph from each src: */
  646     bool progress;
  647     do {
  648         progress = false;
  649         foreach_src_n (reg, n, instr) {
  650             struct ir3_instruction *src = ssa(reg);
  651 
  652             if (!src)
  653                 continue;
  654 
  655             instr_cp(ctx, src);
  656 
  657             /* TODO non-indirect access we could figure out which register
  658              * we actually want and allow cp..
  659              */
  660             if (reg->flags & IR3_REG_ARRAY)
  661                 continue;
  662 
  663             /* Don't CP absneg into meta instructions, that won't end well: */
  664             if (is_meta(instr) && (src->opc != OPC_MOV))
  665                 continue;
  666 
  667             progress |= reg_cp(ctx, instr, reg, n);
  668         }
  669     } while (progress);
  670 
  671     if (instr->regs[0]->flags & IR3_REG_ARRAY) {
  672         struct ir3_instruction *src = ssa(instr->regs[0]);
  673         if (src)
  674             instr_cp(ctx, src);
  675     }
  676 
  677     if (instr->address) {
  678         instr_cp(ctx, instr->address);
  679         ir3_instr_set_address(instr, eliminate_output_mov(instr->address));
  680     }
  681 
  682     /* we can end up with extra cmps.s from frontend, which uses a
  683      *
  684      *    cmps.s p0.x, cond, 0
  685      *
  686      * as a way to mov into the predicate register.  But frequently 'cond'
  687      * is itself a cmps.s/cmps.f/cmps.u.  So detect this special case and
  688      * just re-write the instruction writing predicate register to get rid
  689      * of the double cmps.
  690      */
  691     if ((instr->opc == OPC_CMPS_S) &&
  692             (instr->regs[0]->num == regid(REG_P0, 0)) &&
  693             ssa(instr->regs[1]) &&
  694             (instr->regs[2]->flags & IR3_REG_IMMED) &&
  695             (instr->regs[2]->iim_val == 0)) {
  696         struct ir3_instruction *cond = ssa(instr->regs[1]);
  697         switch (cond->opc) {
  698         case OPC_CMPS_S:
  699         case OPC_CMPS_F:
  700         case OPC_CMPS_U:
  701             instr->opc   = cond->opc;
  702             instr->flags = cond->flags;
  703             instr->cat2  = cond->cat2;
  704             ir3_instr_set_address(instr, cond->address);
  705             instr->regs[1] = cond->regs[1];
  706             instr->regs[2] = cond->regs[2];
  707             instr->barrier_class |= cond->barrier_class;
  708             instr->barrier_conflict |= cond->barrier_conflict;
  709             unuse(cond);
  710             break;
  711         default:
  712             break;
  713         }
  714     }
  715 
  716     /* Handle converting a sam.s2en (taking samp/tex idx params via register)
  717      * into a normal sam (encoding immediate samp/tex idx) if they are
  718      * immediate. This saves some instructions and regs in the common case
  719      * where we know samp/tex at compile time. This needs to be done in the
  720      * frontend for bindless tex, though, so don't replicate it here.
  721      */
  722     if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) &&
  723             !(instr->flags & IR3_INSTR_B) &&
  724             !(ir3_shader_debug & IR3_DBG_FORCES2EN)) {
  725         /* The first src will be a collect, if both of it's
  726          * two sources are mov from imm, then we can
  727          */
  728         struct ir3_instruction *samp_tex = ssa(instr->regs[1]);
  729 
  730         debug_assert(samp_tex->opc == OPC_META_COLLECT);
  731 
  732         struct ir3_instruction *samp = ssa(samp_tex->regs[1]);
  733         struct ir3_instruction *tex  = ssa(samp_tex->regs[2]);
  734 
  735         if ((samp->opc == OPC_MOV) &&
  736                 (samp->regs[1]->flags & IR3_REG_IMMED) &&
  737                 (tex->opc == OPC_MOV) &&
  738                 (tex->regs[1]->flags & IR3_REG_IMMED)) {
  739             instr->flags &= ~IR3_INSTR_S2EN;
  740             instr->cat5.samp = samp->regs[1]->iim_val;
  741             instr->cat5.tex  = tex->regs[1]->iim_val;
  742 
  743             /* shuffle around the regs to remove the first src: */
  744             instr->regs_count--;
  745             for (unsigned i = 1; i < instr->regs_count; i++) {
  746                 instr->regs[i] = instr->regs[i + 1];
  747             }
  748         }
  749     }
  750 }
  751 
  752 void
  753 ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
  754 {
  755     struct ir3_cp_ctx ctx = {
  756             .shader = ir,
  757             .so = so,
  758     };
  759 
  760     /* This is a bit annoying, and probably wouldn't be necessary if we
  761      * tracked a reverse link from producing instruction to consumer.
  762      * But we need to know when we've eliminated the last consumer of
  763      * a mov, so we need to do a pass to first count consumers of a
  764      * mov.
  765      */
  766     foreach_block (block, &ir->block_list) {
  767         foreach_instr (instr, &block->instr_list) {
  768             struct ir3_instruction *src;
  769 
  770             /* by the way, we don't account for false-dep's, so the CP
  771              * pass should always happen before false-dep's are inserted
  772              */
  773             debug_assert(instr->deps_count == 0);
  774 
  775             foreach_ssa_src (src, instr) {
  776                 src->use_count++;
  777             }
  778         }
  779     }
  780 
  781     ir3_clear_mark(ir);
  782 
  783     struct ir3_instruction *out;
  784     foreach_output_n (out, n, ir) {
  785         instr_cp(&ctx, out);
  786         ir->outputs[n] = eliminate_output_mov(out);
  787     }
  788 
  789     foreach_block (block, &ir->block_list) {
  790         if (block->condition) {
  791             instr_cp(&ctx, block->condition);
  792             block->condition = eliminate_output_mov(block->condition);
  793         }
  794 
  795         for (unsigned i = 0; i < block->keeps_count; i++) {
  796             instr_cp(&ctx, block->keeps[i]);
  797             block->keeps[i] = eliminate_output_mov(block->keeps[i]);
  798         }
  799     }
  800 }