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Member "mesa-20.1.8/src/amd/vulkan/radv_debug.c" (16 Sep 2020, 18609 Bytes) of package /linux/misc/mesa-20.1.8.tar.xz:


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    1 /*
    2  * Copyright © 2016 Red Hat.
    3  * Copyright © 2016 Bas Nieuwenhuizen
    4  *
    5  * based in part on anv driver which is:
    6  * Copyright © 2015 Intel Corporation
    7  *
    8  * Permission is hereby granted, free of charge, to any person obtaining a
    9  * copy of this software and associated documentation files (the "Software"),
   10  * to deal in the Software without restriction, including without limitation
   11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   12  * and/or sell copies of the Software, and to permit persons to whom the
   13  * Software is furnished to do so, subject to the following conditions:
   14  *
   15  * The above copyright notice and this permission notice (including the next
   16  * paragraph) shall be included in all copies or substantial portions of the
   17  * Software.
   18  *
   19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
   22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
   24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
   25  * IN THE SOFTWARE.
   26  */
   27 
   28 #include <stdlib.h>
   29 #include <stdio.h>
   30 #include <sys/utsname.h>
   31 
   32 #include "util/mesa-sha1.h"
   33 #include "sid.h"
   34 #include "ac_debug.h"
   35 #include "radv_debug.h"
   36 #include "radv_shader.h"
   37 
   38 #define TRACE_BO_SIZE 4096
   39 
   40 #define COLOR_RESET "\033[0m"
   41 #define COLOR_RED   "\033[31m"
   42 #define COLOR_GREEN "\033[1;32m"
   43 #define COLOR_YELLOW    "\033[1;33m"
   44 #define COLOR_CYAN  "\033[1;36m"
   45 
   46 /* Trace BO layout (offsets are 4 bytes):
   47  *
   48  * [0]: primary trace ID
   49  * [1]: secondary trace ID
   50  * [2-3]: 64-bit GFX pipeline pointer
   51  * [4-5]: 64-bit COMPUTE pipeline pointer
   52  * [6-7]: 64-bit descriptor set #0 pointer
   53  * ...
   54  * [68-69]: 64-bit descriptor set #31 pointer
   55  */
   56 
   57 bool
   58 radv_init_trace(struct radv_device *device)
   59 {
   60     struct radeon_winsys *ws = device->ws;
   61 
   62     device->trace_bo = ws->buffer_create(ws, TRACE_BO_SIZE, 8,
   63                          RADEON_DOMAIN_VRAM,
   64                          RADEON_FLAG_CPU_ACCESS|
   65                          RADEON_FLAG_NO_INTERPROCESS_SHARING |
   66                          RADEON_FLAG_ZERO_VRAM,
   67                          RADV_BO_PRIORITY_UPLOAD_BUFFER);
   68     if (!device->trace_bo)
   69         return false;
   70 
   71     device->trace_id_ptr = ws->buffer_map(device->trace_bo);
   72     if (!device->trace_id_ptr)
   73         return false;
   74 
   75     ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
   76                 &device->dmesg_timestamp, NULL);
   77 
   78     return true;
   79 }
   80 
   81 static void
   82 radv_dump_trace(struct radv_device *device, struct radeon_cmdbuf *cs)
   83 {
   84     const char *filename = getenv("RADV_TRACE_FILE");
   85     FILE *f = fopen(filename, "w");
   86 
   87     if (!f) {
   88         fprintf(stderr, "Failed to write trace dump to %s\n", filename);
   89         return;
   90     }
   91 
   92     fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
   93     device->ws->cs_dump(cs, f, (const int*)device->trace_id_ptr, 2);
   94     fclose(f);
   95 }
   96 
   97 static void
   98 radv_dump_mmapped_reg(struct radv_device *device, FILE *f, unsigned offset)
   99 {
  100     struct radeon_winsys *ws = device->ws;
  101     uint32_t value;
  102 
  103     if (ws->read_registers(ws, offset, 1, &value))
  104         ac_dump_reg(f, device->physical_device->rad_info.chip_class,
  105                 offset, value, ~0);
  106 }
  107 
  108 static void
  109 radv_dump_debug_registers(struct radv_device *device, FILE *f)
  110 {
  111     struct radeon_info *info = &device->physical_device->rad_info;
  112 
  113     fprintf(f, "Memory-mapped registers:\n");
  114     radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS);
  115 
  116     /* No other registers can be read on DRM < 3.1.0. */
  117     if (info->drm_minor < 1) {
  118         fprintf(f, "\n");
  119         return;
  120     }
  121 
  122     radv_dump_mmapped_reg(device, f, R_008008_GRBM_STATUS2);
  123     radv_dump_mmapped_reg(device, f, R_008014_GRBM_STATUS_SE0);
  124     radv_dump_mmapped_reg(device, f, R_008018_GRBM_STATUS_SE1);
  125     radv_dump_mmapped_reg(device, f, R_008038_GRBM_STATUS_SE2);
  126     radv_dump_mmapped_reg(device, f, R_00803C_GRBM_STATUS_SE3);
  127     radv_dump_mmapped_reg(device, f, R_00D034_SDMA0_STATUS_REG);
  128     radv_dump_mmapped_reg(device, f, R_00D834_SDMA1_STATUS_REG);
  129     if (info->chip_class <= GFX8) {
  130         radv_dump_mmapped_reg(device, f, R_000E50_SRBM_STATUS);
  131         radv_dump_mmapped_reg(device, f, R_000E4C_SRBM_STATUS2);
  132         radv_dump_mmapped_reg(device, f, R_000E54_SRBM_STATUS3);
  133     }
  134     radv_dump_mmapped_reg(device, f, R_008680_CP_STAT);
  135     radv_dump_mmapped_reg(device, f, R_008674_CP_STALLED_STAT1);
  136     radv_dump_mmapped_reg(device, f, R_008678_CP_STALLED_STAT2);
  137     radv_dump_mmapped_reg(device, f, R_008670_CP_STALLED_STAT3);
  138     radv_dump_mmapped_reg(device, f, R_008210_CP_CPC_STATUS);
  139     radv_dump_mmapped_reg(device, f, R_008214_CP_CPC_BUSY_STAT);
  140     radv_dump_mmapped_reg(device, f, R_008218_CP_CPC_STALLED_STAT1);
  141     radv_dump_mmapped_reg(device, f, R_00821C_CP_CPF_STATUS);
  142     radv_dump_mmapped_reg(device, f, R_008220_CP_CPF_BUSY_STAT);
  143     radv_dump_mmapped_reg(device, f, R_008224_CP_CPF_STALLED_STAT1);
  144     fprintf(f, "\n");
  145 }
  146 
  147 static void
  148 radv_dump_buffer_descriptor(enum chip_class chip_class, const uint32_t *desc,
  149                 FILE *f)
  150 {
  151     fprintf(f, COLOR_CYAN "    Buffer:" COLOR_RESET "\n");
  152     for (unsigned j = 0; j < 4; j++)
  153         ac_dump_reg(f, chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4,
  154                 desc[j], 0xffffffff);
  155 }
  156 
  157 static void
  158 radv_dump_image_descriptor(enum chip_class chip_class, const uint32_t *desc,
  159                FILE *f)
  160 {
  161     unsigned sq_img_rsrc_word0 = chip_class >= GFX10 ? R_00A000_SQ_IMG_RSRC_WORD0
  162                              : R_008F10_SQ_IMG_RSRC_WORD0;
  163 
  164     fprintf(f, COLOR_CYAN "    Image:" COLOR_RESET "\n");
  165     for (unsigned j = 0; j < 8; j++)
  166         ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4,
  167                 desc[j], 0xffffffff);
  168 
  169     fprintf(f, COLOR_CYAN "    FMASK:" COLOR_RESET "\n");
  170     for (unsigned j = 0; j < 8; j++)
  171         ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4,
  172                 desc[8 + j], 0xffffffff);
  173 }
  174 
  175 static void
  176 radv_dump_sampler_descriptor(enum chip_class chip_class, const uint32_t *desc,
  177                  FILE *f)
  178 {
  179     fprintf(f, COLOR_CYAN "    Sampler state:" COLOR_RESET "\n");
  180     for (unsigned j = 0; j < 4; j++) {
  181         ac_dump_reg(f, chip_class, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4,
  182                 desc[j], 0xffffffff);
  183     }
  184 }
  185 
  186 static void
  187 radv_dump_combined_image_sampler_descriptor(enum chip_class chip_class,
  188                         const uint32_t *desc, FILE *f)
  189 {
  190     radv_dump_image_descriptor(chip_class, desc, f);
  191     radv_dump_sampler_descriptor(chip_class, desc + 16, f);
  192 }
  193 
  194 static void
  195 radv_dump_descriptor_set(struct radv_device *device,
  196              struct radv_descriptor_set *set, unsigned id, FILE *f)
  197 {
  198     enum chip_class chip_class = device->physical_device->rad_info.chip_class;
  199     const struct radv_descriptor_set_layout *layout;
  200     int i;
  201 
  202     if (!set)
  203         return;
  204     layout = set->layout;
  205 
  206     for (i = 0; i < set->layout->binding_count; i++) {
  207         uint32_t *desc =
  208             set->mapped_ptr + layout->binding[i].offset / 4;
  209 
  210         switch (layout->binding[i].type) {
  211         case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
  212         case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
  213         case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
  214         case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
  215             radv_dump_buffer_descriptor(chip_class, desc, f);
  216             break;
  217         case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
  218         case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
  219         case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
  220             radv_dump_image_descriptor(chip_class, desc, f);
  221             break;
  222         case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
  223             radv_dump_combined_image_sampler_descriptor(chip_class, desc, f);
  224             break;
  225         case VK_DESCRIPTOR_TYPE_SAMPLER:
  226             radv_dump_sampler_descriptor(chip_class, desc, f);
  227             break;
  228         case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
  229         case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
  230             /* todo */
  231             break;
  232         default:
  233             assert(!"unknown descriptor type");
  234             break;
  235         }
  236         fprintf(f, "\n");
  237     }
  238     fprintf(f, "\n\n");
  239 }
  240 
  241 static void
  242 radv_dump_descriptors(struct radv_device *device, FILE *f)
  243 {
  244     uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
  245     int i;
  246 
  247     fprintf(f, "Descriptors:\n");
  248     for (i = 0; i < MAX_SETS; i++) {
  249         struct radv_descriptor_set *set =
  250             *(struct radv_descriptor_set **)(ptr + i + 3);
  251 
  252         radv_dump_descriptor_set(device, set, i, f);
  253     }
  254 }
  255 
  256 struct radv_shader_inst {
  257     char text[160];  /* one disasm line */
  258     unsigned offset; /* instruction offset */
  259     unsigned size;   /* instruction size = 4 or 8 */
  260 };
  261 
  262 /* Split a disassembly string into lines and add them to the array pointed
  263  * to by "instructions". */
  264 static void si_add_split_disasm(const char *disasm,
  265                 uint64_t start_addr,
  266                 unsigned *num,
  267                 struct radv_shader_inst *instructions)
  268 {
  269     struct radv_shader_inst *last_inst = *num ? &instructions[*num - 1] : NULL;
  270     char *next;
  271 
  272     while ((next = strchr(disasm, '\n'))) {
  273         struct radv_shader_inst *inst = &instructions[*num];
  274         unsigned len = next - disasm;
  275 
  276         assert(len < ARRAY_SIZE(inst->text));
  277         memcpy(inst->text, disasm, len);
  278         inst->text[len] = 0;
  279         inst->offset = last_inst ? last_inst->offset + last_inst->size : 0;
  280 
  281         const char *semicolon = strchr(disasm, ';');
  282         assert(semicolon);
  283         /* More than 16 chars after ";" means the instruction is 8 bytes long. */
  284         inst->size = next - semicolon > 16 ? 8 : 4;
  285 
  286         snprintf(inst->text + len, ARRAY_SIZE(inst->text) - len,
  287             " [PC=0x%"PRIx64", off=%u, size=%u]",
  288             start_addr + inst->offset, inst->offset, inst->size);
  289 
  290         last_inst = inst;
  291         (*num)++;
  292         disasm = next + 1;
  293     }
  294 }
  295 
  296 static void
  297 radv_dump_annotated_shader(struct radv_shader_variant *shader,
  298                gl_shader_stage stage, struct ac_wave_info *waves,
  299                unsigned num_waves, FILE *f)
  300 {
  301     uint64_t start_addr, end_addr;
  302     unsigned i;
  303 
  304     if (!shader)
  305         return;
  306 
  307     start_addr = radv_buffer_get_va(shader->bo) + shader->bo_offset;
  308     end_addr = start_addr + shader->code_size;
  309 
  310     /* See if any wave executes the shader. */
  311     for (i = 0; i < num_waves; i++) {
  312         if (start_addr <= waves[i].pc && waves[i].pc <= end_addr)
  313             break;
  314     }
  315 
  316     if (i == num_waves)
  317         return; /* the shader is not being executed */
  318 
  319     /* Remember the first found wave. The waves are sorted according to PC. */
  320     waves = &waves[i];
  321     num_waves -= i;
  322 
  323     /* Get the list of instructions.
  324      * Buffer size / 4 is the upper bound of the instruction count.
  325      */
  326     unsigned num_inst = 0;
  327     struct radv_shader_inst *instructions =
  328         calloc(shader->code_size / 4, sizeof(struct radv_shader_inst));
  329 
  330     si_add_split_disasm(shader->disasm_string,
  331                 start_addr, &num_inst, instructions);
  332 
  333     fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n",
  334         radv_get_shader_name(&shader->info, stage));
  335 
  336     /* Print instructions with annotations. */
  337     for (i = 0; i < num_inst; i++) {
  338         struct radv_shader_inst *inst = &instructions[i];
  339 
  340         fprintf(f, "%s\n", inst->text);
  341 
  342         /* Print which waves execute the instruction right now. */
  343         while (num_waves && start_addr + inst->offset == waves->pc) {
  344             fprintf(f,
  345                 "          " COLOR_GREEN "^ SE%u SH%u CU%u "
  346                 "SIMD%u WAVE%u  EXEC=%016"PRIx64 "  ",
  347                 waves->se, waves->sh, waves->cu, waves->simd,
  348                 waves->wave, waves->exec);
  349 
  350             if (inst->size == 4) {
  351                 fprintf(f, "INST32=%08X" COLOR_RESET "\n",
  352                     waves->inst_dw0);
  353             } else {
  354                 fprintf(f, "INST64=%08X %08X" COLOR_RESET "\n",
  355                     waves->inst_dw0, waves->inst_dw1);
  356             }
  357 
  358             waves->matched = true;
  359             waves = &waves[1];
  360             num_waves--;
  361         }
  362     }
  363 
  364     fprintf(f, "\n\n");
  365     free(instructions);
  366 }
  367 
  368 static void
  369 radv_dump_annotated_shaders(struct radv_pipeline *pipeline,
  370                 VkShaderStageFlagBits active_stages, FILE *f)
  371 {
  372     struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
  373     enum chip_class chip_class = pipeline->device->physical_device->rad_info.chip_class;
  374     unsigned num_waves = ac_get_wave_info(chip_class, waves);
  375 
  376     fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET
  377         "\n\n", num_waves);
  378 
  379     /* Dump annotated active graphics shaders. */
  380     while (active_stages) {
  381         int stage = u_bit_scan(&active_stages);
  382 
  383         radv_dump_annotated_shader(pipeline->shaders[stage],
  384                        stage, waves, num_waves, f);
  385     }
  386 
  387     /* Print waves executing shaders that are not currently bound. */
  388     unsigned i;
  389     bool found = false;
  390     for (i = 0; i < num_waves; i++) {
  391         if (waves[i].matched)
  392             continue;
  393 
  394         if (!found) {
  395             fprintf(f, COLOR_CYAN
  396                 "Waves not executing currently-bound shaders:"
  397                 COLOR_RESET "\n");
  398             found = true;
  399         }
  400         fprintf(f, "    SE%u SH%u CU%u SIMD%u WAVE%u  EXEC=%016"PRIx64
  401             "  INST=%08X %08X  PC=%"PRIx64"\n",
  402             waves[i].se, waves[i].sh, waves[i].cu, waves[i].simd,
  403             waves[i].wave, waves[i].exec, waves[i].inst_dw0,
  404             waves[i].inst_dw1, waves[i].pc);
  405     }
  406     if (found)
  407         fprintf(f, "\n\n");
  408 }
  409 
  410 static void
  411 radv_dump_shader(struct radv_pipeline *pipeline,
  412          struct radv_shader_variant *shader, gl_shader_stage stage,
  413          FILE *f)
  414 {
  415     if (!shader)
  416         return;
  417 
  418     fprintf(f, "%s:\n\n", radv_get_shader_name(&shader->info, stage));
  419 
  420     if (shader->spirv) {
  421         unsigned char sha1[21];
  422         char sha1buf[41];
  423 
  424         _mesa_sha1_compute(shader->spirv, shader->spirv_size, sha1);
  425         _mesa_sha1_format(sha1buf, sha1);
  426 
  427         fprintf(f, "SPIRV (sha1: %s):\n", sha1buf);
  428         radv_print_spirv(shader->spirv, shader->spirv_size, f);
  429     }
  430 
  431     if (shader->nir_string) {
  432         fprintf(f, "NIR:\n%s\n", shader->nir_string);
  433     }
  434 
  435     fprintf(f, "LLVM IR:\n%s\n", shader->ir_string);
  436     fprintf(f, "DISASM:\n%s\n", shader->disasm_string);
  437 
  438     radv_shader_dump_stats(pipeline->device, shader, stage, f);
  439 }
  440 
  441 static void
  442 radv_dump_shaders(struct radv_pipeline *pipeline,
  443           VkShaderStageFlagBits active_stages, FILE *f)
  444 {
  445     /* Dump active graphics shaders. */
  446     while (active_stages) {
  447         int stage = u_bit_scan(&active_stages);
  448 
  449         radv_dump_shader(pipeline, pipeline->shaders[stage], stage, f);
  450     }
  451 }
  452 
  453 static void
  454 radv_dump_pipeline_state(struct radv_pipeline *pipeline,
  455              VkShaderStageFlagBits active_stages, FILE *f)
  456 {
  457     radv_dump_shaders(pipeline, active_stages, f);
  458     radv_dump_annotated_shaders(pipeline, active_stages, f);
  459 }
  460 
  461 static void
  462 radv_dump_graphics_state(struct radv_device *device,
  463              struct radv_pipeline *graphics_pipeline,
  464              struct radv_pipeline *compute_pipeline, FILE *f)
  465 {
  466     VkShaderStageFlagBits active_stages;
  467 
  468     if (graphics_pipeline) {
  469         active_stages = graphics_pipeline->active_stages;
  470         radv_dump_pipeline_state(graphics_pipeline, active_stages, f);
  471     }
  472 
  473     if (compute_pipeline) {
  474         active_stages = VK_SHADER_STAGE_COMPUTE_BIT;
  475         radv_dump_pipeline_state(compute_pipeline, active_stages, f);
  476     }
  477 
  478     radv_dump_descriptors(device, f);
  479 }
  480 
  481 static void
  482 radv_dump_compute_state(struct radv_device *device,
  483             struct radv_pipeline *compute_pipeline, FILE *f)
  484 {
  485     VkShaderStageFlagBits active_stages = VK_SHADER_STAGE_COMPUTE_BIT;
  486 
  487     if (!compute_pipeline)
  488         return;
  489 
  490     radv_dump_pipeline_state(compute_pipeline, active_stages, f);
  491     radv_dump_descriptors(device, f);
  492 }
  493 
  494 static struct radv_pipeline *
  495 radv_get_saved_graphics_pipeline(struct radv_device *device)
  496 {
  497     uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
  498 
  499     return *(struct radv_pipeline **)(ptr + 1);
  500 }
  501 
  502 static struct radv_pipeline *
  503 radv_get_saved_compute_pipeline(struct radv_device *device)
  504 {
  505     uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
  506 
  507     return *(struct radv_pipeline **)(ptr + 2);
  508 }
  509 
  510 static void
  511 radv_dump_dmesg(FILE *f)
  512 {
  513     char line[2000];
  514     FILE *p;
  515 
  516     p = popen("dmesg | tail -n60", "r");
  517     if (!p)
  518         return;
  519 
  520     fprintf(f, "\nLast 60 lines of dmesg:\n\n");
  521     while (fgets(line, sizeof(line), p))
  522         fputs(line, f);
  523     fprintf(f, "\n");
  524 
  525     pclose(p);
  526 }
  527 
  528 void
  529 radv_dump_enabled_options(struct radv_device *device, FILE *f)
  530 {
  531     uint64_t mask;
  532 
  533     if (device->instance->debug_flags) {
  534         fprintf(f, "Enabled debug options: ");
  535 
  536         mask = device->instance->debug_flags;
  537         while (mask) {
  538             int i = u_bit_scan64(&mask);
  539             fprintf(f, "%s, ", radv_get_debug_option_name(i));
  540         }
  541         fprintf(f, "\n");
  542     }
  543 
  544     if (device->instance->perftest_flags) {
  545         fprintf(f, "Enabled perftest options: ");
  546 
  547         mask = device->instance->perftest_flags;
  548         while (mask) {
  549             int i = u_bit_scan64(&mask);
  550             fprintf(f, "%s, ", radv_get_perftest_option_name(i));
  551         }
  552         fprintf(f, "\n");
  553     }
  554 }
  555 
  556 static void
  557 radv_dump_device_name(struct radv_device *device, FILE *f)
  558 {
  559     struct radeon_info *info = &device->physical_device->rad_info;
  560     char kernel_version[128] = {};
  561     struct utsname uname_data;
  562     const char *chip_name;
  563 
  564     chip_name = device->ws->get_chip_name(device->ws);
  565 
  566     if (uname(&uname_data) == 0)
  567         snprintf(kernel_version, sizeof(kernel_version),
  568              " / %s", uname_data.release);
  569 
  570     fprintf(f, "Device name: %s (%s DRM %i.%i.%i%s, LLVM "
  571         MESA_LLVM_VERSION_STRING ")\n\n",
  572         chip_name, device->physical_device->name,
  573         info->drm_major, info->drm_minor, info->drm_patchlevel,
  574         kernel_version);
  575 }
  576 
  577 static bool
  578 radv_gpu_hang_occured(struct radv_queue *queue, enum ring_type ring)
  579 {
  580     struct radeon_winsys *ws = queue->device->ws;
  581 
  582     if (!ws->ctx_wait_idle(queue->hw_ctx, ring, queue->queue_idx))
  583         return true;
  584 
  585     return false;
  586 }
  587 
  588 void
  589 radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_cmdbuf *cs)
  590 {
  591     struct radv_pipeline *graphics_pipeline, *compute_pipeline;
  592     struct radv_device *device = queue->device;
  593     enum ring_type ring;
  594     uint64_t addr;
  595 
  596     ring = radv_queue_family_to_ring(queue->queue_family_index);
  597 
  598     bool hang_occurred = radv_gpu_hang_occured(queue, ring);
  599     bool vm_fault_occurred = false;
  600     if (queue->device->instance->debug_flags & RADV_DEBUG_VM_FAULTS)
  601         vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
  602                                                 &device->dmesg_timestamp, &addr);
  603     if (!hang_occurred && !vm_fault_occurred)
  604         return;
  605 
  606     graphics_pipeline = radv_get_saved_graphics_pipeline(device);
  607     compute_pipeline = radv_get_saved_compute_pipeline(device);
  608 
  609     radv_dump_trace(queue->device, cs);
  610 
  611     fprintf(stderr, "GPU hang report:\n\n");
  612     radv_dump_device_name(device, stderr);
  613 
  614     radv_dump_enabled_options(device, stderr);
  615     radv_dump_dmesg(stderr);
  616 
  617     if (vm_fault_occurred) {
  618         fprintf(stderr, "VM fault report.\n\n");
  619         fprintf(stderr, "Failing VM page: 0x%08"PRIx64"\n\n", addr);
  620     }
  621 
  622     radv_dump_debug_registers(device, stderr);
  623 
  624     switch (ring) {
  625     case RING_GFX:
  626         fprintf(stderr, "RING_GFX:\n");
  627         radv_dump_graphics_state(queue->device,
  628                      graphics_pipeline, compute_pipeline,
  629                      stderr);
  630         break;
  631     case RING_COMPUTE:
  632         fprintf(stderr, "RING_COMPUTE:\n");
  633         radv_dump_compute_state(queue->device,
  634                     compute_pipeline, stderr);
  635         break;
  636     default:
  637         assert(0);
  638         break;
  639     }
  640 
  641     abort();
  642 }
  643 
  644 void
  645 radv_print_spirv(const char *data, uint32_t size, FILE *fp)
  646 {
  647     char path[] = "/tmp/fileXXXXXX";
  648     char line[2048], command[128];
  649     FILE *p;
  650     int fd;
  651 
  652     /* Dump the binary into a temporary file. */
  653     fd = mkstemp(path);
  654     if (fd < 0)
  655         return;
  656 
  657     if (write(fd, data, size) == -1)
  658         goto fail;
  659 
  660     sprintf(command, "spirv-dis %s", path);
  661 
  662     /* Disassemble using spirv-dis if installed. */
  663     p = popen(command, "r");
  664     if (p) {
  665         while (fgets(line, sizeof(line), p))
  666             fprintf(fp, "%s", line);
  667         pclose(p);
  668     }
  669 
  670 fail:
  671     close(fd);
  672     unlink(path);
  673 }