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    1 /*
    2  * Copyright © 2007-2019 Advanced Micro Devices, Inc.
    3  * All Rights Reserved.
    4  *
    5  * Permission is hereby granted, free of charge, to any person obtaining
    6  * a copy of this software and associated documentation files (the
    7  * "Software"), to deal in the Software without restriction, including
    8  * without limitation the rights to use, copy, modify, merge, publish,
    9  * distribute, sub license, and/or sell copies of the Software, and to
   10  * permit persons to whom the Software is furnished to do so, subject to
   11  * the following conditions:
   12  *
   13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
   14  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
   15  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
   16  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
   17  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
   19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
   20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
   21  *
   22  * The above copyright notice and this permission notice (including the
   23  * next paragraph) shall be included in all copies or substantial portions
   24  * of the Software.
   25  */
   26 
   27 /**
   28 ************************************************************************************************************************
   29 * @file  gfx10addrlib.h
   30 * @brief Contains the Gfx10Lib class definition.
   31 ************************************************************************************************************************
   32 */
   33 
   34 #ifndef __GFX10_ADDR_LIB_H__
   35 #define __GFX10_ADDR_LIB_H__
   36 
   37 #include "addrlib2.h"
   38 #include "coord.h"
   39 #include "gfx10SwizzlePattern.h"
   40 
   41 namespace Addr
   42 {
   43 namespace V2
   44 {
   45 
   46 /**
   47 ************************************************************************************************************************
   48 * @brief GFX10 specific settings structure.
   49 ************************************************************************************************************************
   50 */
   51 struct Gfx10ChipSettings
   52 {
   53     struct
   54     {
   55         UINT_32 reserved1           : 32;
   56 
   57         // Misc configuration bits
   58         UINT_32 isDcn2              : 1;
   59         UINT_32 supportRbPlus       : 1;
   60         UINT_32 dsMipmapHtileFix    : 1;
   61         UINT_32 dccUnsup3DSwDis     : 1;
   62         UINT_32 reserved2           : 28;
   63     };
   64 };
   65 
   66 /**
   67 ************************************************************************************************************************
   68 * @brief GFX10 data surface type.
   69 ************************************************************************************************************************
   70 */
   71 enum Gfx10DataType
   72 {
   73     Gfx10DataColor,
   74     Gfx10DataDepthStencil,
   75     Gfx10DataFmask
   76 };
   77 
   78 const UINT_32 Gfx10LinearSwModeMask = (1u << ADDR_SW_LINEAR);
   79 
   80 const UINT_32 Gfx10Blk256BSwModeMask = (1u << ADDR_SW_256B_S) |
   81                                        (1u << ADDR_SW_256B_D);
   82 
   83 const UINT_32 Gfx10Blk4KBSwModeMask = (1u << ADDR_SW_4KB_S)   |
   84                                       (1u << ADDR_SW_4KB_D)   |
   85                                       (1u << ADDR_SW_4KB_S_X) |
   86                                       (1u << ADDR_SW_4KB_D_X);
   87 
   88 const UINT_32 Gfx10Blk64KBSwModeMask = (1u << ADDR_SW_64KB_S)   |
   89                                        (1u << ADDR_SW_64KB_D)   |
   90                                        (1u << ADDR_SW_64KB_S_T) |
   91                                        (1u << ADDR_SW_64KB_D_T) |
   92                                        (1u << ADDR_SW_64KB_Z_X) |
   93                                        (1u << ADDR_SW_64KB_S_X) |
   94                                        (1u << ADDR_SW_64KB_D_X) |
   95                                        (1u << ADDR_SW_64KB_R_X);
   96 
   97 const UINT_32 Gfx10BlkVarSwModeMask = (1u << ADDR_SW_VAR_Z_X) |
   98                                       (1u << ADDR_SW_VAR_R_X);
   99 
  100 const UINT_32 Gfx10ZSwModeMask = (1u << ADDR_SW_64KB_Z_X) |
  101                                  (1u << ADDR_SW_VAR_Z_X);
  102 
  103 const UINT_32 Gfx10StandardSwModeMask = (1u << ADDR_SW_256B_S)   |
  104                                         (1u << ADDR_SW_4KB_S)    |
  105                                         (1u << ADDR_SW_64KB_S)   |
  106                                         (1u << ADDR_SW_64KB_S_T) |
  107                                         (1u << ADDR_SW_4KB_S_X)  |
  108                                         (1u << ADDR_SW_64KB_S_X);
  109 
  110 const UINT_32 Gfx10DisplaySwModeMask = (1u << ADDR_SW_256B_D)   |
  111                                        (1u << ADDR_SW_4KB_D)    |
  112                                        (1u << ADDR_SW_64KB_D)   |
  113                                        (1u << ADDR_SW_64KB_D_T) |
  114                                        (1u << ADDR_SW_4KB_D_X)  |
  115                                        (1u << ADDR_SW_64KB_D_X);
  116 
  117 const UINT_32 Gfx10RenderSwModeMask = (1u << ADDR_SW_64KB_R_X) |
  118                                       (1u << ADDR_SW_VAR_R_X);
  119 
  120 const UINT_32 Gfx10XSwModeMask = (1u << ADDR_SW_4KB_S_X)  |
  121                                  (1u << ADDR_SW_4KB_D_X)  |
  122                                  (1u << ADDR_SW_64KB_Z_X) |
  123                                  (1u << ADDR_SW_64KB_S_X) |
  124                                  (1u << ADDR_SW_64KB_D_X) |
  125                                  (1u << ADDR_SW_64KB_R_X) |
  126                                  Gfx10BlkVarSwModeMask;
  127 
  128 const UINT_32 Gfx10TSwModeMask = (1u << ADDR_SW_64KB_S_T) |
  129                                  (1u << ADDR_SW_64KB_D_T);
  130 
  131 const UINT_32 Gfx10XorSwModeMask = Gfx10XSwModeMask |
  132                                    Gfx10TSwModeMask;
  133 
  134 const UINT_32 Gfx10Rsrc1dSwModeMask = Gfx10LinearSwModeMask |
  135                                       Gfx10RenderSwModeMask |
  136                                       Gfx10ZSwModeMask;
  137 
  138 const UINT_32 Gfx10Rsrc2dSwModeMask = Gfx10LinearSwModeMask  |
  139                                       Gfx10Blk256BSwModeMask |
  140                                       Gfx10Blk4KBSwModeMask  |
  141                                       Gfx10Blk64KBSwModeMask |
  142                                       Gfx10BlkVarSwModeMask;
  143 
  144 const UINT_32 Gfx10Rsrc3dSwModeMask = (1u << ADDR_SW_LINEAR)   |
  145                                       (1u << ADDR_SW_4KB_S)    |
  146                                       (1u << ADDR_SW_64KB_S)   |
  147                                       (1u << ADDR_SW_64KB_S_T) |
  148                                       (1u << ADDR_SW_4KB_S_X)  |
  149                                       (1u << ADDR_SW_64KB_Z_X) |
  150                                       (1u << ADDR_SW_64KB_S_X) |
  151                                       (1u << ADDR_SW_64KB_D_X) |
  152                                       (1u << ADDR_SW_64KB_R_X) |
  153                                       Gfx10BlkVarSwModeMask;
  154 
  155 const UINT_32 Gfx10Rsrc2dPrtSwModeMask = (Gfx10Blk4KBSwModeMask | Gfx10Blk64KBSwModeMask) & ~Gfx10XSwModeMask;
  156 
  157 const UINT_32 Gfx10Rsrc3dPrtSwModeMask = Gfx10Rsrc2dPrtSwModeMask & ~Gfx10DisplaySwModeMask;
  158 
  159 const UINT_32 Gfx10Rsrc3dThin64KBSwModeMask = (1u << ADDR_SW_64KB_Z_X) |
  160                                               (1u << ADDR_SW_64KB_R_X);
  161 
  162 const UINT_32 Gfx10Rsrc3dThinSwModeMask = Gfx10Rsrc3dThin64KBSwModeMask | Gfx10BlkVarSwModeMask;
  163 
  164 const UINT_32 Gfx10Rsrc3dThickSwModeMask = Gfx10Rsrc3dSwModeMask & ~(Gfx10Rsrc3dThinSwModeMask | Gfx10LinearSwModeMask);
  165 
  166 const UINT_32 Gfx10Rsrc3dThick4KBSwModeMask = Gfx10Rsrc3dThickSwModeMask & Gfx10Blk4KBSwModeMask;
  167 
  168 const UINT_32 Gfx10Rsrc3dThick64KBSwModeMask = Gfx10Rsrc3dThickSwModeMask & Gfx10Blk64KBSwModeMask;
  169 
  170 const UINT_32 Gfx10MsaaSwModeMask = Gfx10ZSwModeMask |
  171                                     Gfx10RenderSwModeMask;
  172 
  173 const UINT_32 Dcn2NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR)   |
  174                                        (1u << ADDR_SW_4KB_S)    |
  175                                        (1u << ADDR_SW_64KB_S)   |
  176                                        (1u << ADDR_SW_64KB_S_T) |
  177                                        (1u << ADDR_SW_4KB_S_X)  |
  178                                        (1u << ADDR_SW_64KB_S_X) |
  179                                        (1u << ADDR_SW_64KB_R_X);
  180 
  181 const UINT_32 Dcn2Bpp64SwModeMask = (1u << ADDR_SW_4KB_D)    |
  182                                     (1u << ADDR_SW_64KB_D)   |
  183                                     (1u << ADDR_SW_64KB_D_T) |
  184                                     (1u << ADDR_SW_4KB_D_X)  |
  185                                     (1u << ADDR_SW_64KB_D_X) |
  186                                     Dcn2NonBpp64SwModeMask;
  187 /**
  188 ************************************************************************************************************************
  189 * @brief This class is the GFX10 specific address library
  190 *        function set.
  191 ************************************************************************************************************************
  192 */
  193 class Gfx10Lib : public Lib
  194 {
  195 public:
  196     /// Creates Gfx10Lib object
  197     static Addr::Lib* CreateObj(const Client* pClient)
  198     {
  199         VOID* pMem = Object::ClientAlloc(sizeof(Gfx10Lib), pClient);
  200         return (pMem != NULL) ? new (pMem) Gfx10Lib(pClient) : NULL;
  201     }
  202 
  203 protected:
  204     Gfx10Lib(const Client* pClient);
  205     virtual ~Gfx10Lib();
  206 
  207     virtual BOOL_32 HwlIsStandardSwizzle(
  208         AddrResourceType resourceType,
  209         AddrSwizzleMode  swizzleMode) const
  210     {
  211         return m_swizzleModeTable[swizzleMode].isStd;
  212     }
  213 
  214     virtual BOOL_32 HwlIsDisplaySwizzle(
  215         AddrResourceType resourceType,
  216         AddrSwizzleMode  swizzleMode) const
  217     {
  218         return m_swizzleModeTable[swizzleMode].isDisp;
  219     }
  220 
  221     virtual BOOL_32 HwlIsThin(
  222         AddrResourceType resourceType,
  223         AddrSwizzleMode  swizzleMode) const
  224     {
  225         return ((IsTex1d(resourceType)  == TRUE) ||
  226                 (IsTex2d(resourceType)  == TRUE) ||
  227                 ((IsTex3d(resourceType) == TRUE)                  &&
  228                  (m_swizzleModeTable[swizzleMode].isStd  == FALSE) &&
  229                  (m_swizzleModeTable[swizzleMode].isDisp == FALSE)));
  230     }
  231 
  232     virtual BOOL_32 HwlIsThick(
  233         AddrResourceType resourceType,
  234         AddrSwizzleMode  swizzleMode) const
  235     {
  236         return ((IsTex3d(resourceType) == TRUE) &&
  237                 (m_swizzleModeTable[swizzleMode].isStd || m_swizzleModeTable[swizzleMode].isDisp));
  238     }
  239 
  240     virtual ADDR_E_RETURNCODE HwlComputeHtileInfo(
  241         const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
  242         ADDR2_COMPUTE_HTILE_INFO_OUTPUT*      pOut) const;
  243 
  244     virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo(
  245         const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
  246         ADDR2_COMPUTE_CMASK_INFO_OUTPUT*      pOut) const;
  247 
  248     virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
  249         const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
  250         ADDR2_COMPUTE_DCCINFO_OUTPUT*      pOut) const;
  251 
  252     virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
  253         const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
  254         ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*      pOut);
  255 
  256     virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
  257         const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
  258         ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT*      pOut);
  259 
  260     virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr(
  261         const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
  262         ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT*      pOut);
  263 
  264     virtual ADDR_E_RETURNCODE HwlComputeDccAddrFromCoord(
  265         const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
  266         ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT*      pOut);
  267 
  268     virtual UINT_32 HwlGetEquationIndex(
  269         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
  270         ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const;
  271 
  272     virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const
  273     {
  274         *ppEquationTable = m_equationTable;
  275 
  276         return m_numEquations;
  277     }
  278 
  279     virtual ADDR_E_RETURNCODE HwlComputePipeBankXor(
  280         const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
  281         ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT*      pOut) const;
  282 
  283     virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor(
  284         const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
  285         ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT*      pOut) const;
  286 
  287     virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern(
  288         const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
  289         ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT*      pOut) const;
  290 
  291     virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting(
  292         const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
  293         ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT*      pOut) const;
  294 
  295     virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck(
  296         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
  297 
  298     virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled(
  299          const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
  300          ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const;
  301 
  302     virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear(
  303          const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
  304          ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const;
  305 
  306     virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled(
  307         const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
  308         ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*      pOut) const;
  309 
  310     virtual UINT_32 HwlComputeMaxBaseAlignments() const;
  311 
  312     virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const;
  313 
  314     virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn);
  315 
  316     virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision);
  317 
  318     // Initialize equation table
  319     VOID InitEquationTable();
  320 
  321     ADDR_E_RETURNCODE ComputeSurfaceInfoMacroTiled(
  322          const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
  323          ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const;
  324 
  325     ADDR_E_RETURNCODE ComputeSurfaceInfoMicroTiled(
  326          const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
  327          ADDR2_COMPUTE_SURFACE_INFO_OUTPUT*      pOut) const;
  328 
  329     ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMacroTiled(
  330         const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
  331         ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*      pOut) const;
  332 
  333     ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMicroTiled(
  334         const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
  335         ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*      pOut) const;
  336 
  337 private:
  338     UINT_32 ComputeOffsetFromSwizzlePattern(
  339         const UINT_64* pPattern,
  340         UINT_32        numBits,
  341         UINT_32        x,
  342         UINT_32        y,
  343         UINT_32        z,
  344         UINT_32        s) const;
  345 
  346     UINT_32 ComputeOffsetFromEquation(
  347         const ADDR_EQUATION* pEq,
  348         UINT_32              x,
  349         UINT_32              y,
  350         UINT_32              z) const;
  351 
  352     ADDR_E_RETURNCODE ComputeStereoInfo(
  353         const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
  354         UINT_32                                 blkHeight,
  355         UINT_32*                                pAlignY,
  356         UINT_32*                                pRightXor) const;
  357 
  358     Dim3d GetDccCompressBlk(
  359         AddrResourceType resourceType,
  360         AddrSwizzleMode  swizzleMode,
  361         UINT_32          bpp) const
  362     {
  363         UINT_32 index = Log2(bpp >> 3);
  364         Dim3d   compressBlkDim;
  365 
  366         if (IsThin(resourceType, swizzleMode))
  367         {
  368             compressBlkDim.w = Block256_2d[index].w;
  369             compressBlkDim.h = Block256_2d[index].h;
  370             compressBlkDim.d = 1;
  371         }
  372         else
  373         {
  374             compressBlkDim = Block256_3d[index];
  375         }
  376 
  377         return compressBlkDim;
  378     }
  379 
  380     static void GetMipSize(
  381         UINT_32  mip0Width,
  382         UINT_32  mip0Height,
  383         UINT_32  mip0Depth,
  384         UINT_32  mipId,
  385         UINT_32* pMipWidth,
  386         UINT_32* pMipHeight,
  387         UINT_32* pMipDepth = NULL)
  388     {
  389         *pMipWidth  = ShiftCeil(Max(mip0Width, 1u),  mipId);
  390         *pMipHeight = ShiftCeil(Max(mip0Height, 1u), mipId);
  391 
  392         if (pMipDepth != NULL)
  393         {
  394             *pMipDepth = ShiftCeil(Max(mip0Depth, 1u),  mipId);
  395         }
  396     }
  397 
  398     const ADDR_SW_PATINFO* GetSwizzlePatternInfo(
  399         AddrSwizzleMode  swizzleMode,
  400         AddrResourceType resourceType,
  401         UINT_32          log2Elem,
  402         UINT_32          numFrag) const;
  403 
  404     VOID GetSwizzlePatternFromPatternInfo(
  405         const ADDR_SW_PATINFO* pPatInfo,
  406         ADDR_BIT_SETTING       (&pSwizzle)[20]) const
  407     {
  408         memcpy(pSwizzle,
  409                GFX10_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx],
  410                sizeof(GFX10_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx]));
  411 
  412         memcpy(&pSwizzle[8],
  413                GFX10_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx],
  414                sizeof(GFX10_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx]));
  415 
  416         memcpy(&pSwizzle[12],
  417                GFX10_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx],
  418                sizeof(GFX10_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx]));
  419 
  420         memcpy(&pSwizzle[16],
  421                GFX10_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx],
  422                sizeof(GFX10_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx]));
  423     }
  424 
  425     VOID ConvertSwizzlePatternToEquation(
  426         UINT_32                elemLog2,
  427         AddrResourceType       rsrcType,
  428         AddrSwizzleMode        swMode,
  429         const ADDR_SW_PATINFO* pPatInfo,
  430         ADDR_EQUATION*         pEquation) const;
  431 
  432     static INT_32 GetMetaElementSizeLog2(Gfx10DataType dataType);
  433 
  434     static INT_32 GetMetaCacheSizeLog2(Gfx10DataType dataType);
  435 
  436     void GetBlk256SizeLog2(
  437         AddrResourceType resourceType,
  438         AddrSwizzleMode  swizzleMode,
  439         UINT_32          elemLog2,
  440         UINT_32          numSamplesLog2,
  441         Dim3d*           pBlock) const;
  442 
  443     void GetCompressedBlockSizeLog2(
  444         Gfx10DataType    dataType,
  445         AddrResourceType resourceType,
  446         AddrSwizzleMode  swizzleMode,
  447         UINT_32          elemLog2,
  448         UINT_32          numSamplesLog2,
  449         Dim3d*           pBlock) const;
  450 
  451     INT_32 GetMetaOverlapLog2(
  452         Gfx10DataType    dataType,
  453         AddrResourceType resourceType,
  454         AddrSwizzleMode  swizzleMode,
  455         UINT_32          elemLog2,
  456         UINT_32          numSamplesLog2) const;
  457 
  458     INT_32 Get3DMetaOverlapLog2(
  459         AddrResourceType resourceType,
  460         AddrSwizzleMode  swizzleMode,
  461         UINT_32          elemLog2) const;
  462 
  463     UINT_32 GetMetaBlkSize(
  464         Gfx10DataType    dataType,
  465         AddrResourceType resourceType,
  466         AddrSwizzleMode  swizzleMode,
  467         UINT_32          elemLog2,
  468         UINT_32          numSamplesLog2,
  469         BOOL_32          pipeAlign,
  470         Dim3d*           pBlock) const;
  471 
  472     INT_32 GetPipeRotateAmount(
  473         AddrResourceType resourceType,
  474         AddrSwizzleMode  swizzleMode) const;
  475 
  476     INT_32 GetEffectiveNumPipes() const
  477     {
  478         return ((m_settings.supportRbPlus == FALSE) ||
  479                 ((m_numSaLog2 + 1) >= m_pipesLog2)) ? m_pipesLog2 : m_numSaLog2 + 1;
  480     }
  481 
  482     BOOL_32 IsRbAligned(
  483         AddrResourceType resourceType,
  484         AddrSwizzleMode  swizzleMode) const
  485     {
  486         const BOOL_32 isRtopt   = IsRtOptSwizzle(swizzleMode);
  487         const BOOL_32 isZ       = IsZOrderSwizzle(swizzleMode);
  488         const BOOL_32 isDisplay = IsDisplaySwizzle(swizzleMode);
  489 
  490         return (IsTex2d(resourceType) && (isRtopt || isZ)) ||
  491                (IsTex3d(resourceType) && isDisplay);
  492 
  493     }
  494 
  495     BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
  496 
  497     UINT_32 GetMaxNumMipsInTail(UINT_32 blockSizeLog2, BOOL_32 isThin) const;
  498 
  499     static ADDR2_BLOCK_SET GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet, AddrResourceType rsrcType)
  500     {
  501         ADDR2_BLOCK_SET allowedBlockSet = {};
  502 
  503         allowedBlockSet.micro  = (allowedSwModeSet.value & Gfx10Blk256BSwModeMask) ? TRUE : FALSE;
  504         allowedBlockSet.linear = (allowedSwModeSet.value & Gfx10LinearSwModeMask)  ? TRUE : FALSE;
  505         allowedBlockSet.var    = (allowedSwModeSet.value & Gfx10BlkVarSwModeMask)  ? TRUE : FALSE;
  506 
  507         if (rsrcType == ADDR_RSRC_TEX_3D)
  508         {
  509             allowedBlockSet.macroThick4KB  = (allowedSwModeSet.value & Gfx10Rsrc3dThick4KBSwModeMask)  ? TRUE : FALSE;
  510             allowedBlockSet.macroThin64KB  = (allowedSwModeSet.value & Gfx10Rsrc3dThin64KBSwModeMask)  ? TRUE : FALSE;
  511             allowedBlockSet.macroThick64KB = (allowedSwModeSet.value & Gfx10Rsrc3dThick64KBSwModeMask) ? TRUE : FALSE;
  512         }
  513         else
  514         {
  515             allowedBlockSet.macroThin4KB  = (allowedSwModeSet.value & Gfx10Blk4KBSwModeMask)  ? TRUE : FALSE;
  516             allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx10Blk64KBSwModeMask) ? TRUE : FALSE;
  517         }
  518 
  519         return allowedBlockSet;
  520     }
  521 
  522     static ADDR2_SWTYPE_SET GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet)
  523     {
  524         ADDR2_SWTYPE_SET allowedSwSet = {};
  525 
  526         allowedSwSet.sw_Z = (allowedSwModeSet.value & Gfx10ZSwModeMask)        ? TRUE : FALSE;
  527         allowedSwSet.sw_S = (allowedSwModeSet.value & Gfx10StandardSwModeMask) ? TRUE : FALSE;
  528         allowedSwSet.sw_D = (allowedSwModeSet.value & Gfx10DisplaySwModeMask)  ? TRUE : FALSE;
  529         allowedSwSet.sw_R = (allowedSwModeSet.value & Gfx10RenderSwModeMask)   ? TRUE : FALSE;
  530 
  531         return allowedSwSet;
  532     }
  533 
  534     BOOL_32 IsInMipTail(
  535         Dim3d   mipTailDim,
  536         UINT_32 maxNumMipsInTail,
  537         UINT_32 mipWidth,
  538         UINT_32 mipHeight,
  539         UINT_32 numMipsToTheEnd) const
  540     {
  541         BOOL_32 inTail = ((mipWidth <= mipTailDim.w) &&
  542                           (mipHeight <= mipTailDim.h) &&
  543                           (numMipsToTheEnd <= maxNumMipsInTail));
  544 
  545         return inTail;
  546     }
  547 
  548     UINT_32 GetBankXorBits(UINT_32 blockBits) const
  549     {
  550         return (blockBits > m_pipeInterleaveLog2 + m_pipesLog2 + ColumnBits) ?
  551                Min(blockBits - m_pipeInterleaveLog2 - m_pipesLog2 - ColumnBits, BankBits) : 0;
  552     }
  553 
  554     BOOL_32 ValidateNonSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
  555     BOOL_32 ValidateSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
  556 
  557     static const UINT_32 ColumnBits       = 2;
  558     static const UINT_32 BankBits         = 4;
  559     static const UINT_32 UnalignedDccType = 3;
  560 
  561     static const Dim3d Block256_3d[MaxNumOfBpp];
  562     static const Dim3d Block64K_Log2_3d[MaxNumOfBpp];
  563     static const Dim3d Block4K_Log2_3d[MaxNumOfBpp];
  564 
  565     static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE];
  566 
  567     // Number of packers log2
  568     UINT_32 m_numPkrLog2;
  569     // Number of shader array log2
  570     UINT_32 m_numSaLog2;
  571 
  572     Gfx10ChipSettings m_settings;
  573 
  574     UINT_32 m_colorBaseIndex;
  575     UINT_32 m_xmaskBaseIndex;
  576     UINT_32 m_dccBaseIndex;
  577 };
  578 
  579 } // V2
  580 } // Addr
  581 
  582 #endif
  583