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Member "memtest86+-5.01/pci.h" (10 Aug 2013, 4282 Bytes) of package /linux/misc/memtest86+-5.01.tar.gz:


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    1 #ifndef MEMTEST_PCI_H
    2 #define MEMTEST_PCI_H
    3 
    4 int pci_conf_read(unsigned bus, unsigned dev, unsigned fn, unsigned reg, 
    5     unsigned len, unsigned long *value);
    6 int pci_conf_write(unsigned bus, unsigned dev, unsigned fn, unsigned reg, 
    7     unsigned len, unsigned long value);
    8 int pci_init(void);
    9 
   10 #define MAKE_PCIE_ADDRESS(bus, device, function) (((bus) & 0xFF)<<20) | (((device) & 0x1F)<<15) | (((function) & 0x7)<<12)
   11 
   12 /*
   13  * Under PCI, each device has 256 bytes of configuration address space,
   14  * of which the first 64 bytes are standardized as follows:
   15  */
   16 #define PCI_VENDOR_ID       0x00    /* 16 bits */
   17 #define PCI_DEVICE_ID       0x02    /* 16 bits */
   18 #define PCI_COMMAND     0x04    /* 16 bits */
   19 #define  PCI_COMMAND_IO     0x1 /* Enable response in I/O space */
   20 #define  PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
   21 #define  PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
   22 #define  PCI_COMMAND_SPECIAL    0x8 /* Enable response to special cycles */
   23 #define  PCI_COMMAND_INVALIDATE 0x10    /* Use memory write and invalidate */
   24 #define  PCI_COMMAND_VGA_PALETTE 0x20   /* Enable palette snooping */
   25 #define  PCI_COMMAND_PARITY 0x40    /* Enable parity checking */
   26 #define  PCI_COMMAND_WAIT   0x80    /* Enable address/data stepping */
   27 #define  PCI_COMMAND_SERR   0x100   /* Enable SERR */
   28 #define  PCI_COMMAND_FAST_BACK  0x200   /* Enable back-to-back writes */
   29 
   30 #define PCI_STATUS      0x06    /* 16 bits */
   31 #define  PCI_STATUS_CAP_LIST    0x10    /* Support Capability List */
   32 #define  PCI_STATUS_66MHZ   0x20    /* Support 66 Mhz PCI 2.1 bus */
   33 #define  PCI_STATUS_UDF     0x40    /* Support User Definable Features [obsolete] */
   34 #define  PCI_STATUS_FAST_BACK   0x80    /* Accept fast-back to back */
   35 #define  PCI_STATUS_PARITY  0x100   /* Detected parity error */
   36 #define  PCI_STATUS_DEVSEL_MASK 0x600   /* DEVSEL timing */
   37 #define  PCI_STATUS_DEVSEL_FAST 0x000   
   38 #define  PCI_STATUS_DEVSEL_MEDIUM 0x200
   39 #define  PCI_STATUS_DEVSEL_SLOW 0x400
   40 #define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
   41 #define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
   42 #define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
   43 #define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
   44 #define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
   45 
   46 #define PCI_CLASS_REVISION  0x08    /* High 24 bits are class, low 8
   47                        revision */
   48 #define PCI_REVISION_ID         0x08    /* Revision ID */
   49 #define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
   50 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
   51 
   52 #define PCI_CACHE_LINE_SIZE 0x0c    /* 8 bits */
   53 #define PCI_LATENCY_TIMER   0x0d    /* 8 bits */
   54 #define PCI_HEADER_TYPE     0x0e    /* 8 bits */
   55 #define  PCI_HEADER_TYPE_NORMAL 0
   56 #define  PCI_HEADER_TYPE_BRIDGE 1
   57 #define  PCI_HEADER_TYPE_CARDBUS 2
   58 
   59 #define PCI_BIST        0x0f    /* 8 bits */
   60 #define PCI_BIST_CODE_MASK  0x0f    /* Return result */
   61 #define PCI_BIST_START      0x40    /* 1 to start BIST, 2 secs or less */
   62 #define PCI_BIST_CAPABLE    0x80    /* 1 if BIST capable */
   63 
   64 /*
   65  * Base addresses specify locations in memory or I/O space.
   66  * Decoded size can be determined by writing a value of 
   67  * 0xffffffff to the register, and reading it back.  Only 
   68  * 1 bits are decoded.
   69  */
   70 #define PCI_BASE_ADDRESS_0  0x10    /* 32 bits */
   71 #define PCI_BASE_ADDRESS_1  0x14    /* 32 bits [htype 0,1 only] */
   72 #define PCI_BASE_ADDRESS_2  0x18    /* 32 bits [htype 0 only] */
   73 #define PCI_BASE_ADDRESS_3  0x1c    /* 32 bits */
   74 #define PCI_BASE_ADDRESS_4  0x20    /* 32 bits */
   75 #define PCI_BASE_ADDRESS_5  0x24    /* 32 bits */
   76 #define  PCI_BASE_ADDRESS_SPACE 0x01    /* 0 = memory, 1 = I/O */
   77 #define  PCI_BASE_ADDRESS_SPACE_IO 0x01
   78 #define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
   79 #define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
   80 #define  PCI_BASE_ADDRESS_MEM_TYPE_32   0x00    /* 32 bit address */
   81 #define  PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02    /* Below 1M [obsolete] */
   82 #define  PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
   83 #define  PCI_BASE_ADDRESS_MEM_PREFETCH  0x08    /* prefetchable? */
   84 #define  PCI_BASE_ADDRESS_MEM_MASK  (~0x0fUL)
   85 #define  PCI_BASE_ADDRESS_IO_MASK   (~0x03UL)
   86 /* bit 1 is reserved if address_space = 1 */
   87 
   88 
   89 /* Device classes and subclasses */
   90 #define PCI_CLASS_NOT_DEFINED       0x0000
   91 #define PCI_CLASS_NOT_DEFINED_VGA   0x0001
   92 
   93 #define PCI_BASE_CLASS_BRIDGE       0x06
   94 #define PCI_CLASS_BRIDGE_HOST       0x0600
   95 
   96 #endif /* MEMTEST_PCI_H */