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Member "linux-5.3.1/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt" (21 Sep 2019, 1866 Bytes) of package /linux/kernel/v5.3/linux-5.3.1.tar.xz:


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    1 * Rockchip RK3328 Clock and Reset Unit
    2 
    3 The RK3328 clock controller generates and supplies clock to various
    4 controllers within the SoC and also implements a reset controller for SoC
    5 peripherals.
    6 
    7 Required Properties:
    8 
    9 - compatible: should be "rockchip,rk3328-cru"
   10 - reg: physical base address of the controller and length of memory mapped
   11   region.
   12 - #clock-cells: should be 1.
   13 - #reset-cells: should be 1.
   14 
   15 Optional Properties:
   16 
   17 - rockchip,grf: phandle to the syscon managing the "general register files"
   18   If missing pll rates are not changeable, due to the missing pll lock status.
   19 
   20 Each clock is assigned an identifier and client nodes can use this identifier
   21 to specify the clock which they consume. All available clocks are defined as
   22 preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
   23 used in device tree sources. Similar macros exist for the reset sources in
   24 these files.
   25 
   26 External clocks:
   27 
   28 There are several clocks that are generated outside the SoC. It is expected
   29 that they are defined using standard clock bindings with following
   30 clock-output-names:
   31  - "xin24m" - crystal input - required,
   32  - "clkin_i2s" - external I2S clock - optional,
   33  - "gmac_clkin" - external GMAC clock - optional
   34  - "phy_50m_out" - output clock of the pll in the mac phy
   35  - "hdmi_phy" - output clock of the hdmi phy pll - optional
   36 
   37 Example: Clock controller node:
   38 
   39 	cru: clock-controller@ff440000 {
   40 		compatible = "rockchip,rk3328-cru";
   41 		reg = <0x0 0xff440000 0x0 0x1000>;
   42 		rockchip,grf = <&grf>;
   43 
   44 		#clock-cells = <1>;
   45 		#reset-cells = <1>;
   46 	};
   47 
   48 Example: UART controller node that consumes the clock generated by the clock
   49   controller:
   50 
   51 	uart0: serial@ff120000 {
   52 		compatible = "snps,dw-apb-uart";
   53 		reg = <0xff120000 0x100>;
   54 		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
   55 		reg-shift = <2>;
   56 		reg-io-width = <4>;
   57 		clocks = <&cru SCLK_UART0>;
   58 	};