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    1 Copyright 2003, 2004, 2006, 2008 Free Software Foundation, Inc.
    2 
    3 This file is part of the GNU MP Library.
    4 
    5 The GNU MP Library is free software; you can redistribute it and/or modify
    6 it under the terms of either:
    7 
    8   * the GNU Lesser General Public License as published by the Free
    9     Software Foundation; either version 3 of the License, or (at your
   10     option) any later version.
   11 
   12 or
   13 
   14   * the GNU General Public License as published by the Free Software
   15     Foundation; either version 2 of the License, or (at your option) any
   16     later version.
   17 
   18 or both in parallel, as here.
   19 
   20 The GNU MP Library is distributed in the hope that it will be useful, but
   21 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   22 or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   23 for more details.
   24 
   25 You should have received copies of the GNU General Public License and the
   26 GNU Lesser General Public License along with the GNU MP Library.  If not,
   27 see https://www.gnu.org/licenses/.
   28 
   29 
   30 
   31 
   32 
   33 			AMD64 MPN SUBROUTINES
   34 
   35 
   36 This directory contains mpn functions for AMD64 chips.  It is also useful
   37 for 64-bit Pentiums, and "Core 2".
   38 
   39 
   40 		     RELEVANT OPTIMIZATION ISSUES
   41 
   42 The Opteron and Athlon64 can sustain up to 3 instructions per cycle, but in
   43 practice that is only possible for integer instructions.  But almost any
   44 three integer instructions can issue simultaneously, including any 3 ALU
   45 operations, including shifts.  Up to two memory operations can issue each
   46 cycle.
   47 
   48 Scheduling typically requires that load-use instructions are split into
   49 separate load and use instructions.  That requires more decode resources,
   50 and it is rarely a win.  Opteron/Athlon64 have deep out-of-order core.
   51 
   52 
   53 Optimizing for 64-bit Pentium4 is probably a waste of time, as the most
   54 critical instructions are very poorly implemented here.  Perhaps we could
   55 save a cycle or two, but the most common loops now run at between 10 and 22
   56 cycles, so a saved cycle isn't too exciting.
   57 
   58 
   59 The new spin of the venerable P6 core, the "Core 2" is much better than the
   60 Pentium4 for the GMP loops.  Its integer pipeline is somewhat similar to to
   61 the Opteron/Athlon64 pipeline, except that the GMP favourites ADC/SBB and
   62 MUL are slower.  Furthermore, an INC/DEC followed by ADC/SBB incur a
   63 pipeline stall of around 10 cycles.  The default mpn_add_n and mpn_sub_n
   64 code suffers badly from the stall.  The code in the core2 subdirectory uses
   65 the almost forgotten instruction JRCXZ for loop control, and updates the
   66 induction variable using LEA.
   67 
   68 
   69 
   70 REFERENCES
   71 
   72 "System V Application Binary Interface AMD64 Architecture Processor
   73 Supplement", draft version 0.99, December 2007.
   74 http://www.x86-64.org/documentation/abi.pdf