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Member "gmp-6.2.1/mpn/mips64/README" (14 Nov 2020, 2019 Bytes) of package /linux/misc/gmp-6.2.1.tar.xz:


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    1 Copyright 1996 Free Software Foundation, Inc.
    2 
    3 This file is part of the GNU MP Library.
    4 
    5 The GNU MP Library is free software; you can redistribute it and/or modify
    6 it under the terms of either:
    7 
    8   * the GNU Lesser General Public License as published by the Free
    9     Software Foundation; either version 3 of the License, or (at your
   10     option) any later version.
   11 
   12 or
   13 
   14   * the GNU General Public License as published by the Free Software
   15     Foundation; either version 2 of the License, or (at your option) any
   16     later version.
   17 
   18 or both in parallel, as here.
   19 
   20 The GNU MP Library is distributed in the hope that it will be useful, but
   21 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   22 or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   23 for more details.
   24 
   25 You should have received copies of the GNU General Public License and the
   26 GNU Lesser General Public License along with the GNU MP Library.  If not,
   27 see https://www.gnu.org/licenses/.
   28 
   29 
   30 
   31 
   32 
   33 This directory contains mpn functions optimized for MIPS3.  Example of
   34 processors that implement MIPS3 are R4000, R4400, R4600, R4700, and R8000.
   35 
   36 RELEVANT OPTIMIZATION ISSUES
   37 
   38 1. On the R4000 and R4400, branches, both the plain and the "likely" ones,
   39    take 3 cycles to execute.  (The fastest possible loop will take 4 cycles,
   40    because of the delay insn.)
   41 
   42    On the R4600, branches takes a single cycle
   43 
   44    On the R8000, branches often take no noticeable cycles, as they are
   45    executed in a separate function unit..
   46 
   47 2. The R4000 and R4400 have a load latency of 4 cycles.
   48 
   49 3. On the R4000 and R4400, multiplies take a data-dependent number of
   50    cycles, contrary to the SGI documentation.  There seem to be 3 or 4
   51    possible latencies.
   52 
   53 4. The R1x000 processors can issue one floating-point operation, two integer
   54    operations, and one memory operation per cycle.  The FPU has very short
   55    latencies, while the integer multiply unit is non-pipelined.  We should
   56    therefore write fp based mpn_Xmul_1.
   57 
   58 STATUS
   59 
   60 Good...