cpuid: ChangeLog

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1 Tue Mar 6 2023 Todd Allen <todd.allen@etallen.com> 2 * Made new release. 3 4 Sun Mar 5 2023 Todd Allen <todd.allen@etallen.com> 5 * Based on Intel-Linux-Processor-Microcode-Data-Files (ILPMDF*), made 6 the following (synth) changes: 7 * cpuid.c: Updated (0,6),(3,7),8 Bay Trail with stepping name C0. 8 * cpuid.c: Added (0,6),(4,5),1 Haswell-ULT C0/D0 stepping. 9 * cpuid.c: Corrected (0,6),(4,6),1 Crystal Well to C0 stepping. 10 * cpuid.c: Updated (0,6),(4,7),1 Broadwell to include E0 stepping. 11 * cpuid.c: Added (0,6),(5,5),3 Skylake B1 (Xeon Scalable). 12 * cpuid.c: Added (0,6),(5,5),5 Skylake A0 (Xeon Scalable). 13 * cpuid.c: Added (0,6),(5,5),11 Cooper Lake A1 (Xeon Scalable). 14 * cpuid.c: Updated (0,6),(5,14),3 Skylake-H/S/E3, adding N0 & S0 15 steppings. 16 * cpuid.c: Added (0,6),(6,10),5 Ice Lake C0 (Xeon Scalable). 17 * cpuid.c: Added (0,6),(6,12),1 Ice Lake B0. 18 * cpuid.c: Updated (0,6),(8,6),4 Snow Ridge with stepping B0. 19 * cpuid.c: Updated (0,6),(8,6),5 Snow Ridge with stepping B1. 20 * cpuid.c: Added (0,6),(8,6),1 Lakefield B2/B3 stepping. 21 * cpuid.c: Corrected (0,6),(8,12),1 Tiger Lake stepping to B1. 22 * cpuid.c: Added (0,6),(8,12),2 Tiger Lake C0. 23 * cpuid.c: Added (0,6),(8,14),10 Coffee Lake D0. 24 * cpuid.c: Added (0,6),(8,14),13 Whiskey Lake-U V0 stepping. 25 * cpuid.c: Added (0,6),(8,15) Sapphire Rapids numerous steppings. 26 * cpuid.c: Updated (0,6),(9,12) Jasper Lake with stepping A1. 27 28 Thu Mar 2 2023 Todd Allen <todd.allen@etallen.com> 29 * cpuid.c: Differentiate (0,6),(8,10) Lakefield P-cores from Tremont 30 E-cores, much as I previously did for Alder Lake & Raptor Lake. 31 * cpuid.c: In decode_uarch_intel, for known Hybrid chips (Alder Lake, 32 Raptor Lake & Lakefield), only decode the uarch if it's one of the two 33 known hybrid types. However, some (0,6),(9,7) Alder Lake's are 34 non-hybrid (Golden Cove only), so also decode core type == 0x00 there. 35 * cpuid.c: In the Intel Core era, uarch families are identified only by 36 the initial uarch in the family. So the family names in {braces}, 37 which also are uarch names, can be confusing. So, change (synth) and 38 (uarch synth) for those families to explain the relationships between 39 the subsequent uarch and the initial uarch, in the form of 40 "shrink of", "optim of", and the unusual "backport of". 41 * cpuid.c: Added (4th Gen) to the (synth) description of (10,15),(1,*) 42 AMD EPYC Genoa. 43 * cpuid.c: Updated (synth) for (10,15),(7,*) AMD Phoenix & Phoenix 2 44 CPUs to claim 4nm process. 45 46 Tue Feb 28 2023 Todd Allen <todd.allen@etallen.com> 47 * Made new release. 48 49 Sun Feb 26 2023 Todd Allen <todd.allen@etallen.com> 50 * cpuid.c: Corrected 7/1/eax fast REP instructions, where I'd left the 51 REP prefix out of the description. 52 53 Wed Feb 22 2023 Todd Allen <todd.allen@etallen.com> 54 * cpuid.c: Added 7/1/eax FRED & LKGS bits, from Intel Flexible Return and 55 Event Deliver (FRED). 56 * cpuid.man: Added Intel Flexible Return and Event Deliver (FRED). 57 * cpuid.c: Clarified 7/1/eax ArchPerfmonExt, which indicates that leaf 58 0x23 is valid. 59 60 Fri Feb 17 2023 Todd Allen <todd.allen@etallen.com> 61 * cpuid.c: Added (uarch synth) decoding for AMD Ryzen (Phoenix E0), based 62 on sample from bakerlab.org, which I missed on Oct 3 2022, when I 63 added the (synth) decoding. 64 * cpuid.c: Added 0x80000001/ebx PkgType decoding for AMD (10,15) Family 65 19h CPUs: (2,1) Vermeer, (5,1) Cezanne/Barcelo, (6,1) Raphael, and 66 (7,0) Phoenix, based on their respective PPPR's. 67 68 Sun Feb 12 2023 Todd Allen <todd.allen@etallen.com> 69 * cpuid.c: Added very early (synth) decoding for Lunar Lake. There is 70 no corresponding (uarch synth) decoding, because no name is yet known 71 for the uarch. 72 73 Sat Feb 11 2023 Todd Allen <todd.allen@etallen.com> 74 * cpuid.c: Added (0,6),(9,10) Alder Lake Core names: i*-12000. 75 * cpuid.c: Differentiate (0,6),(9,7) & (0,6),(9,10) Alder Lake Gracemont 76 E-cores from Golden Cove P-cores. 77 * cpuid.c: Differentiate (0,6),(11,7); (0,6),(11,10) & (0,6),(11,15) 78 Raptor Lake Gracemont E-cores from Raptor Cove P-cores. 79 * cpuid.c: Added (synth) & (uarch synth) decoding for (10,15),(7,8) 80 Phoenix 2, from Coreboot*. 81 * cpuid.c: Renamed print_hypervisor_3_eax_xen to 82 print_hypervisor_3_0_eax_xen. 83 * cpuid.c: Added print_hypervisor_3_0_ebx_xen and decode Xen tsc mode. 84 * cpuid.c: Added (synth) decoding for (10,15),(6,1,1) Raphael B1. 85 86 Fri Jan 20 2023 Todd Allen <todd.allen@etallen.com> 87 * Made new release. 88 89 Fri Jan 20 2023 Todd Allen <todd.allen@etallen.com> 90 * Eliminate reliance on "old" build system. Instead, for the cpuid.i386 91 and cpuid.x86_64, meant to be executable anywhere, including on old 92 hardware & distros, use static builds. They're much bigger, but 93 utterly immune to library changes. 94 95 Wed Jan 18 2023 Todd Allen <todd.allen@etallen.com> 96 * Intel's 13th Generation Core datasheet provides stepping names as 97 well as numbers! So: 98 * cpuid.c: Added synth decoding for (0,6),(11,7) Raptor Lake B0 stepping. 99 * cpuid.c: Added synth decoding for (0,6),(11,15) Raptor Lake C0 100 steppings, and clarified case for unknown stepping. 101 * cpuid.man: Added 743844: 13th Generation Core datasheet. 102 * cpuid.c: Fixed (0,6)(12,15) synth typo: Emearld Rapids. 103 104 Tue Jan 17 2023 Todd Allen <todd.allen@etallen.com> 105 * cpuid.c: Added 6/eax IA32_HW_FEEDBACK_THREAD_CONFIG bit 25. 106 * cpuid.c: Added 7/0/edx SGX-KEYS: SGX attestation services. 107 * cpuid.c: Clarified 7/0/edx IA32_MCU_OPT_CTRL SRBDS mitigation MSR. 108 * cpuid.c: Clarified 7/0/edx IA32_TSX_FORCE_ABORT MSR. 109 * cpuid.c: Added 7/1/edx CET_SSS: shadow stacks w/o page faults. 110 * cpuid.c: Added several 7/2/edx bits. 111 * cpuid.c: In 0xd/0/eax, corrected CET_U & CET_S, which were IA32_XSS. 112 * cpuid.c: In 0xd/0/eax, removed the IA32_XSS bits, which aren't 113 relevant for XCR0. 114 * cpuid.c: For 0xd/1/ecx, enumerate the IA32_XSS bits instead of a 115 hex bitmask. 116 * cpuid.c: For 0xd, added IA32_XSS PASID state (couple places). 117 * cpuid.c: Renamed 0x1a: Native Model ID. 118 * cpuid.c: Added synth & uarch decoding for (0,6),(11,15) Raptor Lake 119 from MSR_CPUID_table*. 120 * cpuid.c: Added synth decoding for (0,6),(9,7),5 Pentium Gold G7400, 121 based on instlatx64 sample. 122 * cpuid.c: Added rudimentary synth decoding for future (0,6),(12,15) 123 Emerald Rapids CPUs. 124 * cpuid.c: Added 7/1/eax LASS: linear address space separation. 125 * cpuid.c: Corrected 0x18/n/edx maximum number of addressible IDs, which 126 should use minus-one notation. 127 128 Tue Jan 17 2023 Todd Allen <todd.allen@etallen.com> 129 * cpuid.c: Certain leaves cannot be displayed correctly in isolation, 130 i.e. without information about other leaves saved in the stash. For 131 example, the display for leaf 3 uses bits saved from leaf 1. If the 132 -l/--leaf option is used to restrict cpuid to reading only a single 133 leaf, such leaves now are displayed as raw hex, rather than with 134 incorrect information. This is handled by passing a NULL stash to 135 print_reg() and below, and by many new checks for a NULL stash. 136 Thanks to Bill Zissimopoulos for the bug report. 137 138 Mon Jan 9 2023 Todd Allen <todd.allen@etallen.com> 139 * cpuid.c: Updated cache associativity strings used in 0x80000006 and 140 0x80000019 leaves to use value ranges, as in AMD docs. 141 * cpuid.c: Fixed mistake in AMD L3 range reservation support: it's in 142 0x80000020/0 register EBX, not ECX. 143 * cpuid.c: Added 0x80000026/0/edx extended APIC ID. 144 145 Tue Dec 13 2022 Todd Allen <todd.allen@etallen.com> 146 * cpuid.c: Added synth & uarch decoding for (10,15),(1,1) Genoa, from 147 AMD 57095 revision guide. 148 * cpuid.man: Added AMD 57095 revision guides, and some older guides that 149 I'd forgotten. 150 151 Thu Dec 1 2022 Todd Allen <todd.allen@etallen.com> 152 * Made new release. 153 154 Wed Nov 30 2022 Todd Allen <todd.allen@etallen.com> 155 * Clarified synth decoding for Intel Xeon D-1700. 156 157 Wed Nov 30 2022 Todd Allen <todd.allen@etallen.com> 158 * Added uarch & synth decoding for AMD 4800S Desktop Kit, based on 159 instlatx64 sample. The generation is known to be Zen 2 (7nm), but 160 the core is unknown. I heard speculation for each of Ariel (rejected 161 PlayStation 5 CPU), or Lockhart/Scarlett (rejected Xbox CPU). 162 * Added uarch decoding for AMD Genoa A1, based on instlatx64 sample 163 from @IanCutress. 164 165 Mon Nov 28 2022 Todd Allen <todd.allen@etallen.com> 166 * Added uarch decoding for (0,6),(12,15) Emerald Rapids, from LX*. 167 168 Mon Nov 28 2022 Todd Allen <todd.allen@etallen.com> 169 * Added synth & uarch decoding for (10,15),(10,1) Bergamo. 170 171 Mon Nov 28 2022 Todd Allen <todd.allen@etallen.com> 172 * Added 0x8000000a/edx bits: ROGPT, VNMI, IBS virtualization. 173 * Added 0x8000001b/eax bit: IBS L3 miss filtering support. 174 * Added 0x8000001f/eax bits: RMPQUERY instruction support, 175 VMPL supervisor shadow stack support, VMGEXIT parameter support, 176 virtual TOM MSR support, IBS virtual support for SEV-ES guests, 177 SMT protection support, SVSM communication page MSR support, 178 VIRT_RMPUPDATE & VIRT_PSMASH MSR support. 179 * Added 0x80000020/0/ecx bit: L3 range reservation support. 180 * Added 0x80000021/eax bits: automatic IBRS, 181 CPUID disable for non-privileged. 182 * Added 0x80000022/eax bit: AMD LBR & PMC freezing. 183 * Added 0x80000022/ebx field: number of LBR stack entries. 184 * Added 0x80000023 leaf: Multi-Key Encrypted Memory Capabilities. 185 * Added 0x80000026 leaf: AMD Extended CPU Topology. 186 187 Fri Nov 11 2022 Mateusz Guzik <mjguzik@gmail.com> 188 * cpuid.c: FreeBSD patch to use lseek64 and cpuset_setaffinity. 189 190 Tue Oct 11 2022 Todd Allen <todd.allen@etallen.com> 191 * cpuid.c: Added 0x80000022/eax AMD LBR V2 flag, from LX*. 192 * cpuid.c: Note that (8,15),(10,0) Mendocino now is documented. 193 194 Mon Oct 3 2022 Todd Allen <todd.allen@etallen.com> 195 * Made new release. 196 197 Mon Oct 3 2022 Todd Allen <todd.allen@etallen.com> 198 * cpuid.c: Added synth decoding for AMD Ryzen (Phoenix E0), based on 199 sample from bakerlab.org. 200 * cpuid.c: Added synth decoding for AMD Ryzen (Storm Peak A1), based on 201 sample from einstein11.aei.uni-hannover.de. 202 * cpuid.c: Added synth & uarch synth decoding for (0,6),(11,5) Intel 203 Meteor Lake, based on MSR_CPUID_table*. 204 * cpuid.c: Added synth & uarch synth decoding for (0,6),(11,6) Intel 205 Grand Ridge (Crestmont), based on MSR_CPUID_table*. 206 * cpuid.c: Added synth & uarch synth decoding for (0,6),(11,14) Intel 207 Granite Rapids, based on MSR_CPUID_table*. 208 * cpuid.c: Confirmed several other existing synth & uarch decodings based 209 on MSR_CPUID_table*, and updated comments (no functional changes). 210 * cpuid.c: Renamed 7/0/eax enh hardware feedback to simply Thread 211 Director. Evidently, Intel just calls it that now too. 212 * cpuid.c: Added 7/1/eax RAO-INT instructions, CMPccXADD instructions, 213 ArchPerfmonExt is valid, WRMSRNS instructions, AMX-FP16, AVX-IFMA, 214 RDMSRLIST & WRMSRLIST. 215 * cpuid.c: Added 7/1/edx AVX-VNNI-INT8, AVX-NE-CONVERT, PREFETCHIT* 216 instructions. 217 * cpuid.c: Added 0x12/0/eax SGX ENCLU EDECCSA flag. 218 * cpuid.c: Added 0x23 Architecture Performance Monitoring Extended leaf 219 decoding. 220 * cpuid.c: Corrected AVX512IFMA description: integer FMA, not just FMA. 221 222 Tue Sep 27 2022 Todd Allen <todd.allen@etallen.com> 223 * Made new release. 224 225 Tue Sep 27 2022 Todd Allen <todd.allen@etallen.com> 226 * cpuid.c: Added synth decoding for (10,15),(6,1) Raphael, based on 227 instlatx64 samples. 228 229 Wed Aug 17 2022 Todd Allen <todd.allen@etallen.com> 230 * cpuid.c: Fixed missing return statement in get_nr_cpu_ids()'s default 231 case, used by Cygwin. Thanks to Brian Inglis for reporting this. 232 233 Tue Aug 16 2022 Umio-Yasuno <coelacanth_dream@proton.me> 234 * cpuid.c: Fixed title for AMD 0x8000001a leaf: Performance Optimization 235 Identifiers. 236 237 Fri Aug 12 2022 Todd Allen <todd.allen@etallen.com> 238 * Made new release. 239 240 Fri Aug 12 2022 Todd Allen <todd.allen@etallen.com> 241 * cpuid.c: Corrected (synth) decoding for (0,6),(8,6) Intel Snow 242 Ridge/Parker Ridge. It had been lumped in with Elkhart Lake, but only 243 because that had been the only known core name for the Tremont uarch. 244 These appear to be different cores. Also added steppings from SSG*. 245 246 Fri Aug 5 2022 Todd Allen <todd.allen@etallen.com> 247 * cpuid.c: Added 8000000a/edx X2AVIC flag, from Linux kernel patches 248 It appears to be undocumented, so far. 249 250 Thu Aug 4 2022 Todd Allen <todd.allen@etallen.com> 251 * cpuid.c: Improved (synth) decoding for (0,6),(9,7),2, adding 252 Added Alder Lake-HX. 253 254 Wed Jul 27 2022 Todd Allen <todd.allen@etallen.com> 255 * cpuid.c: Reverted May 27 2022 split of 7/0/ebx hack to report bit 22 256 as RDPID on AMD architectures. The AMD documentation is inconsistent 257 on the location of this flag. In E.3.6, it claims 7/0/ebx. But in 258 section 3, the RDPID instruction itself claims 7/0/ecx, as does the 259 mention in Table 3-1. This also is consistent with Intel 260 architectures. Thanks to Stefan Kanthak for pointing this out. 261 262 Mon Jul 25 2022 Todd Allen <todd.allen@etallen.com> 263 * cpuid.c: Generalized (0,6),(8,14),9,YP stepping case to include 264 Pentium 4425Y, from instlatx64 sample. 265 266 Thu Jul 14 2022 Todd Allen <todd.allen@etallen.com> 267 * cpuid.c: Updated 7/0/edx comments to reflect original info source 268 for SRBDS mitigation MSR available, previously just marked LX*. 269 * cpuid.c: Updated 7/0/edx comments to reflect original info source 270 for RTM transaction always aborts, previously just marked LX*. 271 * cpuid.c: Added (vuln to branch type confusion synth) synthetic leaf 272 to correct for the one known inaccuracy. 273 * cpuid.man: Added those two original source web pages from Intel: 274 Intel Transactional Synchronization Extensions (Intel TSX) Memory and 275 Performance Monitoring Update for Intel Processors (Article ID 276 000059422), Special Register Buffer Data Sampling. 277 278 Wed Jul 13 2022 Todd Allen <todd.allen@etallen.com> 279 * cpuid.c: Added 0x80000008/ebx not vulnerable to branch type confusion 280 flag from "Technical Guidance For Mitigating Branch Type Confusion 281 (White Paper)". Also added a synthetic flag to correct the special 282 case for Family 0x19, where the raw flag is documented to be wrong. 283 * cpuid.c: Added 7/2/edx indirect branch prediction related flags from 284 Intel's "Branch History Injection and Intra-mode Branch Target 285 Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598". 286 * cpuid.c: Added (uarch synth) decoding for (0,6),(6,14) Cougar 287 Mountain, mentioned as Airmont by Intel's "Retpoline: A Branch Target 288 Injection Mitigation". 289 * cpuid.man: Added "Branch History Injection and Intra-mode Branch Target 290 Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598" and 291 "Retpoline: A Branch Target Injection Mitigation". 292 293 Tue Jul 12 2022 Todd Allen <todd.allen@etallen.com> 294 * cpuid.c: Clarified (synth) for (0,6),(8,13) Tiger Lake-H from SSG*. 295 296 Tue Jul 12 2022 Todd Allen <todd.allen@etallen.com> 297 * cpuid.c: Added support for hypervisor+3/ecx (Microsoft) flags. 298 * cpuid.c: Added support for hypervisor+0xa/eax (Microsoft) VMCS 299 GuestIa32DebugCtl support flag. 300 * cpuid.c: Added support for hypervisor+0xa/ebx (Microsoft) VMCS 301 HvFlushGuestPhysicalAddress* flag. 302 303 Wed Jun 29 2022 Todd Allen <todd.allen@etallen.com> 304 * cpuid.c: Added (synth) for (0,6),(11,10),3 Raptor Lake-P Q0, from 305 Coreboot*. 306 307 Sat Jun 25 2022 Todd Allen <todd.allen@etallen.com> 308 * cpuid.c: Lionel Debroux's patch used MAX_CPUS all the time. But it 309 really was meaningful only for the USE_KERNEL_SCHED_SETAFFINITY case 310 (although, by happenstance, it may have been correct for all three 311 cases). Replace this with an nr_cpu_ids global, determined by 312 get_nr_cpu_ids(). The simplest version just returns 313 sysconf(_SC_NPROCESSORS_CONF), although that could be problematic on 314 systems with non-contiguous CPU numbers. 315 * cpuid.c: For USE_KERNEL_SCHED_SETAFFINITY, improve this, and also 316 support systems with > 1024 CPUs, by estimating nr_cpu_ids using a 317 power-of-2 walk through successively larger cpu_set_t sizes until 318 sched_getaffinity succeeds. 319 * cpuid.c: For systems using cpu_set_t (only Cygwin?), cap the 320 nr_cpu_ids to CPU_SETSIZE. 321 * cpuid.c: The _SC_NPROCESSORS_CONF check in real_setup() is removed 322 because it's redundant now. 323 324 Wed Jun 22 2022 Lionel Debroux <lionel_debroux@yahoo.fr> 325 * cpuid.c: In do_real() and do_real_one(), avoid breaking out of loop 326 because of downed CPUs. 327 328 Mon Jun 20 2022 Todd Allen <todd.allen@etallen.com> 329 * Made new release. 330 331 Sat Jun 18 2022 Todd Allen <todd.allen@etallen.com> 332 * cpuid.c: Added (synth) for (0,6),(9,7),1 Alder Lake-S B0 from 333 Coreboot*. 334 * cpuid.c: Added (synth) stepping name for (0,6),(9,7),4 Alder Lake-U G0 335 from Coreboot* (although this dubiously mixes partly contradictory 336 info from two sources). 337 * cpuid.c: Added (synth) stepping name for (0,6),(9,7),5 Alder Lake-S H0 338 from Coreboot*. 339 * cpuid.c: Added hypervisor+4/eax (Xen) upcalls with physical IRQ 340 vectors from Xen*. 341 * cpuid.c: Added hypervisor+{0x80,0x81,0x82} (Microsoft) synthetic 342 debugging leaves. 343 * cpuid.c: Eliminated print_header(), and distributed those headers 344 throughout print_reg(), frequently using the try (subleaf) number to 345 ensure they are printed only once. Many headers already were like 346 this, and it makes them more consistent. 347 348 Sun Jun 12 2022 Todd Allen <todd.allen@etallen.com> 349 * cpuid.c: Changed (synth) for Alder Lake-S to remove K/KF suffixes, 350 because other suffixes (or no suffix) are available too. 351 * cpuid.c: Added (synth) for (0,6),(9,7),5 Alder Lake-S. 352 * cpuid.c: Added (synth) for (0,6),(9,7),3 Alder Lake-P/H. 353 * cpuid.c: Added (synth) for (0,6),(9,7),4 Alder Lake-U. 354 355 Sat Jun 11 2022 Todd Allen <todd.allen@etallen.com> 356 * cpuid.c: Added 0xf/1/eax QoS monitoring counter size, both in raw 357 form (-24 notation) and as a synthetic leaf the determines the 358 value from the raw form and family/model information. 359 * cpuid.c: Added stash information to print_header() to avoid printing 360 Xen-only headers for hypervisor+3 leaves of other hypervisors. 361 * cpuid.c: Rewrote the handling of subleaves (tries) for legacy raw 362 input files. Originally, I thought I only needed this support for 363 those leaves which existed during that legacy period. But the 364 testbeds lean on that support for samples from instlatx64. So now 365 it's more general. 366 * cpuid.c: For leaf 0x80000020, rewrote the rules for subleaf processing 367 based on the description in AMD64 Technology Platform Quality of 368 Service Extensions (pub 56375 1.03): walk the bits in the mask. 369 * cpuid.c: Added 0x80000020/0/ebx bits 2 & 3, and renamed bit 1. 370 * cpuid.c: Added 0x80000020/1 subleaf header. 371 * cpuid.c: Added 0x80000020/2 subleaf. 372 * cpuid.c: Added 0x80000020/3 subleaf. 373 * cpuid.man: Added 56375: AMD64 Technology Platform Quality of Service 374 Extensions 375 376 Fri May 27 2022 Todd Allen <todd.allen@etallen.com> 377 * cpuid.c: Added 0x8000001f/eax virtual TSC_AUX supported, from Linux 378 kernel. 379 * cpuid.c: Split 7/0/ebx decoding into Intel-specific & AMD-specific 380 versions (using ugly macro to avoid code duplication), differing by 381 bit 22: PCOMMIT (intel) vs. RDPID/TSC_AUX (amd). 382 383 Wed May 25 2022 Todd Allen <todd.allen@etallen.com> 384 * cpuid.c: Added 0x80000022/eax AMD perfmon V2, from Linux kernel. 385 386 Tue May 24 2022 Todd Allen <todd.allen@etallen.com> 387 * cpuid.c: Added 0x21 TDX guest leaf, as ASCII text 388 (e.g. "IntelTDX "). 389 390 Sat May 21 2022 Todd Allen <todd.allen@etallen.com> 391 * cpuid.c: Changed (synth) for AMD (10,15),(5,*) Cezanne to also mention 392 Barcelo, because instlatx64 samples show that they seem to be 393 indistinguishable from cpuid information. 394 395 Tue May 17 2022 Todd Allen <todd.allen@etallen.com> 396 * cpuid.c: Added synth decoding for stepping (0,6),(11,10),2 397 Raptor Lake-P J0 from Coreboot*. 398 399 Tue May 3 2022 Todd Allen <todd.allen@etallen.com> 400 * cpuid.man: Added 344425, "Architecture Specification: Intel Trust 401 Domain Extensions (Intel TDX) Module". 402 * cpuid.c: Removed 7/0/ecx bus lock detection LX*, Qemu* comment, 403 because it now is documented in the above. 404 * cpuid.man: Added 343754, "Intel Trust Domain CPU Architectural 405 Extensions". 406 * cpuid.c: Added 0x12/0/eax bit 7: EVERIFYREPORT2 support, from the 407 above. 408 409 Tue May 3 2022 Stefan Kanthak <stefan.kanthak@nexgo.de> 410 * cpuid.c: Corrected spelling of 7/0/ecx "RDPID: read processor ID 411 supported". 412 413 Mon May 2 2022 Todd Allen <todd.allen@etallen.com> 414 * cpuid.c: Clarified (synth) decoding for (10,15),(11,14) Alder Lake-N, 415 based on LX*. Also added A0 stepping. 416 * cpuid.c: Added defined() checks around uses of __GNUC__, 417 __GNUC_MINOR__, and __GNUC_PATCHLEVEL__, as suggested by Stefan 418 Kanthak. 419 * Makefile: Added -Wundef to compilation options to check the above, 420 although they always are defined with gcc. 421 * cpuid.c: To simplify the new #if's for __builtin_clzl, added new 422 USE_BUILTIN_CLZL macro. 423 424 Sat Apr 30 2022 Todd Allen <todd.allen@etallen.com> 425 * cpuid.c: Added (synth) decoding for (10,15),(0,1),2 Milan B2 stepping. 426 427 Tue Apr 5 2022 Todd Allen <todd.allen@etallen.com> 428 * cpuid.c: Changed (0,6),(9,10) Alder Lake synth decoding stepping names, 429 based on Coreboot*, evidently from Intel doc 626774. I cannot find 430 that document. Perhaps it is under NDA. 431 * cpuid.c: Added (0,6),(1,9) ZhangJiang synth & uarch decoding from 432 Google_cpu_features*. 433 * cpuid.c: Added (0,7),(1,11) WuDaoKou synth & uarch decoding from 434 Google_cpu_features*. Also corrected (0,7),(0,11) uarch decoding. 435 * cpuid.c: Added (0,7),(3,11) LuJiaZui uarch decoding from 436 Google_cpu_features*. Also simplified its synth decoding. 437 * cpuid.c: Added (0,7),(5,11) YongFeng synth & uarch decoding from 438 Google_cpu_features*. Still somewhat speculative. 439 440 Fri Mar 25 2022 Todd Allen <todd.allen@etallen.com> 441 * cpuid.c: Added hypervisor+4/eax (Microsoft) bits 15, 17, 18. 442 * cpuid.c: Added hypervisor+4/ecx (Microsoft) leaf. 443 * cpuid.c: Added many hypervisor+6/eax (Microsoft) fields. 444 * cpuid.c: Added hypervisor+0xa/eax (Microsoft) bit 22. 445 * cpuid.c: Added hypervisor+3/ebx (Microsoft) Isolation flag, from Linux 446 kernel (arch/x86/include/asm/hyperv-tlfs.h). 447 * cpuid.c: Added hypervisor+0xc/{eax,ebx} (Microsoft) leaves, from Linux 448 kernel (arch/x86/include/asm/hyperv-tlfs.h). 449 450 Fri Mar 18 2022 Todd Allen <todd.allen@etallen.com> 451 * cpuid.c: Corrected (synth) for (0,6),(9,10) Alder Lake to report Core 452 where appropriate, instead of Atom always. In fact, I've seen zero 453 instances of Atoms with this core, so perhaps this was an early 454 misunderstanding. The (0,6),(9,7) Alder Lake-S core was added at the 455 same time, also as an Atom, but was corrected much earlier. So I've 456 made the same correction here. 457 458 Sat Mar 12 2022 Todd Allen <todd.allen@etallen.com> 459 * cpuid.c: Added (synth) decoding for (8,15),(9,0),2 Van Gogh A2 from 460 instlatx64 sample. 461 462 Thu Mar 10 2022 Todd Allen <todd.allen@etallen.com> 463 * cpuid.c: Added (synth) decoding for (0,6),(10,10),{0-1} A0 steppings, 464 based on info from Coreboot*. 465 466 Thu Feb 24 2022 Todd Allen <todd.allen@etallen.com> 467 * Made new release. 468 469 Wed Feb 23 2022 Todd Allen <todd.allen@etallen.com> 470 * cpuid.c: Added (synth) and (uarch synth) decoding for AMD Rembrandt E1. 471 472 Sat Feb 19 2022 Todd Allen <todd.allen@etallen.com> 473 * cpuid.c: Added hypervisor+4/eax (Xen) expanded destination id bit. 474 475 Mon Jan 17 2022 Todd Allen <todd.allen@etallen.com> 476 * cpuid.c: Removed bogus 7/1/eax bit 24 "AMX tile support". The only 477 claim for that was an inaccurate comment in the linux kernel, added 478 2-Nov-2021, but the actual bit is in 7/0/edx, which already was 479 present in cpuid. 480 481 Sun Jan 9 2022 Todd Allen <todd.allen@etallen.com> 482 * cpuid.c: Renamed 6/eax bit to 23 to mention Thread Director. 483 * cpuid.c: Widened 6/ecx number of enh hardware feedback classes from 484 bits 8-11 to bits 8-15. 485 * cpuid.c: Renamed 7/1/eax bit to 10 to include "fast". 486 * cpuid.c: Added 7/1/ebx decoding. 487 * cpuid.c: Added 0x14/0/ebx decoding for support for IA32_RTIT_CTL 488 EventEn & DisTNT bits. 489 * cpuid.c: Added synth decoding for (0,6),(11,15) Alder Lake, based on 490 MSR_CPUID_table*. 491 * cpuid.c: Confirmed synth decoding for (0,6),(10,8) Rocket Lake. 492 493 Tue Jan 4 2022 Todd Allen <todd.allen@etallen.com> 494 * cpuid.c: Added (synth) steppings based on instlatx64 samples: 495 1,(0,5),(0,3),2 P24T C0, (0,6),(0,2),2 K75/Pluto/Orion A2, 496 (0,6),(4,6),1 Crystal Well C1, (0,6),(7,14),5 Ice Lake-U/Y D1, 497 (0,6),(9,7),2 Alder Lake-S C0, (0,6),(10,7),1 Rocket Lake B0. 498 * cpuid.c: Corrected missing Core name for (0,6),(9,7) Alder Lake-S A0 499 stepping. 500 501 Mon Dec 13 2021 Todd Allen <todd.allen@etallen.com> 502 * cpuid.c: In 0x18 leaves, line up values better. 503 504 Fri Dec 10 2021 Todd Allen <todd.allen@etallen.com> 505 * Made new release. 506 507 Fri Dec 10 2021 Todd Allen <todd.allen@etallen.com> 508 * cpuid.c: Reorganized loop over 0x12 subleaves in do_real(). The old 509 code assumed validity was at least partially determined by a bitmask 510 in subleaf 0 (like for leaf 0x10), but that was wrong. Thanks to 511 Scott Raynor for pointing this out. 512 * cpuid.c: Added code for 0x12/(n>=2) subleaves to show invalid cases as 513 such, instead of resorting to a raw dump. 514 * cpuid.c: Fixed missing loop over 0x1b subleaves in do_real(). This 515 might become necessary if more target identifiers are added. 516 * cpuid.c: Added print_1b_n_target() to decode the MKTME target 517 identifier. 518 * cpuid.c: Modified leaf 4 subleaf loop to include the terminating 519 "no more caches" subleaf. Modified print_reg() to abbreviate 520 "no more caches" subleaves. 521 * cpuid.c: Cleaned up loops for leaves 7, 0x14, 0x17, 0x18, 0x1d, 0x20 522 subleaves: max_tries (from subleaf 0) is available before the loop 523 starts. 524 * cpuid.c: Modified leaf 0xb subleaf loop to exit for the right reason, 525 level type == 0. Also, it includes the terminating "invalid" subleaf. 526 The similiar 0x1f leaf already did this. 527 528 Mon Nov 29 2021 Todd Allen <todd.allen@etallen.com> 529 * Made new release. 530 531 Fri Nov 26 2021 Todd Allen <todd.allen@etallen.com> 532 * From AMD Programmer's Manual, Vol 3, Rev 3.33, Appendix E: 533 * cpuid.c: Added 0x80000008/ebx CPU prefers: IBRS always on. 534 * cpuid.c: Renamed 0x80000008/ebx CPU prefers: STIBP always on. 535 * cpuid.c: Renamed 0x80000008/ebx INVLPGB supports TLB flush guest 536 nested. 537 * cpuid.c: Added 0x8000001f/eax Secure TSC supported. 538 * cpuid.c: Added 0x8000001f/eax VMSA register protection. 539 * cpuid.c: Added 0x80000021/eax upper address ignore support. 540 * cpuid.c: Added 0x80000021/eax SMM_CTL MSR not supported 541 * cpuid.c: Added 0x80000021/ebx. 542 * cpuid.c: Added 0x80000022/ebx. 543 544 Mon Nov 22 2021 Todd Allen <todd.allen@etallen.com> 545 * cpuid.c: Correct (uarch synth) phys for Cascade Lake to 14nm++. 546 * cpuid.c: Correct (uarch synth) phys for Cooper Lake to 14nm++. 547 548 Sun Nov 21 2021 Todd Allen <todd.allen@etallen.com> 549 * Made new release. 550 551 Sun Nov 21 2021 Todd Allen <todd.allen@etallen.com> 552 * cpuid.c: Removed __LARGE64_FILES from __CYGWIN__, per Brian Inglis' 553 request. 554 * cpuid.c: Renamed macros with names starting with underscores, which 555 are resered names in C: __THING -> MaskTHING, _THING -> ShftTHING. 556 Brian Inglis says this was an actual practical problem in Cygwin. 557 This change makes the code less dense, but a bit easier to understand. 558 559 Sat Nov 20 2021 Todd Allen <todd.allen@etallen.com> 560 * cpuid.c: Distinguish (synth) decoding: AMD (8,15),(2,0) Dali CPUs: 561 Ryzen vs. other. 562 * cpuid.c: Added to (synth) decoding: AMD Ryzen 1000/2000/3000/4000/5000 563 series numbers. 564 * cpuid.c: Added to (synth) decoding: AMD Epyc Gen numbers. 565 * cpuid.c: Distinguish (synth) decodings for Threadripper CPUs. For 566 Zen & Zen+, only the brand distinguishes; for Zen 2 (and rumored for 567 Zen 3), there are distinct models. 568 * cpuid.c: Distinguish (synth) decoding between Great Horned Owl & Banded 569 Kestrel. 570 * cpuid.c: Distinguish (synth) decoding for Grey Hawk from Renoir. 571 572 Thu Nov 18 2021 Todd Allen <todd.allen@etallen.com> 573 * cpuid.c: Added (synth) & (uarch synth) decoding for (0,6),(11,14) 574 Golden Cove (Alder Lake) from Coreboot*. 575 * cpuid.c: Added (synth) & (uarch synth) decoding for (0,6),(6,7) 576 Palm Cove (Cannon Lake) from DPTF*. 577 * cpuid.c: Added (synth) & (uarch synth) decoding for (0,6),(10,11) 578 Redwood Cove (Meteor Lake-N) from DPTF*. 579 * cpuid.c: Added (synth) & (uarch synth) decoding for (0,6),(11,10) 580 Raptor Cove (Raptor Lake-P) from DPTF*. 581 582 Mon Nov 15 2021 Todd Allen <todd.allen@etallen.com> 583 * cpuid.c: Added (synth) decoding for (0,6),(11,7) Raptor Lake, from LX*. 584 * cpuid.c: Updated (uarch synth) phys strings for Intel 14nm and 10nm 585 process nodes using 14nm+, 14nm++, 14nm+++, 10nm+, 10nm++. 586 587 Sun Nov 14 2021 Todd Allen <todd.allen@etallen.com> 588 * Made new release. 589 590 Mon Nov 8 2021 Todd Allen <todd.allen@etallen.com> 591 * cpuid.c: Updated (uarch synth) for Bergamo to say "Zen 4c". 592 593 Fri Nov 5 2021 Todd Allen <todd.allen@etallen.com> 594 * cpuid.c: Added (synth) decoding for Pentium Gold G5420 (0,6),(9,14),10, 595 based on a sample from Andrey Rahmatullin. Previously, I knew only of 596 variants with stepping 11. 597 * cpuid.c: Renamed Golden Cove & derivatives phys (physical properties) 598 to use new Intel 7 branding. Likewise for the preliminary Redwood 599 Cove & Granite Rapids and Intel 4. 600 601 Thu Nov 4 2021 Todd Allen <todd.allen@etallen.com> 602 * cpuid.c: Added (synth) decoding for AMD Storm Peak (preliminary). 603 * cpuid.c: Added (synth) decoding for Intel (0,6),(10,8) (preliminary). 604 * cpuid.c: Added (synth) decoding for Intel (0,6),(10,10) (preliminary). 605 * cpuid.c: Added (synth) decoding for Intel (0,6),(10,12) (preliminary). 606 * cpuid.c: Added (synth) decoding for Intel (0,6),(10,13) (preliminary). 607 * cpuid.c: Added (synth) decoding for Intel (0,6),(9,15) (preliminary). 608 * cpuid.c: Added Cougar Mountain name to Intel Puma 7, from MRG 609 2018-Mar-6. 610 611 Wed Nov 3 2021 Todd Allen <todd.allen@etallen.com> 612 * cpuid.c: Added (synth) decoding for AMD Lucienne A1 stepping. 613 * cpuid.c: Added (synth) decoding for AMD Van Gogh (preliminary). 614 * cpuid.c: Added (synth) decoding for AMD Mero (preliminary). 615 * cpuid.c: Added (synth) decoding for AMD Mendocino (preliminary). 616 * cpuid.c: Added (synth) decoding for AMD Chagall (preliminary). 617 * cpuid.c: Added (synth) decoding for AMD Badami (preliminary). 618 * cpuid.c: Added (synth) decoding for AMD Rembrandt (preliminary). 619 * cpuid.c: Added (synth) decoding for AMD Genoa (preliminary). 620 * cpuid.c: Added (synth) decoding for AMD Raphael (preliminary). 621 * cpuid.c: Added (synth) decoding for AMD Phoenix (preliminary). 622 * cpuid.c: Added (synth) decoding for AMD Bergamo (preliminary). 623 624 Wed Nov 3 2021 Todd Allen <todd.allen@etallen.com> 625 * cpuid.c: Added hypervisor+3/edx (Microsoft) new fields. 626 * cpuid.c: Added hypervisor+7/eax (Microsoft) new field. 627 * cpuid.c: Added hypervisor+7/ecx (Microsoft) new field. 628 * cpuid.c: Added hypervisor+0xa/eax (Microsoft) new field. 629 630 Wed Nov 3 2021 Todd Allen <todd.allen@etallen.com> 631 * cpuid.c: Updated (synth) decoding for Alder Lake-S to include Core 632 variants. 633 * cpuid.c: Added (synth) and (uarch) decoding for VIA/Centaur CHA (CNS). 634 635 Tue Nov 2 2021 Todd Allen <todd.allen@etallen.com> 636 * cpuid.c: Added 7/1/eax AMX tile support, from Linux kernel. 637 638 Sun Oct 31 2021 Todd Allen <todd.allen@etallen.com> 639 * Made new release. 640 641 Sun Oct 31 2021 Todd Allen <todd.allen@etallen.com> 642 * cpuid.c: Support hypervisors which can move their range of leaves 643 to other base addresses, to support hypervisors under other 644 hypervisors: IS_HYPERVISOR_LEAF(), print_hypervisor_*(). 645 * cpuid.c: Separated out get_hypervisor(). This ended up being 646 unnecessary, but I prefer it anyway. 647 * cpuid.c: Added print_esc_substring() to print hypervisor_id values 648 that contain non-graphic characters. 649 650 Fri Oct 29 2021 Todd Allen <todd.allen@etallen.com> 651 * cpuid.c: Improved (synth) decoding for Intel Xeon (3rd Gen) D2/M1 652 steppings. 653 654 Wed Oct 27 2021 Todd Allen <todd.allen@etallen.com> 655 * cpuid.c: Added 0x40000001/eax support for ACRN hypervisor. Untested. 656 * cpuid.c: Added better decoding of 0x12/1 SECS.ATTRIBUTES fields. 657 658 Tue Oct 26 2021 Todd Allen <todd.allen@etallen.com> 659 * cpuid.c: Added 5,3 model for Cyrix M1 6x86, based on Cyrix 6x86 660 Processor, Instruction Set document (M1-6). 661 * cpuid.c: Corrected wrong register passed to 662 print_40000009_edx_microsoft(). 663 664 Mon Oct 25 2021 Todd Allen <todd.allen@etallen.com> 665 * cpuid.c: Adapted patch from Brian Inglis for easier Cygwin cygport, 666 but made an effort to reduce duplicate header file references, and 667 use of <sys/cpuset.h> for the right reasons (i.e. a more general 668 change). 669 * cpuid.c: For 12/n/ebx & 12/n/edx (n >= 2), mask the high 12 bits. 670 * cpuid.c: Added 0x40000001/eax(KVM) map gpa range hypercall & 671 MSR_KVM_MIGRATION_CONTROL. 672 673 Sun Oct 24 2021 Todd Allen <todd.allen@etallen.com> 674 * cpuid.c: Add (synth) decoding for additional Alder Lake steppings. 675 * cpuid.c: Generalize (synth) decoding for Elkhart Lake B0. 676 * cpuid.c: Added 0x8000000a/edx guest SVME addr check. 677 * cpuid.c: Added 7/0/ecx bus lock detection. 678 * cpuid.c: Added 7/0/edx RTM transaction always aborts, TSX_FORCE_ABORT. 679 * cpuid.c: Added 0x40000001/eax (KVM) extended destination ID. 680 * cpuid.c: Added (synth) decoding for Vortex86EX2 & Vortex86DX2. Info 681 on these is almost nonexistent, so it's possible that these rules are 682 too specific or too vague. 683 * cpuid.c: Improved (synth) decoding for Tiger Lake: Pentium & Celeron. 684 * cpuid.c: Improved (synth) decoding for Elkhart Lake: Pentium & Celeron. 685 * cpuid.c: Improved (synth) decoding for Jasper Lake: Pentium & Celeron. 686 * cpuid.c: Improved (synth) decoding for (0,6)(10,5) Comet Lake: 687 Pentium, Celeron & Xeon. 688 * cpuid.c: Improved (synth) decoding for (0,6),(6,10) Ice Lake: 689 Xeon Scalable. 690 * cpuid.c: Improved (synth) decoding for AMD (8,15),(1,1) Raven Ridge: 691 Athlon Pro 200. 692 * cpuid.c: Improved (synth) decoding for AMD (8,15),(1,8) Picasso: 693 Athlon Pro 300. 694 * cpuid.c: Added (synth) decoding for AMD 4700S Desktop Kit. 695 * cpuid.c: Added (synth) decoding for AMD (8,15),(4,7) Lucienne. 696 697 Sun Oct 24 2021 Todd Allen <todd.allen@etallen.com> 698 * cpuid.c: Added 0x80000008/ecx tscSize. 699 * cpuid.c: Added 0x8000001c/{eax,edx} continuous mode sampling. 700 * cpuid.c: Added 0x8000001c/{eax,edx] tsc in event record. 701 * cpuid.c: Added (synth) decoding for AMD Milan B1. 702 * cpuid.c: Added (synth) decoding for AMD Vermeer. 703 * cpuid.c: Added (synth) decoding for AMD Cezanne. 704 705 Sat Oct 23 2021 Todd Allen <todd.allen@etallen.com> 706 * cpuid.c: Renamed 7/0/ecx 5-level paging to include LA57 & 57-bit addrs. 707 * cpuid.c: Improved 0xa/ebx presentation, and automatically mask bits 708 marked as invalid by 0xa/eax vector length. 709 * cpuid.c: Added 0x12/n/ecx new section property encoding. 710 * cpuid.c: Renamed Rocket Lake uarch to Cypress Cove. 711 * cpuid.c: Improved (synth) decoding for Tiger Lake. 712 * cpuid.c: Improved (synth) decoding for Rocket Lake. 713 714 Fri Jul 16 2021 Ani Sinha <ani@anisinha.ca> 715 * cpuid.c: Add support for 0x40000003/eax reenlightenment control MSR 716 & 0x40000003/eax TscInvariant control MSR [on Microsoft Hyper-V]. 717 718 Fri Jul 16 2021 Smita Koralahalli Channabasappa <Smita.KoralahalliChannabasappa@amd.com> 719 * cpuid.c: restoring the deleted "AMD (unknown model)" entry. 720 721 Mon Jul 12 2021 Smita Koralahalli Channabasappa <Smita.KoralahalliChannabasappa@amd.com> 722 * cpuid.c: updates the existing leaf and subleaf in the CPUID with 723 features related to INVLPGB, CPPC, PSFD, SEV [affects 0x80000008/edx, 724 0x80000008/edx, and 0x8000001f/eax]. 725 * cpuid.c: defines new leaf 80000021/eax. 726 * cpuid.c: replaces the naming "Unknown Model" -> "AMD EPYC Milan" for 727 Family 19h and Model 01h [affects (synth) decoding]. 728 729 Tue Feb 2 2021 Jonathan Teh <jonteh@ntlworld.com> 730 * From http://datasheets.chipdb.org/Cyrix/112ap.pdf (page 7, table 1): 731 * cpuid.c: Cyrix family 4 model 4 should be MediaGX or GXi 732 * cpuid.c: GXm is family 5, model 4 733 * cpuid.c: Cyrix MediaGX is derived from the 5x86 and unrelated to the 734 WinChip C6. Based on Wikipedia, the MediaGXm was renamed the Geode GXm 735 after it was sold to National Semi but the CPUs appear to have 736 continued to be sold under the Cyrix vendor up to and including the 737 Geode GX1. Hence, I've simply duplicated the names from NSC model 4 738 into Cyrix. 739 * cpuid.c: Model 9 for the WinChip 3 is moved to the Centaur section 740 [decode_synth_via()], from the datasheet page 3-11: 741 http://datasheets.chipdb.org/IDT/x86/WinChip3/winchip_3_datasheet.pdf 742 * cpuid.c: The Cyrix CPU detection guide [112ap] also offers some 743 possible codenames from page 20, table 17 Cx486SLC/DLC/SRx/DRx (M0.5) 744 up to table 26 for the GXm. 745 746 Mon Jan 4 2021 Todd Allen <todd.allen@etallen.com> 747 * cpuid.c: Corrected decode_amd_model()'s (0,15),(4,0) decodings for bti 748 values 0x29, 0x2a, and 0x2b. 749 * cpuid.c: Corrected wrong register passed to print_40000001_edx_kvm(). 750 751 Mon Nov 2 2020 Brian Inglis <Brian.Inglis@SystematicSw.ab.ca> 752 * Makefile: Set BUILDROOT=$(DESTDIR) for easier Cygwin cygport support. 753 754 Mon Oct 12 2020 Todd Allen <todd.allen@etallen.com> 755 * cpuid.c: Added (synth) decoding for (6,15),(3,0) AMD R-Series Bald 756 Eagle based on instlatx64 sample. 757 * cpuid.c: Added rudimentary synth & uarch decoding for Montage Jintide 758 Gen1, a CPU based on Intel Skylake (0,6),(5,5), and detectable by brand 759 string. 760 * cpuid.c: Fixed append_uarch() to pass stash, which improves uarch 761 [suffix] for Montage, Zhaoxin, and ZhangJiang CPUs. 762 763 Tue Oct 6 2020 Todd Allen <todd.allen@etallen.com> 764 * Made new release. 765 766 Tue Oct 6 2020 Todd Allen <todd.allen@etallen.com> 767 * cpuid.c: Added 6/eax enhanced hardware feedback interface. 768 * cpuid.c: Added 6/ecx number of enh hardware feedback classes. 769 * cpuid.c: Added 7/0/ecx KL: key locker. 770 * cpuid.c: Added 7/0/edx UINTR: user interrupts. 771 * cpuid.c: Added 7/0/edx AVX512_FP16: fp16 support. 772 * cpuid.c: Added 7/1/eax AVX-VNNI: AVX VNNI neural network instrs. 773 * cpuid.c: Added 7/1/eax zero-length MOVSB. 774 * cpuid.c: Added 7/1/eax fast short STOSB. 775 * cpuid.c: Added 7/1/eax fast short CMPSB, SCASB. 776 * cpuid.c: Added 7/1/eax HRESET: history reset support. 777 * cpuid.c: Added 0xa/ecx fixed counter support enumeration. 778 * cpuid.c: Added 0xd/0/eax IA32_XSS UINTR state. 779 * cpuid.c: Added 0xd/n UINTR feature. 780 * cpuid.c: Added 0x19 key locker features. 781 * cpuid.c: Added 0x20 HRESET features. 782 783 Mon Oct 5 2020 Todd Allen <todd.allen@etallen.com> 784 * cpuid.c: Added (7,5),(2,6) AMD Cato (synth) decoding based on 785 instlatx64 example (possibly an engr sample). 786 787 Sun Oct 4 2020 Todd Allen <todd.allen@etallen.com> 788 * cpuid.c: Corrected 6/edx size field to use minus-one notation. 789 * cpuid.c: Added 7/0/edx AMX flags. 790 * cpuid.c: Added 0xd XTILECFG & XTILEDATA features. 791 * cpuid.c: Added 0xd/1/eax XFD: extended feature disable supported flag. 792 * cpuid.c: Added 0xd/n/ecx XFD: faulting supported flag. 793 * cpuid.c: Added 0x18/0/edx: load-only TLB & store-only TLB encodings. 794 * cpuid.c: Added 0x1d leaf (Tile info) decoding. 795 * cpuid.c: Added 0x1e leaf (TMUL) decoding. 796 * cpuid.c: Added 0x1c leaf (architectural LBR) decoding. 797 * cpuid.c: Added 0xd LBR features. 798 799 Sun Oct 4 2020 Todd Allen <todd.allen@etallen.com> 800 * cpuid.c: Added (synth) steppings for Comet Lake (0,6),(10,6) CPUs. 801 For the first time in a long time, Intel actually provided this in 802 the revision guide (615213)! 803 * cpuid.c: Corrected (synth) decoding for AMD (8,15),(2,0) Dali CPUs. 804 * cpuid.c: Added (synth) decoding for AMD Dali A1 stepping. 805 * cpuid.c: Added (synth) decoding for AMD Picasso A1 stepping. 806 * cpuid.c: Added (synth) decoding for AMD Renoir A1 stepping. 807 808 Sat Oct 3 2020 Todd Allen <todd.allen@etallen.com> 809 * cpuid.c: Added 7/0/ecx PKS flag. 810 * cpuid.c: Added 7/0/edx SRBDS flag, from Linux kernel. 811 * cpuid.c: Added 7/0/edx LBR flag. 812 * cpuid.c: Added 0xd/0/eax IA322_XSS HWP state flag. 813 * cpuid.c: Added synth decoding for Rocket Lake. 814 * cpuid.c: Added synth decoding for Elkhart Lake B0. 815 * cpuid.c: Added synth decoding for Alder Lake [Golden Cove]. 816 * cpuid.c: Clarified synth decoding for (0,6),(8,10) Lakefield. 817 * cpuid.c: Added KVM interrupt-based page-ready APF event flag. 818 819 Sat Aug 8 2020 Todd Allen <todd.allen@etallen.com> 820 * cpuid.c: Corrected 0x20000001/edx header. 821 * cpuid.c: Detect bogus 0x20000000 leaf values and cap the maximum 822 valid register for the 0x2xxxxxxx range to avoid absurdly long dumps 823 on old CPUs. 824 825 Mon Aug 3 2020 Todd Allen <todd.allen@etallen.com> 826 * cpuid.c: Added bzero before cpuid instruction, in case the cpuid 827 instruction quietly fails. This mostly is paranoia, but I don't see 828 how this ever could cause harm. 829 830 Mon Jun 8 2020 Todd Allen <todd.allen@etallen.com> 831 * cpuid.c: Added Tiger Lake-U B0 stepping, from coreboot. 832 * cpuid.c: Added AMD (8,15),(2,0) Picasso model synth & uarch decoding. 833 834 Sun May 24 2020 Todd Allen <todd.allen@etallen.com> 835 * cpuid.c: Added Zhaoxin KX-6000 decoding that still claims the vendor 836 CentaurHauls. Later Zhaoxin CPUs were supposed to use their own 837 vendor, but instlat64x showed an example that still used the old one. 838 839 Sat May 16 2020 Todd Allen <todd.allen@etallen.com> 840 * cpuid.c: Added better (synth) decoding for Intel Comet Lake-H/S 841 Core i*-10000 CPUs, based on instlatx64 example and listings in 842 ark.intel.com. 843 844 Tue Apr 28 2020 Todd Allen <todd.allen@etallen.com> 845 * cpuid.c: Added 0x8000000a/edx INVLPGB/TLBSYNC hypervisor intercept 846 enable flag. 847 848 Mon Apr 27 2020 Todd Allen <todd.allen@etallen.com> 849 * Made new release. 850 851 Wed Apr 22 2020 Todd Allen <todd.allen@etallen.com> 852 * cpuid.c: Added synth decoding for AMD Steppe Eagle/Crowned Eagle 853 (Puma 2014 G-Series), based on instlatx64 sample. 854 855 Thu Apr 16 2020 Todd Allen <todd.allen@etallen.com> 856 * cpuid.c: Added 7/0/edx SERIALIZE & TSXLDTRK bit descriptions. 857 * cpuid.c: Added 0xf/1/eax Counter width & overflow flag. 858 * cpuid.c: Added 0x10/3/ecx per-thread MBA controls flag. 859 * cpuid.c: Added 0x8000001f fields. 860 * cpuid.man: Added AMD 24594 & 40332 docs. 861 862 Tue Mar 3 2020 Todd Allen <todd.allen@etallen.com> 863 * cpuid.c: Corrected field lengths in 14/0 and 14/1 subleafs so that 864 columns line up. 865 866 Thu Feb 27 2020 Todd Allen <todd.allen@etallen.com> 867 * cpuid.c: Added CC150 (Coffee Lake R0) synth decoding, based on 868 instlatx64 example. 869 870 Wed Feb 26 2020 Todd Allen <todd.allen@etallen.com> 871 * cpuid.c: Added Jasper Lake A0 stepping (from Coreboot*). 872 * cpuid.c: Updated 1/ebx "cpu count" to modern terminology: "maximum 873 addressible IDs for CPUs in pkg" to avoid user confusion. It was a 874 reliable count of the number of CPUs for only a split second some time 875 around 2002. Maybe. 876 * cpuid.c: Updated 4/eax CPU & core count terminology in the same way. 877 878 Tue Feb 11 2020 Todd Allen <todd.allen@etallen.com> 879 * Made new release. 880 881 Mon Feb 10 2020 Todd Allen <todd.allen@etallen.com> 882 * cpuid.c: Clarified Intel NNP-I (Spring Hill). 883 * cpuid.c: In decode_vendor(), report "Zhaoxin" even with VENDOR_VIA, 884 if the brand string indicates so. 885 * cpuid.c: In 0xc0000004/ebx, make current voltage use the shift-4 + 700 886 encoding used for other VIA voltages. 887 888 Fri Feb 7 2020 Todd Allen <todd.allen@etallen.com> 889 * cpuid.man: Use both Intel doc numbers for 329671/600827. 890 * cpuid.man: Added missing 329901/600834 Intel doc. 891 892 Thu Feb 6 2020 Todd Allen <todd.allen@etallen.com> 893 * cpuid.c: Added VIA 0xc0000004 leaf decoding. 894 * cpuid.c: Added X2_IMAGES special flag to pretty-print values in the 895 2X encoding. 896 * cpuid.c: Added MINUS1_IMAGES special flag to pretty-print values with 897 the "- 1" encoding. (I finally got turned around about this being 898 better than the older "raw" values.) 899 900 Wed Feb 5 2020 Todd Allen <todd.allen@etallen.com> 901 * cpuid.c: Add VIA C7-D and Eden brands to (0,6),(0,10) (synth). 902 * cpuid.c: Differentiate VIA (0,6),(0,13) (synth) based on brand strings. 903 * cpuid.c: Overhaul of VIA 0xc0000002 leaf decoding. 904 * cpuid.c: Updated VIA Nano steppings (synth). 905 * cpuid.c: Removed extraneous WinChip & core words from C3 and later 906 VIA CPUs (synth). 907 908 Wed Feb 5 2020 Todd Allen <todd.allen@etallen.com> 909 * cpuid.c: Changed mp_synth fields to use '=' separator instead of ':', 910 like every other value. 911 * cpuid.c: Changed processor serial number to use '=' separator instead 912 of ':', like every other value. 913 914 Tue Feb 4 2020 Todd Allen <todd.allen@etallen.com> 915 * cpuid.man: Added 336907 doc with 7/0/ecx/TME bit description. 916 * cpuid.c: Removed LX* comment from 7/0/ecx/TME bit description. It's 917 documented after all. 918 919 Tue Feb 4 2020 Todd Allen <todd.allen@etallen.com> 920 * cpuid.c: Clarified (0,6),(10,6) Comet Lake-U (synth). 921 922 Mon Feb 3 2020 Todd Allen <todd.allen@etallen.com> 923 * Made new release. 924 925 Mon Feb 3 2020 Todd Allen <todd.allen@etallen.com> 926 * cpuid.c: Removed comments about (0,6),(8,14),10 contradiction. 927 Coreboot* removed the incorrect code claiming it was Coffee Lake D0. 928 The actual code already reflected this resolution. 929 * cpuid.c: Removed now-redundant lines from decode_uarch_intel() for 930 the individual (0,6),(8,14) steppings. They all say Kaby Lake now, 931 so they aren't necessary. 932 * cpuid.c: Added (0,6),(4,14),8 Kaby Lake G0 and (0,6),(5,14),8 933 Kaby Lake-H A0 steppings to both (synth) and (uarch synth) that I found 934 in Coreboot*. I realized I was worrying too much about them. They are 935 at least wholly distinct steppings, so they don't constitute the 936 intra-stepping blurring that I saw with {Kaby,Amber,Whiskey,Comet} 937 Lake. They are more akin to the already-existing Cascade Lake & 938 Cooper Lake steppings. Perhaps those two new entries were just early 939 engineering samples for Kaby Lake. 940 * cpuid.c: Added (0,6),(9,14),13 stepping to decode_uarch_intel. The 941 fallback without a stepping is weak, and it should be avoided for 942 any actual known stepping. (Added a comment too.) 943 * Makefile: Changed my own Todd's Development rules to build on very old 944 systems, so that the executables will run at all on very old systems. 945 * Makefile: Changed -Wextra to -W. That isn't recommended on modern 946 gcc versions, but still works. And it is necessary on really old 947 gcc versions, because -Wextra produces a hard error. 948 949 Sun Feb 2 2020 Todd Allen <todd.allen@etallen.com> 950 * Made new release. 951 952 Sun Feb 2 2020 Todd Allen <todd.allen@etallen.com> 953 * Makefile, cpuid.proto.spec: Added FAMILY.NOTES to the list of files to 954 be included in tarball & rpm doc directory. That file still is messy, 955 but I reference it a lot, so maybe it will be useful to others too. 956 957 Sun Feb 2 2020 Todd Allen <todd.allen@etallen.com> 958 * cpuid.c: Added old (synth) models from sandpile.org: AMD Elan SC400, 959 NSC Geode LX. 960 * cpuid.c: Added some old (synth) and (uarch synth) die process numbers 961 from sandpile.org. 962 * cpuid.c: Added stepping values from sandpile.org. 963 * cpuid.c: sandpile.org calls (0,6),(4,6) "Crystalwell". Arguably, that 964 is just the name of the L4 cache. But even Intel's ARK calls these 965 CPUs "Crystal Well". So I'm changing the name to "Crystal Well". The 966 uarch still is Haswell, so that should clarify any confusion. 967 * cpuid.c: sandpile.org calls (0,6),(4,7) "Brystalwell". The situation 968 is similar, but Intel does not use that name at all. I'm not renaming 969 these cores. 970 971 Sun Feb 2 2020 Todd Allen <todd.allen@etallen.com> 972 * cpuid.c: Added leaf walking of the 0x20000000 (Intel Phi) range and 973 decoding of a single bit in 0x20000001, based on information in 974 sandpile.org. I found only a vague hint about this in the Intel Xeon 975 Phi Coprocessor System Developers Guide, but no details. 976 * cpuid.c: For the (0,11) family of Phi processors, placing them within 977 a K1OM family. The (0,6) Phi cores are just Airmont-derived, so left 978 them alone. 979 980 Sat Feb 1 2020 Todd Allen <todd.allen@etallen.com> 981 * cpuid.c: Reverted Cedar Trail back to Cedarview. (Atom uArch name vs. 982 Core name vs. Platform name vs. SoC name is very confusing.) 983 984 Sat Feb 1 2020 Todd Allen <todd.allen@etallen.com> 985 * cpuid.c: Added Broadwell (0,6),(3,13) steppings based on Coreboot*. 986 * cpuid.c: Added Haswell (0,6),(3,12) steppings based on Coreboot*. 987 * cpuid.c: Added Haswell-ULT (0,6),(4,5),0 stepping based on Coreboot*. 988 * cpuid.c: Added some Skylake (0,6),(4,14) steppings based on Coreboot*. 989 * cpuid.c: Added some Skylake (0,6),(5,14) steppings based on Coreboot*. 990 * cpuid.c: Added Kaby Lake-H (0,6),(9,14),9 stepping based on Coreboot*. 991 * cpuid.c: Added Cannon Lake (0,6),(6,6) steppings based on Coreboot*. 992 * cpuid.c: Added Apollo Lake (0,6),(5,12) A0 stepping based on Coreboot*. 993 * cpuid.c: Added Gemini Lake (0,6),(7,10) A0 stepping, and corrected 994 R0 stepping, based on Coreboot*. 995 * cpuid.c: Added Ice Lake-U/Y (0,6),(7,14) A0 stepping based on 996 Coreboot*, and disregarding inconsistent info from spec update. 997 * cpuid.c: Added Tiger Lake (0,6),(8,12) A0 stepping based on Coreboot*. 998 * cpuid.c: Added Elkhart Lake (0,6),(9,6) A0 stepping based on Coreboot*. 999 * cpuid.c: Added Comet Lake (0,6),(10,6) steppings based on Coreboot*. 1000 * cpuid.c: Added Comet Lake-H/S (0,6),(10,5) steppings based on 1001 Coreboot*. 1002 1003 Sat Feb 1 2020 Todd Allen <todd.allen@etallen.com> 1004 * cpuid.c: Added (uarch synth) decoding for (6,15),(0,0) Bulldozer, 1005 based on engineering sample. 1006 * cpuid.c: Added (uarch synth) & (synth) (6,15),(6,0) Excavator Carrizo 1007 and Toronto, based on instlatx64 samples. 1008 * cpuid.c: Added (uarch synth) decoding for (8,15),(0,0) Zen, based on 1009 engineering sample. 1010 * cpuid.c: Added Zhaoxin (0,7),(1,15) based on example. 1011 * cpuid.c: Differentiate Zhaoxin ZhangJiang from VIA Isaiah [C7] in 1012 (synth) and (uarch synth). Sadly, this implies a need to use brand 1013 information for (uarch synth). 1014 * cpuid.c: Addedd (synth) for VIA version of Zhaoxin ZhangJaing at 1015 (0,7),(0,11). 1016 * cpuid.c: Added Westmere-EP A0 & B0 stepping (synth) based on instlatx64 1017 sample & wikipedia article. 1018 * cpuid.c: Fixed bogus stepping in Centerton fallback (synth). 1019 * cpuid.c: Added (0,6),(5,5),10 Cooper Lake (synth) & (uarch synth), 1020 based on Qemu. 1021 * cpuid.c: Added "AMD PRO A" as a 2nd string to detect AMD A-Series. 1022 * cpuid.c: Differentiate Raven Ridge from Great Horned Owl/ 1023 Banded Kestrel (synth), based on "Embedded" string in brand. 1024 * cpuid.c: Added Merlin Falcon as R-Series alternative everywhere 1025 G-Series Brown Falcon appears. 1026 * cpuid.c: Added rules for EPYC Embedded to differentiate (synth) for 1027 Snowy Owl and Naples, based on EPYC 3000 series. Untested, because I 1028 have no examples. 1029 1030 Fri Jan 31 2020 Todd Allen <todd.allen@etallen.com> 1031 * cpuid.man: Added instlatx64.atw.hu. 1032 * cpuid.man: Added -l and -s options. 1033 1034 Fri Jan 31 2020 Todd Allen <todd.allen@etallen.com> 1035 * cpuid.c: Added rudimentary (10,15) (synth) for AMD Zen 3. 1036 1037 Fri Jan 31 2020 Todd Allen <todd.allen@etallen.com> 1038 * cpuid.man: Added linux kernel note about intel-family.h. 1039 * cpuid.c: Added rudimentary Tremont (synth) & (uarch synth). 1040 * cpuid.c: Added tentative Ice Lake NNPI (synth) & (uarch synth). 1041 * cpuid.c: Added rudimentary (0,6),(10,6) Comet Lake [Coffee Lake] 1042 (synth) & (uarch synth). 1043 1044 Fri Jan 31 2020 Todd Allen <todd.allen@etallen.com> 1045 * cpuid.man: Added Intel Microcode Update Guidance document. 1046 * cpuid.c: Removed br.generic check from dc (Core) query. It was useful 1047 in the Yonah era, but has been problematic since. Instead, add a dG 1048 (Generic) query and use that where needed for the Yonah CPUs. And a 1049 few other users of dc now use dG. 1050 * cpuid.c: Added (synth) for Apollo Lake D0 (collision with B0/B1?) & E0. 1051 * cpuid.c: Generalized P4500 & U4500 (Arrandale/Clarkdale) (synth) names. 1052 * cpuid.c: Added Broadwell-DE V3 (synth) alternate stepping. 1053 * cpuid.c: Added Broadwell H 43e (synth). 1054 * cpuid.c: Added Pentium 3700U / 3800U (synth). 1055 * cpuid.c: Added Apollo Lake (Broxton) (synth). 1056 * cpuid.c: Added Atom x5-E8000 (synth). 1057 * cpuid.c: Added Pentium G6900 (Clarkdale K0) (synth). 1058 * cpuid.c: Added Core i*-900 (Clarksfield) (query dc) (synth). 1059 * cpuid.c: Added E5-4600 (Ivy Bridge) (synth) names. 1060 * cpuid.c: Prefixed E to Jasper Forest Xeon (synth) names. 1061 * cpuid.c: Added Xeon E3-1200 (Kaby Lake) (synth) specific line. 1062 * cpuid.c: Added Xeon 6500 names to Beckon (synth). 1063 * cpuid.c: Generalized Pentium 900 (Sandy Bridge) (synth) names. 1064 * cpuid.c: Added Celeron T3000 / 900 / SU2300 (Wolfdale) (synth) names. 1065 * cpuid.c: Added Pentium T4000 (Wolfdale) (synth) names. 1066 * cpuid.c: Added Celeron M ULV 700 (Penryn) (synth). 1067 * cpuid.c: Correct query to dc for Sandy Bridge-E Core (synth). 1068 * cpuid.c: Added Pentium 1405 (Sandy Bridge-E) (synth). 1069 * cpuid.c: Added Xeon D-2100 (Skylake stepping 4) (synth) names. 1070 * cpuid.c: Added Core i9-7000X (Skylake-X) (synth). 1071 * cpuid.c: Changed case of x for SoFIA (synth). 1072 * cpuid.c: Simplified Westmere-EP Xeon (synth) names. 1073 * cpuid.c: Added Atom x*-A3900 (Apollo Lake) (synth) names. 1074 * cpuid.c: Added Rangeley core name to Atom C2000 (synth) names. 1075 * cpuid.c: Clarified that all (0,6),(4,15) CPUs are Broadwell-{E,EX} 1076 in (synth) lines. 1077 * cpuid.c: Clarified that (0,6),(3,13) is Broadwell-U. 1078 * cpuid.c: For (0,6),(4,6) (synth), MRG* 2018-08-31 shows stepping 1, 1079 so that must be the only known stepping: G0. 1080 * cpuid.c: Corrected Broadwell-Y Core M (synth). 1081 * cpuid.c: Added (0,6),(9,14),11 Coffee Lake Pentium & Celeron (synth). 1082 * cpuid.c: Corrected (0,6),(9,14),11 fallback (synth). 1083 * cpuid.c: Clarified transition from i*-8000 to i*-9000 at 1084 (0,6),(9,14),12 stepping in (synth) lines. 1085 * cpuid.c: Added Puma 7 (synth). 1086 * cpuid.c: Generalized Pentium B900C (Ivy Bridge) (synth). 1087 * cpuid.c: Added Celeron G2000 (Haswell) (synth). 1088 * cpuid.c: Clarified Haswell-E (synth). 1089 * cpuid.c: Aded -4000 series to (0,6),(4,6) Core (synth) names. 1090 * cpuid.c: Added (0,6),(3,14) Ivy Bridge Celeron (synth). 1091 * cpuid.c: Corrected (0,6),(3,14) Cores as Ivy Bridge-E (synth). 1092 * cpuid.c: Differentiate i*-8700 and i*-7700 Kaby Lake (synth). 1093 * cpuid.c: Added (0,6),(8,14),9 Kaby Lake Pentium & Celeron (synth). 1094 * cpuid.c: Differentiate (0,6),(8,14),9 Kaby Lake-Y and Amber Lake-Y 1095 (synth) with test for -8000 Series in brand name, because there seems 1096 to be no other way to tell. 1097 * cpuid.c: Added XMM 7272 (SoFIA) (synth). 1098 * cpuid.c: Added Coffee Lake R0 Xeon (synth). 1099 * cpuid.c: Added Whiskey Lake W0 Pentium & Celeron (synth). 1100 * cpuid.c: Correct (8,14) (uarch synth) to just Kaby Lake once all 1101 instances of Coffee lake had been eliminated from that family. The 1102 (9,14) family continues to include both Kaby Lake & Coffee Lake. 1103 1104 Fri Jan 31 2020 Todd Allen <todd.allen@etallen.com> 1105 * cpuid.man: Added Intel 600827 spec update. 1106 * cpuid.c: Generalized Bay Trail-M/D (synth) names and expanded them. 1107 * cpuid.c: Added Bay Trail-M/D D0/D1 (synth). 1108 1109 Thu Jan 30 2020 Todd Allen <todd.allen@etallen.com> 1110 * cpuid.c: Added VIA die processes for as many uarchs/cores as I could 1111 find. 1112 1113 Wed Jan 29 2020 Todd Allen <todd.allen@etallen.com> 1114 * cpuid.c: Added comments about various Intel spec updates. 1115 * cpuid.man: Removed extra "315593" garbage line. 1116 * cpuid.c: Added (synth) for Broadwell-E R0 stepping. 1117 * cpuid.c: Added stepping number for Apollo Lake B0/B1. 1118 * cpuid.c: Differentiate (synth) between Core & Xeon (0,6),(3,15) 1119 Haswell. 1120 * cpuid.c: Differentiate (synth) between Core & Xeon (0,6),(2,12) 1121 Westmere/Gulftown. 1122 * cpuid.c: Simplified more (synth) i*-*000 combinations. 1123 * cpuid.c: Removed duplicate slash in one Haswell (synth) line. 1124 * cpuid.c: Correct Itanium Merced model/stepping confusion. 1125 * cpuid.c: Added KX-5000 & KH-20000 to Zhaoxin WuDaoKou (synth). 1126 * cpuid.c: Added die proess to Zhaoxin WuDaoKou (uarch synth). 1127 * cpuid.c: Added Zhaoxin LuJiaZiu (0,7),(3,11) model (synth) & 1128 (uarch synth). 1129 1130 Tue Jan 28 2020 Todd Allen <todd.allen@etallen.com> 1131 * cpuid.c: Differentiate (synth) between Bay Trail Pentiums, Celerons 1132 & Atoms. 1133 * cpuid.c: Differentiate (synth) between Braswell Pentiums & Celerons. 1134 * cpuid.c: Corrected (synth) steppings for Braswell. 1135 * cpuid.c: Add J3000 series to (synth) for Braswell. 1136 * cpuid.c: Remove Pentium & Celeron items from {Kaby,Coffee,Comet} Lake 1137 Core (synth). I'd already created separate items for those, but 1138 missed removing the names from the Core-specific line. 1139 1140 Mon Jan 27 2020 Todd Allen <todd.allen@etallen.com> 1141 * Made new release. 1142 1143 Mon Jan 27 2020 Todd Allen <todd.allen@etallen.com> 1144 * cpuid.c: Changed 0x8000001e/ecx to display nodes per processor in N-1 1145 notation, after receiving confirmation from AMD that this is correct. 1146 1147 Sat Jan 25 2020 Todd Allen <todd.allen@etallen.com> 1148 * cpuid.c: Fixed spelling of (size synth). I meant to always have 1149 "synth" at the end of synthesized fields, and had that one flipped 1150 around. 1151 * cpuid.c: Clarified AVX512_VNNI: neural network instructions. 1152 * cpuid.c: Clarified AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND. 1153 * cpuid.c: Clarified AVX512_BF16: bfloat16 is a data format, not an 1154 instruction. 1155 * cpuid.c: Added 7/0/edx md-clear feature, found from Xen & Qemu 1156 hypervisors. 1157 * cpuid.c: Added 0x80000008/ebx ppin feature, found from Xen hypervisor. 1158 * cpuid.c: Added 0x40000001/eax (KVM) flags. 1159 * cpuid.c: Got rid of the Transmeta 0x80860001/eax family description, 1160 which I missed when I got rid of all 1/eax families. It wasn't so 1161 egregious, but it wasn't very valuable either. The Transmeta Crusoe 1162 name already was in the (synth) leaf. 1163 * cpuid.c: Wrote a version of bits_needed() that uses __builtin_clz 1164 with gcc 3.4 and later. 1165 * cpuid.c: Fixed bug with old asm-based bits_needed() function when the 1166 input value was 0. 1167 1168 Sat Jan 25 2020 Todd Allen <todd.allen@etallen.com> 1169 * cpuid.c: Further clarified descriptions in 0x8000001f leaf, based on 1170 text in AMD64 Architecture Programmer's Manual, Vol 3, 3.28. I had 1171 missed these new fields in my earlier pass through the manual. 1172 * cpuid.c: Added comments for more undocumented fields, noting where 1173 the information came from, particularly SKC*, LX*, and sandpile.org. 1174 * cpuid.c: Changed case of new descriptions. 1175 * cpuid.c: Created Synth_Family() & Synth_Model() macros based on 1176 print_1_eax & SKC's AMD_Family() macro. 1177 * cpuid.c: Added (family synth) and (model synth) to 0x80000001/eax, 1178 (AMD and Hygon variants), just like for 1/eax. 1179 * cpuid.c: Added Castle Peak B0 stepping (synth), now that I know the 1180 stepping name. 1181 * cpuid.c: Changed 0x80000008/ebx "RDPRU instruction" field. 1182 * cpuid.c: Clarified 0x80000020 leaf descriptions based on AMD 55803 PPR. 1183 * cpuid.c: Modified print_apic_synth's bit width computations to reflect 1184 change in terminology (core => thread, CU => core) in AMD Family 17h. 1185 * cpuid.man: Updated 54945 PPR name, using newer doc from 1186 developer.amd.com. 1187 * cpuid.man: Added 55803 PPR, found by URL provided by AMD. 1188 * cpuid.man: Updated sandpile.org URL. 1189 1190 Sat Jan 25 2020 Todd Allen <todd.allen@etallen.com> 1191 * cpuid.c: Selectively applied changes from Smita Koralahalli 1192 Channabasappa's patch: "Add PQoS feature to CPUID utility and display 1193 subleaf 1 for leaf 0x80000020 in the raw CPUID data." 1194 * cpuid.c: Renamed fields which no longer are Intel-specific: 1195 RDT-CMT/PQoS cache monitoring and RDT-CAT/PQE cache allocation. 1196 1197 Fri Jan 24 2020 Todd Allen <todd.allen@etallen.com> 1198 * cpuid.c: Shortened 0x8000001f leaf descriptions to <= 40 chars. 1199 1200 Fri Jan 24 2020 Smita Koralahalli Channabasappa <Smita.KoralahalliChannabasappa@amd.com> 1201 * cpuid.c: Add AMD Secure Encryption feature bits to CPUID utility. 1202 * cpuid.c: Update CPUID utility with additional AMD specific features. 1203 * cpuid.c: Handle naming issues of cores->threads at register 1204 80000008_ecx and compute unit->core at register 8000001e_ebx for 1205 families greater than 16h. Retains previously assigned names if 1206 families are lesser than or equal to 16h. Family values are 1207 determined by adding family number and extended family 1208 number(80000001_eax[8:11] + 80000001_eax[20:27]) as described in PPR 1209 under CPUID_Fn00000001_eax. 1210 1211 Wed Jan 22 2020 Todd Allen <todd.allen@etallen.com> 1212 * Made new release. 1213 1214 Wed Jan 22 2020 Todd Allen <todd.allen@etallen.com> 1215 * cpuid.c: In print_80000001_ebx_amd, removed two checks for 1216 __M(val_1_eax) >= _XM(0) + _M(0). Yes, gcc, I know that "comparison 1217 of unsigned expression >= 0 is always true", and I also know even a 1218 half-assed optimizer will get rid of it, so I preferred clarity. But 1219 people freak out if the compiler emits any warnings, no matter what 1220 crazy -W options the've chosen. So I'm removing them. 1221 * cpuid.c: Changed a bunch of ccstring return types to cstring. The 1222 extra const in ccstring was meaningless for return types, but it 1223 caused a ton of additional -Wignored-qualifiers warnings. No grousing 1224 about those warnings; they seem legit. 1225 * Makefile: Added -Wextra, so I'll see these before people complain 1226 about them in the future. 1227 1228 Tue Jan 21 2020 Todd Allen <todd.allen@etallen.com> 1229 * cpuid.c: Changed Cannon Lake to Palm Cove when talking about uarch. 1230 * cpuid.c: Added extra (0,6),(8,14),12 (unknown type) fallback. 1231 * cpuid.c: Fixed (0,6),(8,14) Whiskey Lake typo. 1232 * cpuid.c: Added i*-9000 names to (0,6),(9,14) Coffee Lake CPUs. 1233 1234 Mon Jan 20 2020 Todd Allen <todd.allen@etallen.com> 1235 * Made new release. 1236 1237 Sun Jan 19 2020 Todd Allen <todd.allen@etallen.com> 1238 * cpuid.c: Fixed (synth) decoding of Kaby Lake vs. Coffee Lake (and 1239 their myriad "optimizations"). 1240 * cpuid.c: Correctly (synth) decoding of Comet Lake, which was wildly 1241 wrong. 1242 * cpuid.c: Treating Whiskey Lake, Amber Lake, and Comet Lake as distinct 1243 uarchs just causes absurd "Coffee Lake / Whiskey Lake / Amber Lake / 1244 Comet Lake" uarch strings. Instead, call all of them Coffee Lake, but 1245 turn off the core_is_uarch flag. This ends up treating the other 3 as 1246 core names within the Coffee Lake uarch, which seems clearer. 1247 * cpuid.c: Renamed Ice Lake to Sunny Cove when talking about uarch. 1248 * cpuid.c: Renamed Tiger Lake to Willow Cove when talking about uarch. 1249 * cpuid.c: Added (synth) differentiation between Whiskey Lake (U line) 1250 & and Amber Lake (Y line). 1251 * cpuid.c: Added (synth) differentiation between Whiskey Lake (8000 1252 Series) and Comet Lake (10000 Series). 1253 * cpuid.c: Separated (synth) for Goldmont Plus into Pentium & Celeron. 1254 * cpuid.c: Fixed Moorefield (synth) to say Z3500 instead of Z3400. 1255 * cpuid.c: Fixed (0,6),(5,5),7 to Cascade Lake-X. Core names should be 1256 as specific as possible (in contrast to uarch names). 1257 * cpuid.c: added (0,6),(2,7) Atom Z2000 Medfield (synth) based on 1258 example found on instlatx64. 1259 * cpuid.c: Renamed Cedarview (SoC name) to Cedar Trail (core name). 1260 * cpuid.c: Added (0,6),(1,15) Havendale/Auburndale (synth). 1261 * cpuid.c: Added VIA (0,6),(0,15) Esther C5J (synth). 1262 * cpuid.c: Added VIA Nano steppings to (synth). 1263 * cpuid.c: Added AMD Ryzen vs. EPYC (synth) differentiation to 1264 Castle Peak / Rome. 1265 * cpuid.c: Separated Mullins into Mullins (tablets) and Beema (desktop). 1266 * cpuid.c: Separated Kabini into Kabini (desktop) and Kyoto (servers). 1267 Also added Temash for A-Series, although they're all mixed up with 1268 Kabini. 1269 * cpuid.c: Added AMD (6,15),(3,8) Godavari (synth) decoding. 1270 * cpuid.c: Added AMD (2,15),(0,3) Griffin (synth) decodings. 1271 * cpuid.c: Removed duplicate junk code for AMD (1,15),(0,2) which 1272 prevented the 3 and 10 steppings from being used. 1273 * cpuid.c: Corrected some AMD (0,6),(0,8) Duron Applebred (synth) names. 1274 * cpuid.c: Added AMD DG02SRTBP4MFA based on example found on instlatx64. 1275 1276 Fri Jan 17 2020 Todd Allen <todd.allen@etallen.com> 1277 * cpuid.c: Merged 0xb and 0x1f leaf code, much like what Len Brown of 1278 Intel suggested a year ago. I don't know why I didn't just do that in 1279 the first place. Merged field names look more like the 0x1f names, 1280 because I thought they were clearer. 1281 * cpuid.c: Removed type descriptions from "--- level ---" sub-headers. 1282 Intel docs clarify the levels and types are not related. 1283 * cpuid.c: Got rid of the ridiculously overloaded 1/eax family 1284 descriptions. That information is nearly useless in isolation and 1285 described much better in the new (uarch synth) field. 1286 * cpuid.c: Also got rid of 0x80000001/eax family descriptions. It 1287 wasn't nearly as bad, but still better to use the (uarch synth) field. 1288 * cpuid.c: Because I removed that family information, also updated the 1289 decode_uarch* functions with information about older CPU makers' 1290 information. 1291 * cpuid.c: Added vendor name to (uarch synth). 1292 * cpuid.c: Fixed 4 and 0x8000001d leaf descriptions to say that the 1293 values are in "minus 1" notation. Steven Noonan hinted that there was 1294 something to check here, and there was. 1295 * cpuid.c: Added (synth size) field to the 4 and 0x8000001d leaves to 1296 compute the cache size, also based on a hint from Steven Noonan. 1297 * cpuid.c: Added preliminary Zhaoxin decoding based on limited 1298 information I could find. 1299 * cpuid.c: Added missing uarch names to decode_uarch_intel(). 1300 * cpuid.c: Added note about P5 Tillamook CPUs. 1301 * cpuid.c: Added some more die process values. 1302 1303 Thu Jan 16 2020 Todd Allen <todd.allen@etallen.com> 1304 * Made new release. 1305 1306 Thu Jan 16 2020 Todd Allen <todd.allen@etallen.com> 1307 * cpuid.c: Added decode_uarch*() and moved the uarch suffixes there from 1308 print_synth*(). print_synth_intel() and print_synth_amd() now call 1309 that function to get the suffixes. 1310 * cpuid.c: Added print_uarch_synth() to display just those suffixes. 1311 * cpuid.c: Added (synth) decoding for Itanium Poulson & Kittson. 1312 * cpuid.c: Correct (synth) decoding for Itanium Montecito, Millington, 1313 Montvale, Tukwila. 1314 * cpuid.c: Cleaned up AMD [Excavator] core names. 1315 * cpuid.man: Added some missing Intel spec updates. 1316 1317 Wed Jan 15 2020 Todd Allen <todd.allen@etallen.com> 1318 * cpuid.c: Added "(family synth)" and "(model synth)" to do the combined 1319 values used by the linux kernel and AMD. That is: 1320 Family = XF + F 1321 Model = (XM << 4) + M 1322 * cpuid.c: Hunt down the fallback (synth) decodings that just list tons 1323 of different possible meanings, all copied from the more specific 1324 lines above them. They almost always are wrong; if they were right, 1325 the more specific tests would've detected them. So, they're pure 1326 guesswork. Replace them with "(unknown type)", which is more honest. 1327 * cpuid.c: Simplified Intel Xeon Scalable descriptions. 1328 * cpuid.c: Eliminated reiteration of i3-XXXX, i5-XXXX, i7-XXXX CPUs, 1329 using i*-XXXX instead. 1330 * cpuid.c: Added (synth) decoding for Core i*-4000U seen in the wild. 1331 * cpuid.c: Correct missing = symbol in 0x80000001/eax transmeta leaf. 1332 * cpuid.c: Added [K6], [K7], [K8] (synth) clarifications for AMD K8 CPUs. 1333 * cpuid.c: Added (6,15),(6,5) (synth) based on sample from Alexandros 1334 Couloumbis. 1335 * cpuid.c: Added AMD "*-Series" queries for the various latters and 1336 (synth) rules to use them. Added more rules for AMD architectures 1337 that used this nomenclature. 1338 * cpuid.c: Changed dO query to sO. 1339 1340 Wed Jan 15 2020 Todd Allen <todd.allen@etallen.com> 1341 * cpuid.c: Clarified (synth) for each microarchitecture to include 1342 process-neutral microarchitecture names too: 1343 {P6} = (Pentium Pro, Klamath, Deschutes, Katmai, Coppermine, 1344 Tualatin, Mendocino, Cascades) 1345 {Netburst} = [Willamette, Northwood, Prescott, Cedar Mill] 1346 {P6 Pentium M} = (Banias), [Dothan, Yonah] 1347 {Core} = [Merom, Penryn] 1348 {Nehalem} = [Nehalem, Westmere] 1349 {Sandy Bridge} = (Sandy Bridge, Ivy Bridge) 1350 {Haswell} = (Haswell, Broadwell) 1351 {Skylake} = (Skylake, Kaby Lake, Coffee Lake, Whiskey Lake, 1352 Amber Lake, Cascade Lake, Comet Lake, Cooper Lake, 1353 Cannon Lake) 1354 {Sunny Cove} = (Ice Lake, Tiger Lake) 1355 The similarities are hazy in places. But this seems useful to help 1356 people who, for example, don't know "Cedar Mill", but do know 1357 "Netburst". Also the number of Skylake-related architecture names 1358 exploded, and not all "Lake" names belong to Skylake, so this helps to 1359 clarify. 1360 * cpuid.c: Corrected (synth) for Tolapai to 90nm process. 1361 1362 Tue Jan 14 2020 Todd Allen <todd.allen@etallen.com> 1363 * cpuid.c: Clarified Arrandale & Clarkdale as [Westmere]. 1364 * cpuid.c: Clarified Bloomfield, Gainestown & Beckton as [Nehalem]. 1365 * cpuid.c: Added [Merom] clarification to a couple CPUs that missed it. 1366 * cpuid.c: Added [Cedar Mill] clarification to a couple CPUs that missed 1367 it. 1368 * cpuid.c: Clarified Dothan, Stealey, Crofton & Tolopai as [Dothan]. 1369 * cpuid.c: Clarified Yonah, Sossaman as [Yonah]. 1370 * cpuid.c: Did not clarify Banias as [Banias] because it appears there 1371 are no non-Banias chips based on it. 1372 * cpuid.man: Added handy wiki pages about microarchitectures. 1373 1374 Mon Jan 13 2020 Todd Allen <todd.allen@etallen.com> 1375 * cpuid.c: Added 6/eax HW_FEEDBACK flag. 1376 * cpuid.c: Added 7/0/ecx ENQCMD flag. 1377 * cpuid.c: Added 7/0/edx AVX512_VP2INTERSECT flag. 1378 * cpuid.c: Added 7/1/eax AVX512_BF16 flag. 1379 * cpuid.c: Added 0xd/0/eax flags for CET_U & CET_S state. 1380 * cpuid.c: Added 0x80000008/ebx WBNOINVD flag. 1381 * cpuid.c: Added 0x80000008/ebx SSBD flags from AMD white paper. 1382 * cpuid.c: In 7/0/edx leaf, clarified PCONFIG as an instruction. 1383 * cpuid.c: Added synth detection for Cyrix MediaGX (circa 1997 SoC). 1384 * cpuid.c: Added 7/0/ecx TME flag, discovered in the linux-5.5-rc6 1385 kernel source. 1386 * cpuid.c: Added 0x80000008/ebx additional STIBP always on flag, 1387 discovered in the linux-5.5-rc6 kernel source. 1388 * cpuid.man: Added AMD SSBD white paper. 1389 * cpuid.man: Added linux kernel note and clue on what to look for. 1390 1391 Sun Jan 12 2020 Todd Allen <todd.allen@etallen.com> 1392 * cpuid.c: Added Matisse B0 stepping based on sample from Steven Noonan. 1393 * cpuid.c: Removed redundant dR lines from Pinnacle Ridge. (They could 1394 come back if I see an EPYC based on Pinnacle Ridge, but they're 1395 redundant now.) 1396 1397 Sun Jan 12 2020 Todd Allen <todd.allen@etallen.com> 1398 * Made new release. 1399 1400 Sun Jan 12 2020 Todd Allen <todd.allen@etallen.com> 1401 * Makefile, cpuid.proto.spec: Added INSTALL_STRIP to allow disabling the 1402 install -s option. This makes rpmbuild & find-debuginfo.sh happy, 1403 because they can find the cpuid debug information and create the 1404 cpuid-debuginfo rpm. 1405 * Makefile: Updated release target to move debugsource rpms too. 1406 1407 Sun Jan 12 2020 Todd Allen <todd.allen@etallen.com> 1408 * cpuid.c: Added 0x40000004 leaf for Xen hypervisor. 1409 * cpuid.c: Added 0x40000005 leaf for Xen hypervisor. 1410 * cpuid.c: Fixed errors with static ccstring arrays that were not large 1411 enough to hold NULLs for all reserved bit field values. 1412 * cpuid.c: Added AMD's CMT "compute unit" concept to print_apic_synth 1413 by adding that architectural level above the "cores" level, which 1414 relects AMD's portrayal. This level is displayed only if it is 1415 present. 1416 * cpuid.c: Added some undocumented synth decodings found on 1417 https://en.wikichip.org/wiki/amd/cpuid. Not everything there makes 1418 sense, so I didn't take everything. Marked with comments. 1419 * cpuid.c: Added architecture tags to Intel synth decodings: 1420 [Willamette], [Northwood], [Prescott], [Merom], [Penryn], [Nehalem], 1421 [Westmere]. After that, Intel dropped the hyper-specific code names 1422 in favor of suffix letters. 1423 * cpuid.c: Added architecture tags to Intel synth decodings: [Bonnell], 1424 [Saltwell], [Silvermont], [Airmont], [Goldmont], [Goldmont Plus]. 1425 Intel continues to use hyper-specific names for Atom CPUs. 1426 1427 Sat Jan 11 2020 Todd Allen <todd.allen@etallen.com> 1428 * Makefile: Added -Wimplicit-fallthrough -Wunused-parameter options. 1429 * cpuid.c: Clarified 4/edx WBINV/INVD flag. 1430 * cpuid.c: Added new 7/edx flags, especially including new features to 1431 mitigate speculative execution exploits. 1432 * cpuid.c: Cleaned up output of 0x10 subleaves. 1433 * cpuid.c: Added 0x12/0/ebx CPINFO for #CP exceptions in enclave. 1434 * cpuid.c: Properly display 0x18 sub-leaf number. 1435 * cpuid.c: Added leaf 0x1f V2 Topology logic to decode_mp_synth() and 1436 print_apic_synth(). I have no physical examples, so I only could test 1437 with artificial input files. 1438 * cpuid.c: Added 3-way and 6-way associativity to 0x80000006 and 1439 0x80000019 leaves. 1440 * cpuid.c: Fixed incorrect fallthrough in switch for "41322 3.74: 1441 table 16". 1442 * cpuid.c: Fixed incorrect fallthrough's in switch for Family 12h tables. 1443 * cpuid.c: Added UNUSED macro to make newer gcc's shut up about unused 1444 formals. (They have one complaint if the name is omitted, and another 1445 complaint if it's specified but unused. There's just no pleasing gcc.) 1446 * cpuid.c: Added break after usage() to make gcc shut up about a 1447 nonexistent fallthrough (even though it was marked with NOTREACHED). 1448 * cpuid.c: Added missing newlines to all the print_2_byte Cyrix/VIA 1449 special cases. 1450 * cpuid.c: Fixed print_f_0_edx: QoS monitoring was in 0xf/0 bit 1, not 1451 bit 0. 1452 * cpuid.c: Added print_40000001_edx_kvm and appropriate call. 1453 * cpuid.c: For 0x80000001/ebx amd, display PkgType for all family 16h 1454 or higher systems, even if no specific BrandId breakdown is known. 1455 Added encodings from AMD BKDG and PPR documents. 1456 1457 Sat Jan 11 2020 Todd Allen <todd.allen@etallen.com> 1458 * cpuid.c: Added proper synth decoding for Atom C3000 (Denverton). 1459 * cpuid.c: Clarified Goldmont into eithe Apollo Lake or Denverton. 1460 * cpuid.c: Corrected (0,6),(9,14) synth decoding to be Coffee Lake. 1461 * cpuid.c: Added (0,6),(9,14) Coffee Lake synth decoding steppings. 1462 * cpuid.c: Added (0,6),(9,14) Coffee Lake synth decoding for Xeon E-2100 1463 & E-2200. 1464 * cpuid.c: Added (0,6),(5,5),7 synth decoding for Xeon 2nd Gen Scalable. 1465 * cpuid.c: Added (0,6),(5,5),7 synth decoding for Xeon D-2100. 1466 * cpuid.c: Added synth decoding for Gemini Lake R0 stepping (same as B0). 1467 * cpuid.c: Added vague synth decoding for (0,6),(6,6) Cannon Lake. 1468 * cpuid.c: Added vague synth decoding for (0,6),(6,10) Ice Lake. 1469 * cpuid.c: Added vague synth decoding for (0,6),(6,12) Ice Lake. 1470 * cpuid.c: Added vague synth decoding for (0,6),(7,13) Ice Lake. 1471 * cpuid.c: Added additional synth decodings for AMD Ryzen, including 1472 Pinnacle Ridge. 1473 * cpuid.c: Differentiate Ryzen from EPYC using brand string and new 1474 query functions. 1475 * cpuid.man: Added new spec updates, revision guides, etc. 1476 1477 Sat Jan 11 2020 Todd Allen <todd.allen@etallen.com> 1478 * Prettification of Masanori Misono's 0x40000001/eax KVM fields. 1479 * Formatting changes & URL removal from Jeffrey Walton's SunOS patch. 1480 * Prettification of Thomas Friebel's 0x40000003 leaf fix: while loop. 1481 * Reverted print_header() to use !raw (personal preference of mine). 1482 * Format changes to & rearrangement of fanjinke's Hygon patch. 1483 * Changed Ani Sinha's 0x80000008/ebx indirect branch prediction barrier 1484 description to include IBPB acronym. 1485 1486 Fri Jan 3 2020 Thomas Friebel <friebelt@amazon.de> 1487 * Fixed bug that skipped half the subleaves in the 0x40000003 hypervisor 1488 leaf. 1489 * Fixed contradictory try logic in print_header() for leaf 0x40000003. 1490 * Fixed to use 0x40000003/ebx for high 32 bits of vtsc_offset, 1491 instead of using eax for both high & low 32 bits. 1492 1493 Fri Nov 8 2019 Ani Sinha <ani.sinha@nutanix.com> 1494 * cpuid.c: Added 0x80000001/ecx NB performance counter extensions & 1495 0x80000008/ebx indirect branch prediction barrier. 1496 1497 Mon May 13 2019 fanjinke <fanjinke@hygon.cn> 1498 * Added Hygon support. 1499 1500 Wed May 8 2019 Jeffrey Walton <noloader@gmail.com> 1501 * cpuid.c: Added support for SunOS build. 1502 1503 Sat Mar 2 2019 Masanori Misonoc <m.misono760@gmail.com> 1504 * cpuid.c: Added 0x40000001/eax KVM bit fields. 1505 1506 Fri Jun 1 2018 Tony Luck <tony.luck@intel.com> 1507 * cpuid.c: Added decoding of 0x10/3 subleaf. 1508 1509 Sat May 26 2018 Todd Allen <todd.allen@etallen.com> 1510 * cpuid.c: Fixed 7/ecx spelling error: intruction. 1511 * cpuid.c: Fixed main spelling error: unrecogized. 1512 1513 Sat May 19 2018 Todd Allen <todd.allen@etallen.com> 1514 * Made new release. 1515 1516 Sat May 19 2018 Todd Allen <todd.allen@etallen.com> 1517 * cpuid.c: Added some more fields reported by Stefan Kanthak, after 1518 tracking down some documentation that explains them: 1519 * cpuid.c: Added 7/ecx bit 7: CET_SS and 7/edx bit 20: CET_IBT fields. 1520 So far, the only documentation for these is Control-flow Enforcement 1521 Technology Preview (334525), section 8.2 Feature Enumeration. 1522 * cpuid.c: Added 7/ecx bit 16: 5-level paging. So far, the only 1523 documentation for this is 5-Level Paging and 5-Level EPT White Paper 1524 (335252). 1525 * cpuid.c: Improved 14/0/ecx descriptions. 1526 * cpuid.c: Added hypervisor leaf descriptions from Microsoft's 1527 Hypervisor Top Level Functional Specification (Released Version 5.0b). 1528 * cpuid.man: Added the above mentioned docs. 1529 1530 Thu May 17 2018 Todd Allen <todd.allen@etallen.com> 1531 * cpuid.c: Added CPUID features documented in PPR for AMD Family 17h 1532 Model 01h B1 (54945 Rev 1.14): 1533 * cpuid.c: Added PCOMMIT to 7/ebx: PCOMMIT instruction (a deprecated 1534 instruction). 1535 * cpuid.c: Added bits to 80000001/ecx (amd). 1536 * cpuid.c: Added 80000007/ebx. 1537 * cpuid.c: Added 80000007/ecx. 1538 * cpuid.c: Added bits to 80000007/edx. 1539 * cpuid.c: Added 80000008/ebx. 1540 * cpuid.c: Added bits to 8000000a/edx. 1541 * cpuid.c: Added bits to 8000001a/eax. 1542 * cpuid.c: Added bits to 8000001b/eax. 1543 * cpuid.c: Added tentative 8000001f descriptions. Information obtained 1544 from Linux kernel 4.17-rc5 arch/x86/kernel/cpu/scattered.c (as patched 1545 by Tom Lendacky of AMD on 18-Apr-2017 via LKML), and from Secure 1546 Encrypted Virtualization API Version 0.16 Technical Preview 1547 (55766 Rev 3.06). 1548 * cpuid.man: Added 54945 & 55766 docs. 1549 1550 Thu Apr 19 2018 Todd Allen <todd.allen@etallen.com> 1551 * Made new release. 1552 1553 Wed Apr 19 2018 Todd Allen <todd.allen@etallen.com> 1554 * cpuid.c: Fixed various bugs reported by Stefan Kanthak: 1555 * cpuid.c: Fixed bug in print_2_meaning: 0x49 normal & special cases. 1556 * cpuid.c: Fixed bug in print_2_meaning: 0x63 additional 2M/4M, 4-way, 1557 32 entries item. 1558 * cpuid.c: Collapsed print_2_meaning into print_2_byte so that the 1559 prefix and CONT are known in one place. 1560 * cpuid.c: Fixed bug in print_2_byte: 0x7d is not sectored. 1561 * cpuid.c: Fixed bug in print_2_byte: 0xc2 is 4K, not 4M. 1562 * cpuid.c: Changed 6/ecx bit 0 to "hardware coordination feedback". 1563 * cpuid.c; Changed 7/ebx bit 3 to "BMI1 instructions". 1564 * cpuid.c: Change 7/ebx bit 12 to RDT-M. 1565 * cpuid.c: Change 7/ebx bit 15 to RDT-A. 1566 * cpuid.c: Corrected "0x40000003/ecx" label. 1567 * cpuid.c; print_40000003_edx_microsoft: corrected "idle" spelling. 1568 1569 Wed Apr 19 2018 Todd Allen <todd.allen@etallen.com> 1570 * cpuid.c: Added mnemonic letters for some 1/ecx, 1/edx, and 7/ebx leaf 1571 fields. 1572 * cpuid.c: Fixed bug with 4/ecx: field name should be "number of sets". 1573 * cpuid.c: Fixed bug with 4/ecx leaf: pass ECX to it! 1574 * cpuid.c; Fixed bug with 0x10/ecx: pass ECX to it! 1575 * cpuid.c: Fixed bug with 0x10/edx: pass EDX to it! 1576 1577 Sun Apr 8 2018 Todd Allen <todd.allen@etallen.com> 1578 * cpuid.c: Added 2 leaf 0xfe encoding: TLB data in leaf 0x18. 1579 * cpuid.c: Added new Intel 6/eax bit fields. 1580 * cpuid.c: Added new Intel a/edx bit field: anythread deprecation. 1581 * cpuid.c: Added new Intel d/0/eax bit field: IA32_XSS HDC state. 1582 * cpuid.c: Added new Intel 10/0/ebx bit field: memory bandwidth alloc. 1583 * cpuid.c: Added new Intel 12/0/eax bit fields 1584 * cpuid.c: Added new Intel 18 leaf: deterministic address translation. 1585 * cpuid.c: Added new Intel 7/ecx bit fields from Intel Architecture 1586 Instruction Set Extensions and Future Features Programming Reference. 1587 * cpuid.c: Added new Intel 1b leaf from Intel Architecture 1588 Instruction Set Extensions and Future Features Programming Reference. 1589 * cpuid.c: Added synth decoding for Avoton C0 stepping (same as B0). 1590 * cpuid.c: Corrected synth decoding for Bay Trail-M C0 steppings. 1591 * cpuid.c: Added synth decoding for Bay Trail-I (E3800). 1592 * cpuid.c: Added synth decoding for Xeon D-1500N (Broadwell-DE A1). 1593 * cpuid.c: Added synth decoding for Xeon E7-4800/8800 (Broadwell-EX B0). 1594 * cpuid.c: Correct synth decoding for Bay Trail A0. 1595 * cpuid.c: Added synth decoding for Bay Trail D0. 1596 * cpuid.c: Added synth decoding for Core X-Series (Skylake-X). 1597 * cpuid.c: Added synth decoding for Xeon Scalable (Bronze, Silver, Gold, 1598 Platinium) (Skylake). 1599 * cpuid.c: Added synth decoding for Pentium Silver (Gemini Lake). 1600 * cpuid.c: Added synth decoding for AMD Zen. 1601 * cpuid.man: Added new spec updates & PPR. 1602 1603 Fri Nov 3 2017 Todd Allen <todd.allen@etallen.com> 1604 * cpuid.c, cpuid.man: Attribute whitepaper to Shih Kuo. 1605 1606 Wed Jun 22 2017 Lars Wendler <polynomial-c@gentoo.org> 1607 * cpuid.c: recent glibc versions no longer automagically include 1608 sysmacros.h headers. This needs to be done by the source files itself 1609 now. 1610 1611 Fri Mar 3 2017 Todd Allen <todd.allen@etallen.com> 1612 * cpuid.c: Added missing SDBG bit to 1/ecx leaf. 1613 1614 Sun Jan 22 2017 Todd Allen <todd.allen@etallen.com> 1615 * Made new release. 1616 * cpuid.c: Use __cpuid_count macro for "cpuid" instruction if possible. 1617 This macro is present in gcc 4.3.0 and later, and works around the fact 1618 that the cpuid instruction writes on the PIC register. This is only 1619 important when compiling PIC/PIE. 1620 * cpuid.c: Added synth decoding for Intel Knights Landing B0. The Intel 1621 docs still don't specify the stepping numbers, but all examples seen 1622 so far have stepping number 1, and so far B0 is the only stepping. 1623 * cpuid.c: Added new synth decodings for Intel Kaby Lake. 1624 * cpuid.c: Fixed synth decodings for AMD Steamroller. 1625 * cpuid.c: Fixed synth decodings for AMD Jaguar. 1626 * cpuid.c: Added synth decodings for AMD Puma. 1627 * cpuid.c: Added synth decodings for AMD Excavator. 1628 * cpuid.c: For (6,15),(0,2) Piledriver processors, detect FX series 1629 and report it as Vishera instead of Abu Dhabi/Seoul/Delhi. 1630 * cpuid.c: Added general microarchitecure names for AMD (e.g. 1631 Piledriver) in addition to specific core names (e.g. Trinity) for 1632 later generation processors. If I have trouble remembering these, 1633 it seems likely other people do too. 1634 * cpuid.c: Added synth decoding for Quark X1000. 1635 * cpuid.c: Added Intel Atom Z2760 (Clover Trail). 1636 * cpuid.c: Added extra synth decodings for some Sandy Bridge processors. 1637 * cpuid.c: Added extra synth decodings for some Ivy Bridge processors. 1638 * cpuid.man: Added new & missing spec updates & revision guides. 1639 * FUTURE: Cleaned this up somewhat. 1640 1641 Mon Dec 5 2016 Todd Allen <todd.allen@etallen.com> 1642 * cpuid.c: Removed stale len variable from do_file(). 1643 1644 Thu Dec 1 2016 Todd Allen <todd.allen@etallen.com> 1645 * Made new release. 1646 1647 Wed Nov 30 2016 Todd Allen <todd.allen@etallen.com> 1648 * cpuid.c: Fixed bugs in the subleaf walks for 0x8000001d (AMD cache 1649 information) and 0x40000003 (Xen hypervisor information) because the 1650 code for them was under wholly the wrong loops. Thanks to Brice 1651 Goglin for detecting this and working out the cause of the bug. 1652 1653 Wed Nov 16 2016 Todd Allen <todd.allen@etallen.com> 1654 * cpuid.c: Updated comments referencing 325462 Table 35-1 to also 1655 specify Volume 3. 1656 * cpuinfo2cpuid: Added grep commands to EXAMPLES. 1657 1658 Mon Nov 14 2016 Todd Allen <todd.allen@etallen.com> 1659 * Made new release. 1660 * cpuid.man: Added 334663 & 334820 spec updates. 1661 1662 Sun Nov 13 2016 Todd Allen <todd.allen@etallen.com> 1663 * cpuid.c: Fixed bug reported by Andrew Cooper where, in do_real, for 1664 the 0xd leaf, the lower half of the valid bit set for XSS should've 1665 used 0xd/1/ecx instead of 0xd/1/eax. Sadly, this bug affects raw 1666 dumps too. 1667 * cpuid.c: Added -l/--leaf and -s/--subleaf options to cause cpuid 1668 to dump just the specified leaf and subleaf. If -s/--subleaf is not 1669 specified, it is assumed to be 0. The intended purpose for this is 1670 to display raw dumps of not-yet-supported leaves, or to workaround 1671 bugs like the above. 1672 1673 Sat Nov 12 2016 Todd Allen <todd.allen@etallen.com> 1674 * cpuid.c: In bits_needed, add a further check for !defined(__ILP32__), 1675 which should help with building a 32-bit version of cpuid on a 64-bit 1676 system. 1677 1678 Sat Nov 12 2016 Todd Allen <todd.allen@etallen.com> 1679 * cpuid.c: Made editorial changes to Piotr Luc's patches (spelling, 1680 capitalization, register order, comments, etc.). 1681 * cpuid.c: Added AVX512DQ, AVX512IFMA, AVX512BW, AVX512VL, and CLWB 1682 decoding to 7/ebx. 1683 * cpuid.c: Added AVX512VBMI to 7/ecx. 1684 * cpuid.c: Added print_f_0_edx to show L3 cache QoS monitoring support. 1685 * cpuid.c: Added total & local bandwidth monitoring to 0xf/1/edx. 1686 * cpuid.c: Added 0x15/ecx nominal core crystal clock decoding. 1687 * cpuid.c: In print_17_0_ebx, corrected reversed scheme encodings. 1688 * cpuid.c: Added synth decoding for Xeon D-1500 (Broadwell-DE) Y0 1689 stepping. 1690 * cpuid.c: Added synth decoding comment about Braswell D1 stepping, but 1691 its stepping number isn't documented. 1692 * cpuid.c: Added synth decoding for (0,6),(8,14) Kaby Lake processors. 1693 * cpuid.c: Added synth decoding for Apollo Lake processors. 1694 * cpuid.c: Added vague synth decoding for (0,6),(9,14) Kaby Lake 1695 processors. 1696 * cpuid.c: Re-sorted (0,6),(5,7) Knights Landing to correct position. 1697 * cpuid.c: Re-sorted (0,6),(5,15) Goldmont to correct position. 1698 1699 Sat Oct 27 2016 Piotr Luc <Piotr.Luc@intel.com> 1700 * cpuid.c: Add AVX512_4VNNIW & AVX512_4FMAPS flags. 1701 * cpuid.c: Add Knights Mill (KNM) CPUID. 1702 1703 Sun Aug 14 2016 Todd Allen <todd.allen@etallen.com> 1704 * Made new release. 1705 * Makefile: Added clean rules to remove tarballs & rpm's with other 1706 version numbers. 1707 1708 Sun Aug 14 2016 Todd Allen <todd.allen@etallen.com> 1709 * cpuinfo2cpuid: Added a script that takes input from a /proc/cpuinfo 1710 file and converts it into suitable input to cpuid. The information 1711 that cpuid is capable of producing based on this very limited input 1712 information is slight, but apparently there is interest in getting the 1713 synthesized (synth) leaf from this. There isn't much value in using 1714 it with an actual /proc/cpuinfo file on the local system, because just 1715 allowing cpuid to read the local cpuid info will provide better 1716 output. But it could be useful for interpreted saved /proc/cpuinfo 1717 files from another system. I slapped together the basic logic, and 1718 Jirka Hladky turned it into a proper perl script, with actual options, 1719 a help screen, and even documentation. I then made some changes to 1720 give it some more uniform indentation, whitespace, and such. And to 1721 give Jirka Hladky more credit, since his contribution to the script is 1722 larger than my own. 1723 * Makefile: Added rules to generate cpuinfo2cpuid.man from the =pod data 1724 in the script. 1725 * Makefile: Added cpuinfo2cpuid & cpuinfo2cpuid.man to the released 1726 materials. 1727 * cpuid.proto.spec: Added cpuinfo2cpuid & cpuinfo2cpuid.1.gz to released 1728 materials. 1729 1730 Sun Aug 14 2016 Todd Allen <todd.allen@etallen.com> 1731 * cpuid.c: Changed instances of Kb to KB. In print_2_meaning, changed 1732 an instance of 4k to 4K. 1733 1734 Sat Aug 13 2016 Todd Allen <todd.allen@etallen.com> 1735 * cpuid.c: Added 7/ebx SGX & FDP_EXCPTN_ONLY flags. 1736 * cpuid.c: Added 7/ecx BNDLDX/BNDSTX MAWAU value field, RDPID & SGX_LC. 1737 * cpuid.c: Added d/0/eax MPX state field. 1738 * cpuid.c: In print_d_0_eax, split MPX and AVX-512 all_or_none fields 1739 into their component parts. Also added IA32_XSS PT state. 1740 * cpuid.c: In print_d_n_ecx, clarify XCR0 as user state and IA32_CXX as 1741 supervisor state. 1742 * cpuid.c: In print_d_n, add MPX and PT features. 1743 * cpuid.c: Renamed leaf 0x10 to Intel's new name. Corrected totally 1744 bogus interpretation of subleaf 0. 1745 * cpuid.c: Generalize subleaf 0x10/1 to also include 0x10/2, and 1746 provide new Intel correct names for each. 1747 * cpuid.c: Added 0x14/0 PTWRITE & power event trace. 1748 * cpuid.c: Added description for leaf 0x12 (SGX Capability) and all its 1749 subleaves. 1750 * cpuid.c: Added descriptionf or leaf 0x17 (SoC vendor) and its 1751 subleaves. 1752 * cpuid.c: Decode new leaf 2 cache descriptors: 0x64 & 0xc4. 1753 * cpuid.c: Updated Atom C2000 (Avoton) with A0/A1 steppings. 1754 * cpuid.c: Added Atom Z3n00 (Bay Trail-T B2/B3) specific stepping 1. 1755 * cpuid.c: Added Xeon D-1500 (Broadwell-DE) V2 stepping. 1756 * cpuid.c: Corrected Atom Z8000 (Cherry Trail) with correct model, per 1757 changes in its spec update. 1758 * cpuid.c: Change the (0,6),(5,14) Skylake descriptions to be more vague 1759 to reflect the larger set of existing processors now. 1760 * cpuid.c: Add actual information for the (0,6),(4,14) Skylake 1761 processors. 1762 * cpuid.c: Add actual information for the (0,6),(5,14) Broadwell-E 1763 processors. 1764 * cpuid.c: Add actual information for the (0,6),(4,15) Broadwell and 1765 Broadwell-EX processors. 1766 * cpuid.c: Added vague mentions of Goldmont (0,6),(5,12) and (0,6),(5,15) 1767 based on 325462 Table 35-1. 1768 * cpuid.c: Add Atom S1200 (Centerton) under (0,6),(3,6) thanks to an 1769 example provided by Jirka Hladky. 1770 * cpuid.c: Added Eden to the list of possible meanings of VIA 1771 (0,6),(6,13). An example provided by Daniel Wyatt shows that they 1772 sometimes use the simple Eden brand for this architecture. 1773 * cpuid.man: Added various new Intel documents used while making the 1774 above changes. 1775 * cpuid.c: Made -f - operate on stdin. 1776 1777 Wed Jun 22 2016 Alan Cox <alan@lxorguk.ukuu.org.uk> 1778 * cpuid.c: Added out-of-memory checks to strregexp. 1779 1780 Mon Oct 19 2015 Todd Allen <todd.allen@etallen.com> 1781 * Updated cpuid.man's list of information sources with new sources used 1782 in the 20151017 release (and one renamed source). 1783 1784 Sat Oct 17 2015 Todd Allen <todd.allen@etallen.com> 1785 * Made new release. 1786 * cpuid.c: Updated synth decoding for Broadwell processors. 1787 * cpuid.c: Added 0xd leaf field. 1788 * cpuid.c: Updated and expanded 0x14 leaf fields. 1789 * cpuid.c: Added synth decoding for Intel Xeon E7 v2 (Ivy Bridge-EX). 1790 * cpuid.c: Added synth decoding for Intel Core i5/i7 (Skylake). 1791 * cpuid.c: Added vague synth decodings for a few more future processor 1792 models from Intel 64 and IA-32 Architectures Software Developer's 1793 Manual (325462), Table 35-1. 1794 1795 Thu Oct 15 2015 Hubert Chrzaniuk <hubert.chrzaniuk@intel.com> 1796 * cpuid.c: Decode new leaf 2 cache descriptors: 6a, 6b, 6c, 6d. 1797 * cpuid.c: added synth decoding for Knights Landing. 1798 [NOTE FROM Todd Allen: There is no datasheet or spec update for 1799 Knights Landing yet, but Intel 64 and IA-32 Architectures Software 1800 Developer's Manual (325462), Table 35-1 mentions that it will have the 1801 family & model (0,6),(5,7). 1802 1803 Sat Jun 6 2015 Todd Allen <todd.allen@etallen.com> 1804 * Made new release. 1805 * cpuid.man: Added 325462 manual. 1806 * cpuid.c: Added new & missing decodings for: 4/ecx, 6/eax, 7/ebx, 7/ecx. 1807 * cpuid.c: Overhauled handling of 0xd leaf, based on new and more 1808 extensive information in the Intel CPUID documentation, particularly 1809 on how to decide which leaves are valid. The approach functions 1810 correctly for the subset described in the AMD documentation, too. 1811 This overhaul includes information on the XSAVEC, XGETBV, and 1812 XSAVES/XRSTORS instructions. 1813 * cpuid.c: Renamed 0xf leaves to include "Monitoring". 1814 * cpuid.c: Added 0x10 leaves for QoS Enforcement. 1815 * cpuid.c: Added new leaf 2 cache meanings: 0x1d, 0x24, 0xa0, 0xc3. 1816 * cpuid.c: Added missing i7 synth decoding for (0,6),(3,14). 1817 * cpuid.c: Corrected Atom Z3000 model & stepping which were bafflingly 1818 wrong: (0,6)(3,5),1 -> (0,6)(3,7),8. 1819 * cpuid.c: Corrected other Bay Trail stepping names for Celeron/Pentium 1820 N and J series. 1821 * cpuid.man: Added references to a bunch of new Intel manuals. 1822 * cpuid.c: Added synth decoding for Intel Xeon Phi (Knights Corner). 1823 * cpuid.c: Added synth decoding for Intel Atom C2000 (Avoton). 1824 * cpuid.c: Added synth decoding for Intel Xeon E5-x600 (Haswell-EP). 1825 * cpuid.c: Added synth decoding for Intel Xeon E5-[48]800 (Haswell-EP). 1826 * cpuid.c: Added synth decoding for Intel Core M (Broadwell-Y). 1827 * cpuid.c: Added synth decoding for Intel Xeon D-1500 (Broadwell-DE). 1828 * cpuid.c: Added synth decoding for Intel i7-5000 Extreme (Haswell R2). 1829 * cpuid.c: Added synth decoding for Intel Atom Z8000 (Cherry Trail). 1830 * cpuid.c: Added synth decoding for Intel Pentium/Celeron N3000 1831 (Braswell). 1832 * cpuid.c: Added synth decoding for Intel i7 5th gen (Broadwell). 1833 * cpuid.c: Added synth decoding for Intel E3-1200 v4 (Broadwell). 1834 * cpuid.c: Added Xeon E5-4600 to synth decoding for other Sandy Bridge 1835 E5 processors (it was omitted accidentally). 1836 * cpuid.c: Added Pentium D 9xx Processor to synth decoding for Presler 1837 D0 (it was omitted accidentally). 1838 1839 Fri Mar 21 2014 Todd Allen <todd.allen@etallen.com> 1840 * cpuid.c: Deal with 0-width PKG_width fields in print_apic_synth(), 1841 for CPUs where the SMT_width + CORE_width >= 8. This happens on 1842 Xeon Phi chips. 1843 1844 Wed Feb 12 2014 Todd Allen <todd.allen@etallen.com> 1845 * cpuid.c: Added CLFLUSHOPT instruction field to leaf 7, ebx. 1846 * cpuid.c: Added Processor Frequency Information leaf (0x16). 1847 1848 Tue Feb 11 2014 Todd Allen <todd.allen@etallen.com> 1849 * Makefile: Added src_tar rule. 1850 1851 Tue Feb 11 2014 Todd Allen <todd.allen@etallen.com> 1852 * cpuid.c: Made changes to allow building and running on kFreeBSD. This 1853 started out as a patch from Andrey Rahmatullin, but I refactored it. 1854 The changes to disable the cpuid kernel support are protected by a 1855 USE_CPUID_MODULE definition. And there's an additional sanity check 1856 to reject -k in that case. The changes to use the library versions of 1857 sched_setaffinity are protected by USE_KERNEL_SCHED_SETAFFINITY. I 1858 continue to go straight to the kernel on linux, though. 1859 1860 Tue Feb 11 2014 Todd Allen <todd.allen@etallen.com> 1861 * Makefile: Reorganized Andrey Rahmatullin's changes a bit and used 1862 them in my development build rules (make todd) too. 1863 1864 Tue Feb 11 2014 Andrey Rahmatullin <wrar@wrar.name> 1865 * Makefile: Honor CPPFLAGS, CFLAGS and LDFLAGS from the environment. 1866 1867 Mon Jan 27 2014 Todd Allen <todd.allen@etallen.com> 1868 * Makefile: Change to my development build rules (make todd) to use ld's 1869 --hash-style=both to avoid a SIGFPE when running on very old 32-bit 1870 systems. It has no effect on the tool for anyone else. 1871 1872 Thu Jan 23 2014 Todd Allen <todd.allen@etallen.com> 1873 * Made new release. 1874 1875 Thu Jan 23 2014 Todd Allen <todd.allen@etallen.com> 1876 * cpuid.c: Stop displaying raw hex for 0xc and 0xe leaves, because they 1877 are reserved and just contain zeroes. 1878 * cpuid.c: Fixed missing leaf 0xf subleaf 1 in do_real(). 1879 * cpuid.man: Added reference to Intel Architecture Instruction Set 1880 Extensions Programming Reference (319433). 1881 * cpuid.c: Added new feature flags from that document. 1882 1883 Sun Jan 12 2014 Todd Allen <todd.allen@etallen.com> 1884 * Made new release. 1885 1886 Sun Jan 12 2014 Todd Allen <todd.allen@etallen.com> 1887 * cpuid.c: Added Celeron B800 synth decoding. 1888 * cpuid.c: Added Pentium G3000 & Celeron G1800 synth decoding. 1889 * cpuid.c: Added 4th Gen Core family mobile processors synth decoding. 1890 * cpuid.c: Added information about E5 v2 processors (no longer just 1891 engineering samples) and related Ivy Bridge-EP processors. 1892 * cpuid.c: Added Bay Trail (Atom Z3000, etc.) processors synth decoding. 1893 1894 Sun Jan 12 2014 Todd Allen <todd.allen@etallen.com> 1895 * cpuid.man: Added reference to Intel decoding from Intel 64 and IA-32 1896 Architectures Software Developer's Manual Volume 2A: Instruction Set 1897 Reference, A-M (253666). 1898 * cpuid.c: Added new Intel decodings from that document. 1899 1900 Sun Jan 12 2014 Todd Allen <todd.allen@etallen.com> 1901 * cpuid.c: Added new (instruction supported synth) field to report on 1902 instruction support when knowledge of that is scattered across 1903 multiple CPUID leaves. PREFETCH/PREFETCHW is the weirdest example. 1904 * cpuid.c: Clarified the raw PREFETCH/PREFETCHW field in 80000001 edx 1905 leaf with the 3DNow! prefix, similar to the description in the AMD 1906 CPUID docs. Thanks to Chris Orgill for reporting these two issues. 1907 1908 Fri Sep 27 2013 Todd Allen <todd.allen@etallen.com> 1909 * cpuid.c: Added missing break to decode_amd_model(), family (0,15), 1910 model (4,0), case 0x18. Thanks to David Binderman for reporting this. 1911 1912 Mon Jun 10 2013 Todd Allen <todd.allen@etallen.com> 1913 * Made new release. 1914 1915 Mon Jun 10 2013 Todd Allen <todd.allen@etallen.com> 1916 * cpuid.c: Added mention of Opteron 3200 (Zurich) chips, accidentally 1917 omitted from yesterday's updates. 1918 1919 Sun Jun 9 2013 Todd Allen <todd.allen@etallen.com> 1920 * Made new release. 1921 1922 Sun Jun 9 2013 Todd Allen <todd.allen@etallen.com> 1923 * cpuid.c: Updated 14h Model 00h-0Fh AMD model tables. 1924 * cpuid.c: Added synth decoding for Opteron x300 (Piledriver) chips. 1925 * cpuid.c: Added synth decoding for family 16h processors, tentatively 1926 identified as Steamroller. 1927 * cpuid.man: Added new AMD 15h Model 10h-1Fh, and AMD 16h Model 00h-0Fh 1928 manuals. 1929 1930 Sat Jun 8 2013 Todd Allen <todd.allen@etallen.com> 1931 * cpuid.c: Added sanity check to 0xCxxxxxxx leaves to check for an 1932 unreasonably large indicated maximum leaf number. If found, further 1933 walk of them is halted. 1934 * cpuid.c: Skip 0x4xxxxxxx leaves if cpuid does not indicate that the 1935 environment is a guest. This was suggested by Steven Levine, although 1936 I implemented it differently. 1937 1938 Sat Jun 8 2013 Todd Allen <todd.allen@etallen.com> 1939 * cpuid.c: Clarified some KVM hypervisor leaf feature flags that Eduardo 1940 Habkost pointed out. Added a couple new flags. 1941 1942 Sat Jun 8 2013 Todd Allen <todd.allen@etallen.com> 1943 * cpuid.c: Extended Eduardo Habkost's stash separation to include the 1944 0x80000008 leaf, and the leaves that inform transmeta_info. 1945 1946 Sat Jun 8 2013 Eduardo Habkost <ehabkost@raisama.net> 1947 * cpuid.c: This patch separates the code that changes fields in the 1948 'stash' struct from the code that prints that information. This way, 1949 the stash struct will get updated even when in raw mode, so other 1950 parts of the code can use that information. 1951 [NOTE FROM Todd Allen: It used to be that the stash was only set and 1952 used in cooked mode, but some uses dealing with the hypervisor snuck 1953 out and were used all the time. This new separation is only really 1954 necessary for the hypervisor fields, but it's good practice to do all 1955 the fields this way, so I'm accepting the patch as is.] 1956 1957 Sat Jun 8 2013 Todd Allen <todd.allen@etallen.com> 1958 * cpuid.c: Added synth decoding for Celeron G400/G500. 1959 * cpuid.c: Added synth decoding for Cedarview B3. 1960 * cpuid.c: Added synth decoding for Ivy Bridge i3 processors. 1961 * cpuid.c: Added synth decoding for Ivy Bridge Pentium G1600/G2000/G2100. 1962 * cpuid.c: Added synth decoding for Ivy Bridge Pentium 1963 900/1000/2000/2100. 1964 * cpuid.c: Clarified that Ivy Bridge Xeon E3-1200 is actually E3-1200 v2. 1965 * cpuid.c: Added vague synth decoding for Haswell, but spec updates 1966 show no specific chips or steppings yet. 1967 * cpuid.c: Expanded A100/A110 synth decoding to include semi-official 1968 Pentium M (Crofton) processors in Apple TV boxes. 1969 * cpuid.c: Added Xeon E5-2600 v2 engineering sample. Perhaps this will 1970 be the final synth decoding for them, but for now it's just marked as 1971 an engineering sample. 1972 * cpuid.man: Added new Intel manuals. 1973 1974 Fri Aug 24 2012 Todd Allen <todd.allen@etallen.com> 1975 * cpuid.c: Added sanity check to 0x4xxxxxxx leaves to check for an 1976 unrecognized hypervisor and an unreasonably large indicated maximum 1977 leaf number. If found, further walk of them is halted. 1978 1979 Tue Aug 21 2012 Todd Allen <todd.allen@etallen.com> 1980 * cpuid.c: Cleaned up printf(name) statements that were admonished by 1981 clang. 1982 1983 Fri Jun 1 2012 Todd Allen <todd.allen@etallen.com> 1984 * Made new release. 1985 1986 Thu May 31 2012 Todd Allen <todd.allen@etallen.com> 1987 * cpuid.c: Updated CPUID feature flags. 1988 * cpuid.c: Updated CPUID function 7 to support sub-leaves (mostly for 1989 future functionality that might be added to them). 1990 * cpuid.c: Updated synth decoding for Intel Dothan C0 because some use 1991 65nm process now. 1992 * cpuid.c: Updated Intel EP80579 synth to mention 65nm process. 1993 * cpuid.c: Added synth decoding for Intel Atom E600 series. 1994 * cpuid.c: Updated synth decoding for Intel Sandy Bridge D2 to include J1 1995 and Q0, which have the same CPUID. 1996 * cpuid.c: Added synth decoding for Intel Atom D2000/N2000 (Cedarview). 1997 * cpuid.c: Added synth decoding for Intel Sandy Bridge-E. 1998 * cpuid.c: Added synth decoding for AMD Llano. 1999 * cpuid.c: Improved distinction between AMD Interlagos & Zambezi. 2000 * cpuid.c: Added synth decoding for RDC IAD 100. 2001 * cpuid.c: Fixed some formatting bugs for Transmeta-specific leaves. 2002 * cpuid.c: Added synth decoding for some of VIA's versions of WinChips. 2003 * cpuid.man: Added mentions of spec updates for several Atoms, i7 for 2004 LGA-2011, and Xeon E5; and AMD 12h family. 2005 2006 Wed May 30 2012 Todd Allen <todd.allen@etallen.com> 2007 * cpuid.c: Fixed ancient bug in distinguishing Irwindale from Nocona 2008 (they differ only by L2 cache size). 2009 * cpuid.c: Added synth decoding for desktop and mobile Ivy Bridge. 2010 2011 Sat Feb 25 2012 Todd Allen <todd.allen@etallen.com> 2012 * Made new release. 2013 * cpuid.c: Cleaned up hypervisor-specific leaves for KVM. 2014 * cpuid.man: Added mention of KVM cpuid documentation. 2015 2016 Fri Feb 24 2012 Todd Allen <todd.allen@etallen.com> 2017 * cpuid.c: Added synth decoding for Intel Westmere-EX processors. 2018 * cpuid.c: Added synth decoding for AMD family 15h chips: AMD FX 2019 (Zambezi), Opteron 6200 (Interlagos), and Opteron 4200 (Valencia). 2020 * cpuid.c: Added synth decoding for AMD Z-Series and other Fusion 2021 chip ON-C0 steppings. 2022 * cpuid.c: Added synth decoding for Atom Z600 (Lincroft). 2023 * cpuid.c: Updated AMD model decoding for family 10h processors. 2024 * cpuid.man: Added mention of AMD family 14h and 15h documents, and 2025 Intel Westmere-EX & Lincroft documents. 2026 * cpuid.man: Removed obsolete limitation about 0x8000001b. 2027 * cpuid.c: Added support for hypervisor leaves (0x4000000 and after). 2028 Interpreted known generic leaves. Interpreted hypervisor-specific 2029 leaves for Xen (deduced from source, as no documentation on them 2030 exists). Interpreted hypervisor-specific leaves for KVM. Interpreted 2031 hypervisor-specific leaves for Microsoft. 2032 2033 Tue Jan 3 2012 Todd Allen <todd.allen@etallen.com> 2034 * cpuid.c: Added synth decoding for Athlon 64 (Venice DH-E6) chips. 2035 2036 Wed Nov 2 2011 Todd Allen <todd.allen@etallen.com> 2037 * cpuid.c: Added saw_4 and saw_b stash flags to deal with chips that 2038 report 0xc codes but still omit 0xb codes. This way, a maximum code 2039 of 0xc no longer implies the presence of 0xb codes for things like 2040 APIC decoding. 2041 2042 Mon Mar 28 2011 Todd Allen <todd.allen@etallen.com> 2043 * cpuid.c: Added APIC synth decoding for AMD, deduced by analogy to Intel 2044 code and the multiprocessor synth logic. 2045 2046 Mon Mar 7 2011 Todd Allen <todd.allen@etallen.com> 2047 * cpuid.c: Added some decoding for VIA 0xc0000002 codes, based on 2048 information from Juerg Haefliger. Very incomplete because VIA 2049 doesn't document their functions well. 2050 * cpuid.c: Fixed output of 0xc0000001 raw dump to conform to new style. 2051 2052 Sat Mar 5 2011 Todd Allen <todd.allen@etallen.com> 2053 * Made new release. 2054 2055 Fri Mar 4 2011 Todd Allen <todd.allen@etallen.com> 2056 * cpuid.c,cpuid.man: Added Celeron T1000 series, previously missing. 2057 * cpuid.c,cpuid.man: Added Celeron Mobile P4000, U3000 series. 2058 * cpuid.c,cpuid.man: Added current Sandy Bridge processors. 2059 2060 Thu Mar 3 2011 Todd Allen <todd.allen@etallen.com> 2061 * cpuid.c: Added detection of PCIDs & TSC-DEADLINE. 2062 * cpuid.c: Verified Mike Stroyan CPUID 2 cache meanings from Intel CPUID 2063 document (241618-037). Added 0x76 meaning. 2064 * cpuid.c: Added various new flags from Intel 241618-037. 2065 * cpuid.c,cpuid.man: Added AMD family 14h processors. 2066 * cpuid.c,cpuid.man: Updated Intel process id table, mostly as just 2067 generalizations. 2068 2069 Tue Nov 9 2010 Todd Allen <todd.allen@etallen.com> 2070 * cpuid.c: Update the usage() screen, since some of its -i and -1 2071 comments are incorrect now. 2072 2073 Mon Oct 4 2010 Todd Allen <todd.allen@etallen.com> 2074 * cpuid.c, cpuid.man: Added AMD Geode LX. 2075 * cpuid.c: Added NSC Geode GX2 and AMD Geode GX. 2076 * cpuid.c, cpuid.man: Added AMD Geode NX. 2077 2078 Sat Oct 2 2010 Todd Allen <todd.allen@etallen.com> 2079 * Made new release. 2080 * cpuid.c,cpuid.man: Added Intel Atom N500. 2081 2082 Thu Sep 30 2010 Todd Allen <todd.allen@etallen.com> 2083 * cpuid.c,cpuid.man: Added support for Intel Tolapai (SoC). 2084 * cpuid.c,cpuid.man: Added support for Intel Clarkdale chips from 2085 specification update 323179. 2086 * cpuid.c: Generalized decode_amd_model by adding full brand tables for 2087 AMD chips. If a BIOS doesn't recognize a chip it writes 2088 "model unknown" into its brand string via MSR's. 2089 decode_override_brand detects that and uses the decode_amd_model brand 2090 to differentiate CPUs. 2091 * cpuid.c: Corrected 80000001/ebx PkgType, BrandId, and str1 bit fields. 2092 * cpuid.c: Corrected problems with brand field decoding because its bit 2093 field with differs from architecture to architecture. 2094 * cpuid.c: decode_amd_model: the partialmodel decrement special case 2095 applies only to XF=1,F=15; and not to XF=2,F=15. 2096 2097 Mon Sep 27 2010 Todd Allen <todd.allen@etallen.com> 2098 * cpuid.c: Added support for NSC/AMD Geode GX1. 2099 2100 Wed Sep 8 2010 Todd Allen <todd.allen@etallen.com> 2101 * cpuid.c: Corrected the Transmeta processor revisions, which should've 2102 been in hex instead of octal. 2103 2104 Thu Sep 2 2010 Todd Allen <todd.allen@etallen.com> 2105 * cpuid.c: Added a couple vague steppings for Transmeta Efficeon TM8000 2106 processors. Updated some transmeta bitfields. This is all done 2107 blind, as I have no examples of these chips, little documentation, and 2108 the company is long defunct. 2109 2110 Thu Sep 2 2010 Todd Allen <todd.allen@etallen.com> 2111 * Made new release. 2112 * cpuid.c: Fixed a few header strings that had incorrect function hex 2113 codes or registers. 2114 2115 Wed Sep 1 2010 Todd Allen <todd.allen@etallen.com> 2116 * Made new release. 2117 * cpuid.c: Fixed buffer size in do_file() to be able to read new 2118 raw dumps with ecx information. It needed a couple more characters. 2119 * cpuid.c: Added Celeron M (Yonah D0) & Celeron M (Merom-L1 A1) synth 2120 entries. 2121 * cpuid.c: added Xeon Processor LV (Sossaman D0). 2122 * cpuid.c: Update Itanium chips in the synth tables. Sadly, this all 2123 still is being done blind, as I have no access to any Itanium chips. 2124 * cpuid.c: Wrote an x86_64 counterpart to the assembly code for 2125 bits_needed(). 2126 * Makefile, cpuid.proto.spec: Changed to support building for both i386 2127 and x86_64. 2128 2129 Tue Aug 31 2010 Todd Allen <todd.allen@etallen.com> 2130 * Made new release. 2131 * cpuid.c: Rearranged synth rules and substantially simplified query 2132 macros into something like the form I was hoping for when I started 2133 this redesign. 2134 * cpuid.c: Added changes from the new AMD CPUID document that claims to 2135 have been released in September 2010! 2136 * cpuid.c: Changed raw dump to include %ecx values to accomodate CPUID 2137 functions with gaps in the useful %ecx range (e.g. 0xd). The file 2138 parser accepts either the old or new forms. 2139 * Makefile, cpuid.proto.spec: Updated build scheme for my current 2140 systems. 2141 * LICENSE: Changed to a GPL license. 2142 2143 Mon Aug 30 2010 Todd Allen <todd.allen@etallen.com> 2144 * cpuid.c: Semi-mechanically eliminated the codes used to 2145 disambiguate in the synth string and replaced them with queries, 2146 which I think will be more general-purpose and will allow me to 2147 eliminate a lot of the problem with codes appropriate for one 2148 model being a problem for subsequent models (e.g. the Core Solo 2149 vs. Core Duo distinction). There still are general-purpose 2150 queries like there were general-purpose codes, but the 2151 special-case queries will only matter for those families that 2152 care about them. This does mean that it's possible for multiple 2153 queries to register as true, so I have to be more careful with 2154 the order of chips in the synth tables. 2155 2156 Fri Aug 27 2010 Todd Allen <todd.allen@etallen.com> 2157 * Tested on a variety of CPUs. 2158 * cpuid.c: Corrected Mobile Turion checking in decode_brand. 2159 * cpuid.c: Added synth entries for 6/15/4 pre-production 2160 Conroe B0/Woodcrest B0. 2161 * cpuid.c: Added synth entries for Santa Rosa F3 stepping 2162 (undocumented). 2163 * cpuid.c: Fixed synth entries for Brisbane, Toledo, and Windsor to 2164 expect code DA (for dual-core Athlons). 2165 * cpuid.c: Generalized the check for Intel Extreme Edition chips. 2166 * cpuid.c: Added synth entries Core 2 Quad (Conroe) chips. 2167 * cpuid.c: Added synth entry for VIA 6/13/0 chip. Unfortunately, there 2168 is no documentation and very little anecdotal evidence of this chip, 2169 so the description is vague. 2170 * cpuid.c: Added addition CPUID function 2 cache codes from Mike 2171 Stroyan. 2172 * cpuid.c: Fixed some cut&paste errors that had EAX where it should 2173 have been EBX, as reported by Mike Stroyan 2174 * cpuid.c: Added very short synth table for SiS chips. I found no 2175 documentation on these, so I just have the one case. 2176 * cpuid.c: Fixed the (synth) strings for oddball chips, which suffered 2177 from a cut&paste error. 2178 * cpuid.c: Simplified some of the fallback strings that had grown 2179 ridiculously long. 2180 2181 Thu Aug 26 2010 Todd Allen <todd.allen@etallen.com> 2182 * Tested on a variety of CPUs. 2183 * cpuid.c: Added more logic for Woodcrest pre-production chips. 2184 * cpuid.c: Corrected synth logic for VIA Antaur chips. 2185 * cpuid.c: Added synth for plain vanilla Thoroughbred Athlon. 2186 2187 Wed Aug 25 2010 Todd Allen <todd.allen@etallen.com> 2188 * Tested on a variety of CPUs. 2189 * cpuid.c: Fixed a couple bugs with decoding processor numbers in 2190 print_synth_amd_model. 2191 2192 Tue Aug 24 2010 Todd Allen <todd.allen@etallen.com> 2193 * cpuid.c: Further changes to mp_synth decoding, including tracking 2194 of the decoding method used (there are around 4 major approaches, 2195 depending on how you count). 2196 * cpuid.c: Added apic_synth decoding to find the appropriate field 2197 widths and decode the process local APIC physical ID. This is useful 2198 in its own right, but also helps convince me that many Intel chips 2199 really do claim to have hyperthreads even though they don't. 2200 * cpuid.c: Added support for direct instruction (-i) functionality to 2201 report on all CPUs by calling sched_setaffinity to reschedule the 2202 process on each CPU. This is now the default behavior for -i, but 2203 it can be overridden with the -1 option. 2204 * cpuid.c: added Barcelona B1 (undocumented chip) synth decoding. 2205 2206 Mon Aug 23 2010 Todd Allen <todd.allen@etallen.com> 2207 * cpuid.c: Made real_get pass the requested ecx values even when 2208 using -k. Modern linux kernel expect the ecx values in the upper 2209 32 bits of the file offset (i.e. lseek64). 2210 * cpuid.c: Worked out a fallback for determining mp_synth information 2211 for Intel chips which lack CPUID function 4. 2212 * cpuid.c: Added mechanism for determining mp_synth information from 2213 CPUID function 11 information if it's available (because if it's 2214 present on Intel chips, it's the only reliable way; the older 2215 mechanisms return gibberish). 2216 2217 Fri Aug 20 2010 Todd Allen <todd.allen@etallen.com> 2218 * cpuid.c, cpuid.man: Added to synth even more Nehalem chips. 2219 * cpuid.c: Added 6/15 model for VIA Nano, but there's very little 2220 detailed information on this chip, so that's it. 2221 * cpuid.c: Corrected some AMD codename confusion from 2006: 2222 Dublin->ClawHammer/Odessa, Sonora->Dublin, 2223 Palermo(mobile)->Georgetown/Sonora, Lancaster->Lancaster/Richmond, 2224 Richmond->Taylor/Trinidad. 2225 * cpuid.c: Overhauled the AMD model dumping code to understand new 2226 families. 2227 * cpuid.c: Tweaked decode_mp_synth to use ApicIdCoreIdSize, per AMD's 2228 CPUID recommendations. 2229 2230 Thu Aug 19 2010 Todd Allen <todd.allen@etallen.com> 2231 * cpuid.c, cpuid.man: Updated synth tables for Intel Xeons. 2232 * cpuid.c: Removed all the "How to distinguish" comments, since 2233 it seems to be very common for Intel to have indistinguishable 2234 processors nowadays (the old cache-checking tricks are unreliable 2235 now). 2236 * cpuid.c, cpuid.man: Added to synth additional Nehalem chips as I'm 2237 able to hunt them down. 2238 2239 Wed Aug 18 2010 Todd Allen <todd.allen@etallen.com> 2240 * cpuid.c, cpuid.man: Updated synth tables for Intel Core 2, Atom, 2241 Celeron, and Pentium chips based on the same cores. 2242 2243 Tue Aug 17 2010 Todd Allen <todd.allen@etallen.com> 2244 * cpuid.c, cpuid.man: Updated synth tables for AMD family 10h (K10) 2245 and family 11h processors. 2246 * cpuid.c: simplified print_x_synth_amd by pruning its table down to 2247 just the three families that differ from normal 1/eax simple synth, 2248 and falling back on 1/eax simple synth otherwise. 2249 2250 Mon Aug 16 2010 Todd Allen <todd.allen@etallen.com> 2251 * cpuid.c: Added new steppings to synth tables using latest spec 2252 updates for all AMD processor families already in them. 2253 * cpuid.c, cpuid.man: Updated synth tables for AMD family 0Fh (K8) 2254 processors. 2255 2256 Fri Aug 13 2010 Todd Allen <todd.allen@etallen.com> 2257 * cpuid.c: Updated raw data dump based on latest CPUID documentation 2258 from Intel & AMD. 2259 * cpuid.c: Fixed dump of function 4 to iterate over all caches. 2260 2261 Thu Aug 12 2010 Todd Allen <todd.allen@etallen.com> 2262 * cpuid.c: Reorganized synth tables to always use extended family 2263 and extended model numbers since they are so prevalent on modern 2264 chips. 2265 * cpuid.c: Added new steppings to synth tables using latest spec 2266 updates for all Intel processor families already in them. 2267 2268 Sun Nov 26 2006 Todd Allen <todd.allen@etallen.com> 2269 * cpuid.c: Recognize Intel Core 2 Extreme Edition from brand string. 2270 Thanks to Tony Freitas for explaining that Ennnn means desktop while 2271 Xnnnn means Extreme Edition for those processors. 2272 2273 Wed Nov 22 2006 Todd Allen <todd.allen@etallen.com> 2274 * cpuid.c: Recognize Itanium2 Montecito C2. 2275 * cpuid.c: Recognize Intel Core 2 Duo Mobile (Conroe B2). 2276 * cpuid.c: Recognize Intel Quad-Core Xeon Processor 5300 (Woodcrest B3) 2277 and Intel Core 2 Extreme Quad-Core Processor QX6700 (Woodcrest B3). 2278 * cpuid.c: Recognize Intel Celeron D Processor 36x (Cedar Mill D0). 2279 * cpuid.c: Distinguish Core 2 Duo from Core 2 Extreme Edition based on 2280 presence or absence of hyperthreading. Thanks to Tony Seacow for 2281 providing output for numerous processors and the advice about 2282 hyperthreading. 2283 2284 Thu Nov 2 2006 Todd Allen <todd.allen@etallen.com> 2285 * cpuid.c: Changed "number of logical CPU cores - 1" to "number of CPU 2286 cores - 1". 2287 2288 Sun Sep 17 2006 Todd Allen <todd.allen@etallen.com> 2289 * Made new release. 2290 * cpuid.c: Made the cpuid instruction (-i, --inst options) the default. 2291 * cpuid.c: Added -k, --kernel option to cause the kernel module to be 2292 used. 2293 * cpuid.c: Removed confusing CPU number from output when using 2294 the cpuid instruction. 2295 * cpuid.man: Updated with new options. 2296 * cpuid.c, Makefile: Changed i386 _llseek kludge to workaround 2297 offsets >= 0x80000000. Now using -D_FILE_OFFSET_BITS=64 in the 2298 Makefile instead. This should allow the i386 cpuid to work on 2299 an x86_64 system. 2300 * cpuid.c: Added knowledge of CPU modules to synthesized field: Tulsa, 2301 Woodcrest B1 (pre-production) 2302 * cpuid.c: In synthesized model field, properly distinguish between 2303 Intel Pentium D Processor 8x0 and Intel Pentium Extreme Edition 2304 Processor 840 (both Smithfields). 2305 * cpuid.man: Added mention of new 7100 series spec updates. 2306 * cpuid.spec: Changed Copyright to License. 2307 2308 Thu Aug 23 2006 Todd Allen <todd.allen@etallen.com> 2309 * cpuid.c: Removed unnecessary one_cpu argument from do_file. 2310 * cpuid.c: Added -v option to display version number. 2311 2312 Wed Aug 23 2006 Todd Allen <todd.allen@etallen.com> 2313 * Made new release. 2314 2315 Tue Aug 22 2006 Todd Allen <todd.allen@etallen.com> 2316 * cpuid.c, cpuid.man: Added -i option to use the CPUID instruction 2317 directly instead of the CPUID kernel module. 2318 * cpuid.c: Change Pentium Processor 9x0 to 9xx because of 9x5 2319 processors. 2320 * cpuid.man: Updated information about determining synthesized model 2321 information, and added information about determining synthesized 2322 multiprocessor information. 2323 2324 Mon Aug 7 2006 Todd Allen <todd.allen@etallen.com> 2325 * cpuid.proto.spec: Change URL to cpuid-specific page. 2326 2327 Sun Aug 6 2006 Todd Allen <todd.allen@etallen.com> 2328 * Made new release. 2329 2330 Sat Aug 5 2006 Todd Allen <todd.allen@etallen.com> 2331 * cpuid.c: Added support for differentiating Core 2 Duo CPUs from Xeon 2332 5100 CPUs based on the brand string. 2333 * cpuid.c: Clarified that CPUID 4 ECX contains one less than the 2334 number of sets. 2335 * cpuid.c: Added support for CPUID 5 ecx & edx. 2336 * cpuid.c: Added support for CPUID 6 ecx. 2337 * cpuid.c: Added support for CPUID 0xa eax & ebx. 2338 * cpuid.c: Made CPUID functions 7, 8, and 9 reserved (i.e. say nothing 2339 until and unless they are defined). 2340 * cpuid.c: Corrected CPUID 1 ecx xTPR disabnle. 2341 2342 Wed Aug 2 2006 Todd Allen <todd.allen@etallen.com> 2343 * cpuid.c: Corrected bug with Core 2 Duo recognition. 2344 * cpuid.c: Distinguish between Allendale and Conroe cores based on 2345 L2 cache size. 2346 * cpuid.c: Added VIA C7 & C7-M names to Esther WinChip C5J core CPUs. 2347 * cpuid.man: Mention wikipedia pages for CPUs. 2348 2349 Tue Aug 1 2006 Todd Allen <todd.allen@etallen.com> 2350 * cpuid.c: On help screen, clarified that -f option reads output from 2351 -r option. 2352 * cpuid.proto.spec: Used %{} macros for external command invocations. 2353 2354 Mon Jul 31 2006 Todd Allen <todd.allen@etallen.com> 2355 * Makefile: Removed install -o 0 -g 0 options. For installations 2356 from the tarball, the user will have to be root anyway. And for 2357 rpm, the %defattr() attribute in the spec is handling this more 2358 cleanly. Finally, those options are causing some non-root 2359 installations to have to be done by the root user, which is 2360 undesirable. 2361 * cpuid.c: Improved identification for VIA C3 (Samuel WinChip C5A core). 2362 * cpuid.c: Loosened up check for "Mobile AMD Athlon(tm) XP" by 2363 removing "-M" suffix. 2364 * cpuid.c: Recognize mobile Athlon XP (Thoroughbred). 2365 2366 Sun Jul 30 2006 Todd Allen <todd.allen@etallen.com> 2367 * Made new release. 2368 * cpuid.c: Fixed "deterministic cache parameters (4)", so that its 2369 children aren't staggered. 2370 * cpuid.c: Corrected Venice and Palermo processors with DH-E3 and 2371 DH-E6 steppings that had been reported as Toledo processors 2372 incorrectly. 2373 * cpuid.c: Corrected codename for the Athlon Thoroughbred's Duron 2374 counterpart: Applebred. 2375 * cpuid.c: Added code to distinguish Athlon XP Thortons from Bartons, 2376 based on L2 cache size. 2377 * cpuid.c: Added code to distinguish Athlon 64 X2 Manchester E6 from 2378 Athlon 64 X2 Toledo. 2379 * cpuid.c: Added Celeron Yonah C0. 2380 * cpuid.c: Added Core Yonah D0. 2381 * cpuid.c: Added Xeon Nocona R0 / Irwindale R0 stepping. 2382 * cpuid.c: Added Pentium 4 Cedar Mill C1, Pentium D Presler C1, and 2383 Xeon Dempsey C1. 2384 * cpuid.c: Added Xeon Woodcrest B2. 2385 * cpuid.c: Added Core 2 Conroe B1 & B2 & Core 2 Extreme Processor B1 & 2386 B2. 2387 * cpuid.c: Updated Itanium2 processors. 2388 * cpuid.man: Added Intel specification updates for new CPUs. 2389 2390 Wed Jul 26 2006 Todd Allen <todd.allen@etallen.com> 2391 * cpuid.c: In decode_brand, added check for "Athlon(TM) XP", equivalent 2392 to "Athlon(tm) XP". 2393 * cpuid.c: Fixed "80000002" typo in print_80860002_eax(). 2394 2395 Mon Jul 24 2006 Todd Allen <todd.allen@etallen.com> 2396 * cpuid.c: Distinguish properly between Core Solo, Core Duo, and 2397 Xeon Processor LV. Reorganized multi-processor decoding to 2398 support that. 2399 2400 Sun Jul 23 2006 Todd Allen <todd.allen@etallen.com> 2401 * cpuid.c: Fixed emission of raw values for cpuid code 2. 2402 * cpuid.c: Added -f file option to read raw hexadecimal input from a 2403 file and parse it instead of executing the cpuid instruction, and 2404 code reorganization to support this. 2405 2406 Mon May 22 2006 Todd Allen <todd.allen@etallen.com> 2407 * cpuid.c: Fixed "unrecogninzed" typo in error. 2408 2409 Fri Apr 7 2006 Todd Allen <todd.allen@etallen.com> 2410 * cpuid.proto.spec: Added %defattr so that the files in the rpm's are 2411 owned by "root" and not "todd". (Why did no one scream bloody murder 2412 about this before?) 2413 2414 Mon Apr 3 2006 Todd Allen <todd.allen@etallen.com> 2415 * Made new release. 2416 * cpuid.c: Added code to distinguish between the two different Dual-Core 2417 Xeon (Paxville A0) and Dual-Core Xeon Processor 7000 (Paxville A0). 2418 Empirically, the significant differences are the VMX flag and the 2419 "execution disable" flag. The VMX flag is in an Intel-defined 2420 CPUID function, so it's used. Thanks to Jason Nicholls for providing 2421 the Dual-Core Xeon (Paxville A0) output that made this possible. 2422 * cpuid.c: Added detection for Xeon Processor LV (Sossaman C0). 2423 2424 Mon Mar 13 2006 Todd Allen <todd.allen@etallen.com> 2425 * Made new release. 2426 * cpuid.c: Fixed code that distinguished processors based on 2427 presence or absence of L3 cache. Some of the cache codes weren't 2428 being recognized as L3 cache. 2429 2430 Sun Feb 26 2006 Todd Allen <todd.allen@etallen.com> 2431 * Made new release. 2432 2433 Wed Feb 22 2006 Todd Allen <todd.allen@etallen.com> 2434 * cpuid.c: Added VMX: virtual machine extensions to CPUID function 1, 2435 register ecx. 2436 * cpuid.c: Added SVM LBR virtualization to CPUID function 8000000a, 2437 register edx. 2438 * cpuid.c: Fixed cut & paste header error in print_8000000a_eax. 2439 2440 Tue Feb 21 2006 Todd Allen <todd.allen@etallen.com> 2441 * cpuid.c: Renamed "hyper-threading technology" field to 2442 "hyper-threading / multi-core supported" to eliminate some confusing 2443 situations, such as Northwood chips which nominally support hyper- 2444 threading, but where it is disabled in the chip; or where hyper- 2445 threading is disabled in the BIOS; or AMD multi-core chips, which 2446 indicate TRUE here, but all of which lack hyper-threading at present. 2447 * cpuid.c: Updated family 15 description, which had grown very stale. 2448 * cpuid.c: Generalized Intel Pentium D Processor 900 to 9x0. 2449 * cpuid.c: Added Processor Number info to Smithfield processors. 2450 2451 Wed Feb 8 2006 Todd Allen <todd.allen@etallen.com> 2452 * Made new release. 2453 * cpuid.c: Use defined(i386) instead of __LONG_MAX__ to determine 2454 whether or not it's necessary to use _llseek(). Fixes handling of 2455 functions >= 2**31 on some build systems, like the one I used to 2456 build the binary rpm. (D'oh!) And also indirectly affects the 2457 (synth) field. 2458 * cpuid.c: Fix a busted error check in read_reg() that caused it to 2459 return success if the read() failed and quiet was true. 2460 * LICENSE: Created LICENSE file (using content straight out of the 2461 man page). 2462 2463 Tue Feb 7 2006 Todd Allen <todd.allen@etallen.com> 2464 * Made new release. 2465 * cpuid.c: Correctly distinguish Egypt/Italy processors. 2466 * cpuid.c: Fixed minor problems in error checking in open_file(). 2467 * cpuid.spec: Fixed bad Packager field. 2468 * cpuid.spec: Include ChangeLog. 2469 * cpuid.man: Added -r/--raw description. 2470 * cpuid.man: Clarified info used for (synth) field. 2471 * cpuid.man: Fixed version number & date. 2472 * Makefile: Reworked to make it easy for people other than me to build 2473 and install. 2474 * cpuid.spec: Used new Makefile organization 2475 * Makefile: Fixed production of spec file so that it's possible to 2476 rebuild with the srpm without having to specify %version and 2477 %release. 2478 2479 Mon Feb 6 2006 Todd Allen <todd.allen@etallen.com> 2480 * Initial public release.