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Member "cpuid-20201006/ChangeLog" (6 Oct 2020, 84760 Bytes) of package /linux/misc/cpuid-20201006.src.tar.gz:


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    1 Tue Oct  6 2020 Todd Allen <todd.allen@etallen.com>
    2 	* Made new release.
    3 
    4 Tue Oct  6 2020 Todd Allen <todd.allen@etallen.com>
    5 	* cpuid.c: Added 6/eax enhanced hardware feedback interface.
    6 	* cpuid.c: Added 6/ecx number of enh hardware feedback classes.
    7 	* cpuid.c: Added 7/0/ecx KL: key locker.
    8 	* cpuid.c: Added 7/0/edx UINTR: user interrupts.
    9 	* cpuid.c: Added 7/0/edx AVX512_FP16: fp16 support.
   10 	* cpuid.c: Added 7/1/eax AVX-VNNI: AVX VNNI neural network instrs.
   11 	* cpuid.c: Added 7/1/eax zero-length MOVSB.
   12 	* cpuid.c: Added 7/1/eax fast short STOSB.
   13 	* cpuid.c: Added 7/1/eax fast short CMPSB, SCASB.
   14 	* cpuid.c: Added 7/1/eax HRESET: history reset support.
   15 	* cpuid.c: Added 0xa/ecx fixed counter support enumeration.
   16 	* cpuid.c: Added 0xd/0/eax IA32_XSS UINTR state.
   17 	* cpuid.c: Added 0xd/n UINTR feature.
   18 	* cpuid.c: Added 0x19 key locker features.
   19 	* cpuid.c: Added 0x20 HRESET features.
   20 
   21 Mon Oct  5 2020 Todd Allen <todd.allen@etallen.com>
   22 	* cpuid.c: Added (7,5),(2,6) AMD Cato (synth) decoding based on
   23 	  instlatx64 example (possibly an engr sample).
   24 
   25 Sun Oct  4 2020 Todd Allen <todd.allen@etallen.com>
   26 	* cpuid.c: Corrected 6/edx size field to use minus-one notation.
   27 	* cpuid.c: Added 7/0/edx AMX flags.
   28 	* cpuid.c: Added 0xd XTILECFG & XTILEDATA features.
   29 	* cpuid.c: Added 0xd/1/eax XFD: extended feature disable supported flag.
   30 	* cpuid.c: Added 0xd/n/ecx XFD: faulting supported flag.
   31 	* cpuid.c: Added 0x18/0/edx: load-only TLB & store-only TLB encodings.
   32 	* cpuid.c: Added 0x1d leaf (Tile info) decoding.
   33 	* cpuid.c: Added 0x1e leaf (TMUL) decoding.
   34 	* cpuid.c: Added 0x1c leaf (architectural LBR) decoding.
   35 	* cpuid.c: Added 0xd LBR features.
   36 
   37 Sun Oct  4 2020 Todd Allen <todd.allen@etallen.com>
   38 	* cpuid.c: Added (synth) steppings for Comet Lake (0,6),(10,6) CPUs.
   39 	  For the first time in a long time, Intel actually provided this in
   40 	  the revision guide (615213)!
   41 	* cpuid.c: Corrected (synth) decoding for AMD (8,15),(2,0) Dali CPUs.
   42 	* cpuid.c: Added (synth) decoding for AMD Dali A1 stepping.
   43 	* cpuid.c: Added (synth) decoding for AMD Picasso A1 stepping.
   44 	* cpuid.c: Added (synth) decoding for AMD Renoir A1 stepping.
   45 
   46 Sat Oct  3 2020 Todd Allen <todd.allen@etallen.com>
   47 	* cpuid.c: Added 7/0/ecx PKS flag.
   48 	* cpuid.c: Added 7/0/edx SRBDS flag, from Linux kernel.
   49 	* cpuid.c: Added 7/0/edx LBR flag.
   50 	* cpuid.c: Added 0xd/0/eax IA322_XSS HWP state flag.
   51 	* cpuid.c: Added synth decoding for Rocket Lake.
   52 	* cpuid.c: Added synth decoding for Elkhart Lake B0.
   53 	* cpuid.c: Added synth decoding for Alder Lake [Golden Cove].
   54 	* cpuid.c: Clarified synth decoding for (0,6),(8,10) Lakefield.
   55 	* cpuid.c: Added KVM interrupt-based page-ready APF event flag.
   56 
   57 Sat Aug  8 2020 Todd Allen <todd.allen@etallen.com>
   58 	* cpuid.c: Corrected 0x20000001/edx header.
   59 	* cpuid.c: Detect bogus 0x20000000 leaf values and cap the maximum
   60 	  valid register for the 0x2xxxxxxx range to avoid absurdly long dumps
   61 	  on old CPUs.
   62 
   63 Mon Aug  3 2020 Todd Allen <todd.allen@etallen.com>
   64 	* cpuid.c: Added bzero before cpuid instruction, in case the cpuid
   65 	  instruction quietly fails.  This mostly is paranoia, but I don't see
   66 	  how this ever could cause harm.
   67 
   68 Mon Jun  8 2020 Todd Allen <todd.allen@etallen.com>
   69 	* cpuid.c: Added Tiger Lake-U B0 stepping, from coreboot.
   70 	* cpuid.c: Added AMD (8,15),(2,0) Picasso model synth & uarch decoding.
   71 
   72 Sun May 24 2020 Todd Allen <todd.allen@etallen.com>
   73 	* cpuid.c: Added Zhaoxin KX-6000 decoding that still claims the vendor
   74 	  CentaurHauls.  Later Zhaoxin CPUs were supposed to use their own
   75 	  vendor, but instlat64x showed an example that still used the old one.
   76 
   77 Sat May 16 2020 Todd Allen <todd.allen@etallen.com>
   78 	* cpuid.c: Added better (synth) decoding for Intel Comet Lake-H/S
   79 	  Core i*-10000 CPUs, based on instlatx64 example and listings in
   80 	  ark.intel.com.
   81 
   82 Tue Apr 28 2020 Todd Allen <todd.allen@etallen.com>
   83 	* cpuid.c: Added 0x8000000a/edx INVLPGB/TLBSYNC hypervisor intercept
   84 	  enable flag.
   85 
   86 Mon Apr 27 2020 Todd Allen <todd.allen@etallen.com>
   87 	* Made new release.
   88 
   89 Wed Apr 22 2020 Todd Allen <todd.allen@etallen.com>
   90 	* cpuid.c: Added synth decoding for AMD Steppe Eagle/Crowned Eagle
   91 	  (Puma 2014 G-Series), based on instlatx64 sample.
   92 
   93 Thu Apr 16 2020 Todd Allen <todd.allen@etallen.com>
   94 	* cpuid.c: Added 7/0/edx SERIALIZE & TSXLDTRK bit descriptions.
   95 	* cpuid.c: Added 0xf/1/eax Counter width & overflow flag.
   96 	* cpuid.c: Added 0x10/3/ecx per-thread MBA controls flag.
   97 	* cpuid.c: Added 0x8000001f fields.
   98 	* cpuid.man: Added AMD 24594 & 40332 docs.
   99 
  100 Tue Mar  3 2020 Todd Allen <todd.allen@etallen.com>
  101 	* cpuid.c: Corrected field lengths in 14/0 and 14/1 subleafs so that
  102 	  columns line up.
  103 
  104 Thu Feb 27 2020 Todd Allen <todd.allen@etallen.com>
  105 	* cpuid.c: Added CC150 (Coffee Lake R0) synth decoding, based on
  106 	  instlatx64 example.
  107 
  108 Wed Feb 26 2020 Todd Allen <todd.allen@etallen.com>
  109 	* cpuid.c: Added Jasper Lake A0 stepping (from Coreboot*).
  110 	* cpuid.c: Updated 1/ebx "cpu count" to modern terminology: "maximum
  111 	  addressible IDs for CPUs in pkg" to avoid user confusion.  It was a
  112 	  reliable count of the number of CPUs for only a split second some time
  113 	  around 2002.  Maybe.
  114 	* cpuid.c: Updated 4/eax CPU & core count terminology in the same way.
  115 
  116 Tue Feb 11 2020 Todd Allen <todd.allen@etallen.com>
  117 	* Made new release.
  118 
  119 Mon Feb 10 2020 Todd Allen <todd.allen@etallen.com>
  120 	* cpuid.c: Clarified Intel NNP-I (Spring Hill).
  121 	* cpuid.c: In decode_vendor(), report "Zhaoxin" even with VENDOR_VIA,
  122 	  if the brand string indicates so.
  123 	* cpuid.c: In 0xc0000004/ebx, make current voltage use the shift-4 + 700
  124 	  encoding used for other VIA voltages.
  125 
  126 Fri Feb  7 2020 Todd Allen <todd.allen@etallen.com>
  127 	* cpuid.man: Use both Intel doc numbers for 329671/600827.
  128 	* cpuid.man: Added missing 329901/600834 Intel doc.
  129 
  130 Thu Feb  6 2020 Todd Allen <todd.allen@etallen.com>
  131 	* cpuid.c: Added VIA 0xc0000004 leaf decoding.
  132 	* cpuid.c: Added X2_IMAGES special flag to pretty-print values in the
  133 	  2X encoding.
  134 	* cpuid.c: Added MINUS1_IMAGES special flag to pretty-print values with
  135 	  the "- 1" encoding.  (I finally got turned around about this being
  136 	  better than the older "raw" values.)
  137 
  138 Wed Feb  5 2020 Todd Allen <todd.allen@etallen.com>
  139 	* cpuid.c: Add VIA C7-D and Eden brands to (0,6),(0,10) (synth).
  140 	* cpuid.c: Differentiate VIA (0,6),(0,13) (synth) based on brand strings.
  141 	* cpuid.c: Overhaul of VIA 0xc0000002 leaf decoding.
  142 	* cpuid.c: Updated VIA Nano steppings (synth).
  143 	* cpuid.c: Removed extraneous WinChip & core words from C3 and later
  144 	  VIA CPUs (synth).
  145 
  146 Wed Feb  5 2020 Todd Allen <todd.allen@etallen.com>
  147 	* cpuid.c: Changed mp_synth fields to use '=' separator instead of ':',
  148 	  like every other value.
  149 	* cpuid.c: Changed processor serial number to use '=' separator instead
  150 	  of ':', like every other value.
  151 
  152 Tue Feb  4 2020 Todd Allen <todd.allen@etallen.com>
  153 	* cpuid.man: Added 336907 doc with 7/0/ecx/TME bit description.
  154 	* cpuid.c: Removed LX* comment from 7/0/ecx/TME bit description.  It's
  155 	  documented after all.
  156 
  157 Tue Feb  4 2020 Todd Allen <todd.allen@etallen.com>
  158 	* cpuid.c: Clarified (0,6),(10,6) Comet Lake-U (synth).
  159 
  160 Mon Feb  3 2020 Todd Allen <todd.allen@etallen.com>
  161 	* Made new release.
  162 
  163 Mon Feb  3 2020 Todd Allen <todd.allen@etallen.com>
  164 	* cpuid.c: Removed comments about (0,6),(8,14),10 contradiction.
  165 	  Coreboot* removed the incorrect code claiming it was Coffee Lake D0.
  166 	  The actual code already reflected this resolution.
  167 	* cpuid.c: Removed now-redundant lines from decode_uarch_intel() for
  168 	  the individual (0,6),(8,14) steppings.  They all say Kaby Lake now,
  169 	  so they aren't necessary.
  170 	* cpuid.c: Added (0,6),(4,14),8 Kaby Lake G0 and (0,6),(5,14),8
  171 	  Kaby Lake-H A0 steppings to both (synth) and (uarch synth) that I found
  172 	  in Coreboot*.  I realized I was worrying too much about them.  They are
  173 	  at least wholly distinct steppings, so they don't constitute the
  174 	  intra-stepping blurring that I saw with {Kaby,Amber,Whiskey,Comet}
  175 	  Lake.  They are more akin to the already-existing Cascade Lake &
  176 	  Cooper Lake steppings.  Perhaps those two new entries were just early
  177 	  engineering samples for Kaby Lake.
  178 	* cpuid.c: Added (0,6),(9,14),13 stepping to decode_uarch_intel.  The
  179 	  fallback without a stepping is weak, and it should be avoided for
  180 	  any actual known stepping.  (Added a comment too.)
  181 	* Makefile: Changed my own Todd's Development rules to build on very old
  182 	  systems, so that the executables will run at all on very old systems.
  183 	* Makefile: Changed -Wextra to -W.  That isn't recommended on modern
  184 	  gcc versions, but still works.  And it is necessary on really old
  185 	  gcc versions, because -Wextra produces a hard error.
  186 
  187 Sun Feb  2 2020 Todd Allen <todd.allen@etallen.com>
  188 	* Made new release.
  189 
  190 Sun Feb  2 2020 Todd Allen <todd.allen@etallen.com>
  191 	* Makefile, cpuid.proto.spec: Added FAMILY.NOTES to the list of files to
  192 	  be included in tarball & rpm doc directory.  That file still is messy,
  193 	  but I reference it a lot, so maybe it will be useful to others too.
  194 
  195 Sun Feb  2 2020 Todd Allen <todd.allen@etallen.com>
  196 	* cpuid.c: Added old (synth) models from sandpile.org: AMD Elan SC400,
  197 	  NSC Geode LX.
  198 	* cpuid.c: Added some old (synth) and (uarch synth) die process numbers
  199 	  from sandpile.org.
  200 	* cpuid.c: Added stepping values from sandpile.org.
  201 	* cpuid.c: sandpile.org calls (0,6),(4,6) "Crystalwell".  Arguably, that
  202 	  is just the name of the L4 cache.  But even Intel's ARK calls these
  203 	  CPUs "Crystal Well".  So I'm changing the name to "Crystal Well".  The
  204 	  uarch still is Haswell, so that should clarify any confusion.
  205 	* cpuid.c: sandpile.org calls (0,6),(4,7) "Brystalwell".  The situation
  206 	  is similar, but Intel does not use that name at all.  I'm not renaming
  207 	  these cores.
  208 
  209 Sun Feb  2 2020 Todd Allen <todd.allen@etallen.com>
  210 	* cpuid.c: Added leaf walking of the 0x20000000 (Intel Phi) range and
  211 	  decoding of a single bit in 0x20000001, based on information in
  212 	  sandpile.org.  I found only a vague hint about this in the Intel Xeon
  213 	  Phi Coprocessor System Developers Guide, but no details.
  214 	* cpuid.c: For the (0,11) family of Phi processors, placing them within
  215 	  a K1OM family.  The (0,6) Phi cores are just Airmont-derived, so left
  216 	  them alone.
  217 
  218 Sat Feb  1 2020 Todd Allen <todd.allen@etallen.com>
  219 	* cpuid.c: Reverted Cedar Trail back to Cedarview.  (Atom uArch name vs.
  220 	  Core name vs. Platform name vs. SoC name is very confusing.)
  221 
  222 Sat Feb  1 2020 Todd Allen <todd.allen@etallen.com>
  223 	* cpuid.c: Added Broadwell (0,6),(3,13) steppings based on Coreboot*.
  224 	* cpuid.c: Added Haswell (0,6),(3,12) steppings based on Coreboot*.
  225 	* cpuid.c: Added Haswell-ULT (0,6),(4,5),0 stepping based on Coreboot*.
  226 	* cpuid.c: Added some Skylake (0,6),(4,14) steppings based on Coreboot*.
  227 	* cpuid.c: Added some Skylake (0,6),(5,14) steppings based on Coreboot*.
  228 	* cpuid.c: Added Kaby Lake-H (0,6),(9,14),9 stepping based on Coreboot*.
  229 	* cpuid.c: Added Cannon Lake (0,6),(6,6) steppings based on Coreboot*.
  230 	* cpuid.c: Added Apollo Lake (0,6),(5,12) A0 stepping based on Coreboot*.
  231 	* cpuid.c: Added Gemini Lake (0,6),(7,10) A0 stepping, and corrected
  232 	  R0 stepping, based on Coreboot*.
  233 	* cpuid.c: Added Ice Lake-U/Y (0,6),(7,14) A0 stepping based on
  234 	  Coreboot*, and disregarding inconsistent info from spec update.
  235 	* cpuid.c: Added Tiger Lake (0,6),(8,12) A0 stepping based on Coreboot*.
  236 	* cpuid.c: Added Elkhart Lake (0,6),(9,6) A0 stepping based on Coreboot*.
  237 	* cpuid.c: Added Comet Lake (0,6),(10,6) steppings based on Coreboot*.
  238 	* cpuid.c: Added Comet Lake-H/S (0,6),(10,5) steppings based on
  239 	  Coreboot*.
  240 
  241 Sat Feb  1 2020 Todd Allen <todd.allen@etallen.com>
  242 	* cpuid.c: Added (uarch synth) decoding for (6,15),(0,0) Bulldozer,
  243 	  based on engineering sample.
  244 	* cpuid.c: Added (uarch synth) & (synth) (6,15),(6,0) Excavator Carrizo
  245 	  and Toronto, based on instlatx64 samples.
  246 	* cpuid.c: Added (uarch synth) decoding for (8,15),(0,0) Zen, based on
  247 	  engineering sample.
  248 	* cpuid.c: Added Zhaoxin (0,7),(1,15) based on example.
  249 	* cpuid.c: Differentiate Zhaoxin ZhangJiang from VIA Isaiah [C7] in
  250 	  (synth) and (uarch synth).  Sadly, this implies a need to use brand
  251 	  information for (uarch synth).
  252 	* cpuid.c: Addedd (synth) for VIA version of Zhaoxin ZhangJaing at
  253 	  (0,7),(0,11).
  254 	* cpuid.c: Added Westmere-EP A0 & B0 stepping (synth) based on instlatx64
  255 	  sample & wikipedia article.
  256 	* cpuid.c: Fixed bogus stepping in Centerton fallback (synth).
  257 	* cpuid.c: Added (0,6),(5,5),10 Cooper Lake (synth) & (uarch synth),
  258 	  based on Qemu.
  259 	* cpuid.c: Added "AMD PRO A" as a 2nd string to detect AMD A-Series.
  260 	* cpuid.c: Differentiate Raven Ridge from Great Horned Owl/
  261 	  Banded Kestrel (synth), based on "Embedded" string in brand.
  262 	* cpuid.c: Added Merlin Falcon as R-Series alternative everywhere
  263 	  G-Series Brown Falcon appears.
  264 	* cpuid.c: Added rules for EPYC Embedded to differentiate (synth) for
  265 	  Snowy Owl and Naples, based on EPYC 3000 series.  Untested, because I
  266 	  have no examples.
  267 
  268 Fri Jan 31 2020 Todd Allen <todd.allen@etallen.com>
  269 	* cpuid.man: Added instlatx64.atw.hu.
  270 	* cpuid.man: Added -l and -s options.
  271 
  272 Fri Jan 31 2020 Todd Allen <todd.allen@etallen.com>
  273 	* cpuid.c: Added rudimentary (10,15) (synth) for AMD Zen 3.
  274 
  275 Fri Jan 31 2020 Todd Allen <todd.allen@etallen.com>
  276 	* cpuid.man: Added linux kernel note about intel-family.h.
  277 	* cpuid.c: Added rudimentary Tremont (synth) & (uarch synth).
  278 	* cpuid.c: Added tentative Ice Lake NNPI (synth) & (uarch synth).
  279 	* cpuid.c: Added rudimentary (0,6),(10,6) Comet Lake [Coffee Lake]
  280 	  (synth) & (uarch synth).
  281 
  282 Fri Jan 31 2020 Todd Allen <todd.allen@etallen.com>
  283 	* cpuid.man: Added Intel Microcode Update Guidance document.
  284 	* cpuid.c: Removed br.generic check from dc (Core) query.  It was useful
  285 	  in the Yonah era, but has been problematic since.  Instead, add a dG
  286 	  (Generic) query and use that where needed for the Yonah CPUs.  And a
  287 	  few other users of dc now use dG.
  288 	* cpuid.c: Added (synth) for Apollo Lake D0 (collision with B0/B1?) & E0.
  289 	* cpuid.c: Generalized P4500 & U4500 (Arrandale/Clarkdale) (synth) names.
  290 	* cpuid.c: Added Broadwell-DE V3 (synth) alternate stepping.
  291 	* cpuid.c: Added Broadwell H 43e (synth).
  292 	* cpuid.c: Added Pentium 3700U / 3800U (synth).
  293 	* cpuid.c: Added Apollo Lake (Broxton) (synth).
  294 	* cpuid.c: Added Atom x5-E8000 (synth).
  295 	* cpuid.c: Added Pentium G6900 (Clarkdale K0) (synth).
  296 	* cpuid.c: Added Core i*-900 (Clarksfield) (query dc) (synth).
  297 	* cpuid.c: Added E5-4600 (Ivy Bridge) (synth) names.
  298 	* cpuid.c: Prefixed E to Jasper Forest Xeon (synth) names.
  299 	* cpuid.c: Added Xeon E3-1200 (Kaby Lake) (synth) specific line.
  300 	* cpuid.c: Added Xeon 6500 names to Beckon (synth).
  301 	* cpuid.c: Generalized Pentium 900 (Sandy Bridge) (synth) names.
  302 	* cpuid.c: Added Celeron T3000 / 900 / SU2300 (Wolfdale) (synth) names.
  303 	* cpuid.c: Added Pentium T4000 (Wolfdale) (synth) names.
  304 	* cpuid.c: Added Celeron M ULV 700 (Penryn) (synth).
  305 	* cpuid.c: Correct query to dc for Sandy Bridge-E Core (synth).
  306 	* cpuid.c: Added Pentium 1405 (Sandy Bridge-E) (synth).
  307 	* cpuid.c: Added Xeon D-2100 (Skylake stepping 4) (synth) names.
  308 	* cpuid.c: Added Core i9-7000X (Skylake-X) (synth).
  309 	* cpuid.c: Changed case of x for SoFIA (synth).
  310 	* cpuid.c: Simplified Westmere-EP Xeon (synth) names.
  311 	* cpuid.c: Added Atom x*-A3900 (Apollo Lake) (synth) names.
  312 	* cpuid.c: Added Rangeley core name to Atom C2000 (synth) names.
  313 	* cpuid.c: Clarified that all (0,6),(4,15) CPUs are Broadwell-{E,EX}
  314 	  in (synth) lines.
  315 	* cpuid.c: Clarified that (0,6),(3,13) is Broadwell-U.
  316 	* cpuid.c: For (0,6),(4,6) (synth), MRG* 2018-08-31 shows stepping 1,
  317 	  so that must be the only known stepping: G0.
  318 	* cpuid.c: Corrected Broadwell-Y Core M (synth).
  319 	* cpuid.c: Added (0,6),(9,14),11 Coffee Lake Pentium & Celeron (synth).
  320 	* cpuid.c: Corrected (0,6),(9,14),11 fallback (synth).
  321 	* cpuid.c: Clarified transition from i*-8000 to i*-9000 at
  322 	  (0,6),(9,14),12 stepping in (synth) lines.
  323 	* cpuid.c: Added Puma 7 (synth).
  324 	* cpuid.c: Generalized Pentium B900C (Ivy Bridge) (synth).
  325 	* cpuid.c: Added Celeron G2000 (Haswell) (synth).
  326 	* cpuid.c: Clarified Haswell-E (synth).
  327 	* cpuid.c: Aded -4000 series to (0,6),(4,6) Core (synth) names.
  328 	* cpuid.c: Added (0,6),(3,14) Ivy Bridge Celeron (synth).
  329 	* cpuid.c: Corrected (0,6),(3,14) Cores as Ivy Bridge-E (synth).
  330 	* cpuid.c: Differentiate i*-8700 and i*-7700 Kaby Lake (synth).
  331 	* cpuid.c: Added (0,6),(8,14),9 Kaby Lake Pentium & Celeron (synth).
  332 	* cpuid.c: Differentiate (0,6),(8,14),9 Kaby Lake-Y and Amber Lake-Y
  333 	  (synth) with test for -8000 Series in brand name, because there seems
  334 	  to be no other way to tell.
  335 	* cpuid.c: Added XMM 7272 (SoFIA) (synth).
  336 	* cpuid.c: Added Coffee Lake R0 Xeon (synth).
  337 	* cpuid.c: Added Whiskey Lake W0 Pentium & Celeron (synth).
  338 	* cpuid.c: Correct (8,14) (uarch synth) to just Kaby Lake once all
  339 	  instances of Coffee lake had been eliminated from that family.  The
  340 	  (9,14) family continues to include both Kaby Lake & Coffee Lake.
  341 
  342 Fri Jan 31 2020 Todd Allen <todd.allen@etallen.com>
  343 	* cpuid.man: Added Intel 600827 spec update.
  344 	* cpuid.c: Generalized Bay Trail-M/D (synth) names and expanded them.
  345 	* cpuid.c: Added Bay Trail-M/D D0/D1 (synth).
  346 
  347 Thu Jan 30 2020 Todd Allen <todd.allen@etallen.com>
  348 	* cpuid.c: Added VIA die processes for as many uarchs/cores as I could
  349 	  find.
  350 
  351 Wed Jan 29 2020 Todd Allen <todd.allen@etallen.com>
  352 	* cpuid.c: Added comments about various Intel spec updates.
  353 	* cpuid.man: Removed extra "315593" garbage line.
  354 	* cpuid.c: Added (synth) for Broadwell-E R0 stepping.
  355 	* cpuid.c: Added stepping number for Apollo Lake B0/B1.
  356 	* cpuid.c: Differentiate (synth) between Core & Xeon (0,6),(3,15)
  357 	  Haswell.
  358 	* cpuid.c: Differentiate (synth) between Core & Xeon (0,6),(2,12)
  359 	  Westmere/Gulftown.
  360 	* cpuid.c: Simplified more (synth) i*-*000 combinations.
  361 	* cpuid.c: Removed duplicate slash in one Haswell (synth) line.
  362 	* cpuid.c: Correct Itanium Merced model/stepping confusion.
  363 	* cpuid.c: Added KX-5000 & KH-20000 to Zhaoxin WuDaoKou (synth).
  364 	* cpuid.c: Added die proess to Zhaoxin WuDaoKou (uarch synth).
  365 	* cpuid.c: Added Zhaoxin LuJiaZiu (0,7),(3,11) model (synth) &
  366 	  (uarch synth).
  367 
  368 Tue Jan 28 2020 Todd Allen <todd.allen@etallen.com>
  369 	* cpuid.c: Differentiate (synth) between Bay Trail Pentiums, Celerons
  370 	  & Atoms.
  371 	* cpuid.c: Differentiate (synth) between Braswell Pentiums & Celerons.
  372 	* cpuid.c: Corrected (synth) steppings for Braswell.
  373 	* cpuid.c: Add J3000 series to (synth) for Braswell.
  374 	* cpuid.c: Remove Pentium & Celeron items from {Kaby,Coffee,Comet} Lake
  375 	  Core (synth).  I'd already created separate items for those, but
  376 	  missed removing the names from the Core-specific line.
  377 
  378 Mon Jan 27 2020 Todd Allen <todd.allen@etallen.com>
  379 	* Made new release.
  380 
  381 Mon Jan 27 2020 Todd Allen <todd.allen@etallen.com>
  382 	* cpuid.c: Changed 0x8000001e/ecx to display nodes per processor in N-1
  383 	  notation, after receiving confirmation from AMD that this is correct.
  384 
  385 Sat Jan 25 2020 Todd Allen <todd.allen@etallen.com>
  386 	* cpuid.c: Fixed spelling of (size synth).  I meant to always have
  387 	  "synth" at the end of synthesized fields, and had that one flipped
  388 	  around.
  389 	* cpuid.c: Clarified AVX512_VNNI: neural network instructions.
  390 	* cpuid.c: Clarified AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND.
  391 	* cpuid.c: Clarified AVX512_BF16: bfloat16 is a data format, not an
  392 	  instruction.
  393 	* cpuid.c: Added 7/0/edx md-clear feature, found from Xen & Qemu
  394 	  hypervisors.
  395 	* cpuid.c: Added 0x80000008/ebx ppin feature, found from Xen hypervisor.
  396 	* cpuid.c: Added 0x40000001/eax (KVM) flags.
  397 	* cpuid.c: Got rid of the Transmeta 0x80860001/eax family description,
  398 	  which I missed when I got rid of all 1/eax families.  It wasn't so
  399 	  egregious, but it wasn't very valuable either.  The Transmeta Crusoe
  400 	  name already was in the (synth) leaf.
  401 	* cpuid.c: Wrote a version of bits_needed() that uses __builtin_clz
  402 	  with gcc 3.4 and later.
  403 	* cpuid.c: Fixed bug with old asm-based bits_needed() function when the
  404 	  input value was 0.
  405 
  406 Sat Jan 25 2020 Todd Allen <todd.allen@etallen.com>
  407 	* cpuid.c: Further clarified descriptions in 0x8000001f leaf, based on
  408 	  text in AMD64 Architecture Programmer's Manual, Vol 3, 3.28.  I had
  409 	  missed these new fields in my earlier pass through the manual.
  410 	* cpuid.c: Added comments for more undocumented fields, noting where
  411 	  the information came from, particularly SKC*, LX*, and sandpile.org.
  412 	* cpuid.c: Changed case of new descriptions.
  413 	* cpuid.c: Created Synth_Family() & Synth_Model() macros based on
  414 	  print_1_eax & SKC's AMD_Family() macro.
  415 	* cpuid.c: Added (family synth) and (model synth) to 0x80000001/eax,
  416 	  (AMD and Hygon variants), just like for 1/eax.
  417 	* cpuid.c: Added Castle Peak B0 stepping (synth), now that I know the
  418 	  stepping name.
  419 	* cpuid.c: Changed 0x80000008/ebx "RDPRU instruction" field.
  420 	* cpuid.c: Clarified 0x80000020 leaf descriptions based on AMD 55803 PPR.
  421 	* cpuid.c: Modified print_apic_synth's bit width computations to reflect
  422 	  change in terminology (core => thread, CU => core) in AMD Family 17h.
  423 	* cpuid.man: Updated 54945 PPR name, using newer doc from
  424 	  developer.amd.com.
  425 	* cpuid.man: Added 55803 PPR, found by URL provided by AMD.
  426 	* cpuid.man: Updated sandpile.org URL.
  427 
  428 Sat Jan 25 2020 Todd Allen <todd.allen@etallen.com>
  429 	* cpuid.c: Selectively applied changes from Smita Koralahalli
  430 	  Channabasappa's patch: "Add PQoS feature to CPUID utility and display
  431 	  subleaf 1 for leaf 0x80000020 in the raw CPUID data."
  432 	* cpuid.c: Renamed fields which no longer are Intel-specific:
  433 	  RDT-CMT/PQoS cache monitoring and RDT-CAT/PQE cache allocation.
  434 
  435 Fri Jan 24 2020 Todd Allen <todd.allen@etallen.com>
  436 	* cpuid.c: Shortened 0x8000001f leaf descriptions to <= 40 chars.
  437 
  438 Fri Jan 24 2020 Smita Koralahalli Channabasappa <Smita.KoralahalliChannabasappa@amd.com>
  439 	* cpuid.c: Add AMD Secure Encryption feature bits to CPUID utility.
  440 	* cpuid.c: Update CPUID utility with additional AMD specific features.
  441 	* cpuid.c: Handle naming issues of cores->threads at register
  442 	  80000008_ecx and compute unit->core at register 8000001e_ebx for
  443 	  families greater than 16h.  Retains previously assigned names if
  444 	  families are lesser than or equal to 16h.  Family values are
  445 	  determined by adding family number and extended family
  446 	  number(80000001_eax[8:11] + 80000001_eax[20:27]) as described in PPR
  447 	  under CPUID_Fn00000001_eax.
  448 
  449 Wed Jan 22 2020 Todd Allen <todd.allen@etallen.com>
  450 	* Made new release.
  451 
  452 Wed Jan 22 2020 Todd Allen <todd.allen@etallen.com>
  453 	* cpuid.c: In print_80000001_ebx_amd, removed two checks for
  454 	  __M(val_1_eax) >= _XM(0) + _M(0).  Yes, gcc, I know that "comparison
  455 	  of unsigned expression >= 0 is always true", and I also know even a
  456 	  half-assed optimizer will get rid of it, so I preferred clarity.  But
  457 	  people freak out if the compiler emits any warnings, no matter what
  458 	  crazy -W options the've chosen.  So I'm removing them.
  459 	* cpuid.c: Changed a bunch of ccstring return types to cstring.  The
  460 	  extra const in ccstring was meaningless for return types, but it
  461 	  caused a ton of additional -Wignored-qualifiers warnings.  No grousing
  462 	  about those warnings; they seem legit.
  463 	* Makefile: Added -Wextra, so I'll see these before people complain
  464 	  about them in the future.
  465 
  466 Tue Jan 21 2020 Todd Allen <todd.allen@etallen.com>
  467 	* cpuid.c: Changed Cannon Lake to Palm Cove when talking about uarch.
  468 	* cpuid.c: Added extra (0,6),(8,14),12 (unknown type) fallback.
  469 	* cpuid.c: Fixed (0,6),(8,14) Whiskey Lake typo.
  470 	* cpuid.c: Added i*-9000 names to (0,6),(9,14) Coffee Lake CPUs.
  471 
  472 Mon Jan 20 2020 Todd Allen <todd.allen@etallen.com>
  473 	* Made new release.
  474 
  475 Sun Jan 19 2020 Todd Allen <todd.allen@etallen.com>
  476 	* cpuid.c: Fixed (synth) decoding of Kaby Lake vs. Coffee Lake (and
  477 	  their myriad "optimizations").
  478 	* cpuid.c: Correctly (synth) decoding of Comet Lake, which was wildly
  479 	  wrong.
  480 	* cpuid.c: Treating Whiskey Lake, Amber Lake, and Comet Lake as distinct
  481 	  uarchs just causes absurd "Coffee Lake / Whiskey Lake / Amber Lake /
  482 	  Comet Lake" uarch strings.  Instead, call all of them Coffee Lake, but
  483 	  turn off the core_is_uarch flag.  This ends up treating the other 3 as
  484 	  core names within the Coffee Lake uarch, which seems clearer.
  485 	* cpuid.c: Renamed Ice Lake to Sunny Cove when talking about uarch.
  486 	* cpuid.c: Renamed Tiger Lake to Willow Cove when talking about uarch.
  487 	* cpuid.c: Added (synth) differentiation between Whiskey Lake (U line)
  488 	  & and Amber Lake (Y line).
  489 	* cpuid.c: Added (synth) differentiation between Whiskey Lake (8000
  490 	  Series) and Comet Lake (10000 Series).
  491 	* cpuid.c: Separated (synth) for Goldmont Plus into Pentium & Celeron.
  492 	* cpuid.c: Fixed Moorefield (synth) to say Z3500 instead of Z3400.
  493 	* cpuid.c: Fixed (0,6),(5,5),7 to Cascade Lake-X.  Core names should be
  494 	  as specific as possible (in contrast to uarch names).
  495 	* cpuid.c: added (0,6),(2,7) Atom Z2000 Medfield (synth) based on
  496 	  example found on instlatx64.
  497 	* cpuid.c: Renamed Cedarview (SoC name) to Cedar Trail (core name).
  498 	* cpuid.c: Added (0,6),(1,15) Havendale/Auburndale (synth).
  499 	* cpuid.c: Added VIA (0,6),(0,15) Esther C5J (synth).
  500 	* cpuid.c: Added VIA Nano steppings to (synth).
  501 	* cpuid.c: Added AMD Ryzen vs. EPYC (synth) differentiation to
  502 	  Castle Peak / Rome.
  503 	* cpuid.c: Separated Mullins into Mullins (tablets) and Beema (desktop).
  504 	* cpuid.c: Separated Kabini into Kabini (desktop) and Kyoto (servers).
  505 	  Also added Temash for A-Series, although they're all mixed up with
  506 	  Kabini.
  507 	* cpuid.c: Added AMD (6,15),(3,8) Godavari (synth) decoding.
  508 	* cpuid.c: Added AMD (2,15),(0,3) Griffin (synth) decodings.
  509 	* cpuid.c: Removed duplicate junk code for AMD (1,15),(0,2) which
  510 	  prevented the 3 and 10 steppings from being used.
  511 	* cpuid.c: Corrected some AMD (0,6),(0,8) Duron Applebred (synth) names.
  512 	* cpuid.c: Added AMD DG02SRTBP4MFA based on example found on instlatx64.
  513 
  514 Fri Jan 17 2020 Todd Allen <todd.allen@etallen.com>
  515 	* cpuid.c: Merged 0xb and 0x1f leaf code, much like what Len Brown of
  516 	  Intel suggested a year ago.  I don't know why I didn't just do that in
  517 	  the first place.  Merged field names look more like the 0x1f names,
  518 	  because I thought they were clearer.
  519 	* cpuid.c: Removed type descriptions from "--- level ---" sub-headers.
  520 	  Intel docs clarify the levels and types are not related.
  521 	* cpuid.c: Got rid of the ridiculously overloaded 1/eax family
  522 	  descriptions.  That information is nearly useless in isolation and
  523 	  described much better in the new (uarch synth) field.
  524 	* cpuid.c: Also got rid of 0x80000001/eax family descriptions.  It
  525 	  wasn't nearly as bad, but still better to use the (uarch synth) field.
  526 	* cpuid.c: Because I removed that family information, also updated the
  527 	  decode_uarch* functions with information about older CPU makers'
  528 	  information.
  529 	* cpuid.c: Added vendor name to (uarch synth).
  530 	* cpuid.c: Fixed 4 and 0x8000001d leaf descriptions to say that the
  531 	  values are in "minus 1" notation.  Steven Noonan hinted that there was
  532 	  something to check here, and there was.
  533 	* cpuid.c: Added (synth size) field to the 4 and 0x8000001d leaves to
  534 	  compute the cache size, also based on a hint from Steven Noonan.
  535 	* cpuid.c: Added preliminary Zhaoxin decoding based on limited
  536 	  information I could find.
  537 	* cpuid.c: Added missing uarch names to decode_uarch_intel().
  538 	* cpuid.c: Added note about P5 Tillamook CPUs.
  539 	* cpuid.c: Added some more die process values.
  540 
  541 Thu Jan 16 2020 Todd Allen <todd.allen@etallen.com>
  542 	* Made new release.
  543 
  544 Thu Jan 16 2020 Todd Allen <todd.allen@etallen.com>
  545 	* cpuid.c: Added decode_uarch*() and moved the uarch suffixes there from
  546 	  print_synth*().  print_synth_intel() and print_synth_amd() now call
  547 	  that function to get the suffixes.
  548 	* cpuid.c: Added print_uarch_synth() to display just those suffixes.
  549 	* cpuid.c: Added (synth) decoding for Itanium Poulson & Kittson.
  550 	* cpuid.c: Correct (synth) decoding for Itanium Montecito, Millington,
  551 	  Montvale, Tukwila.
  552 	* cpuid.c: Cleaned up AMD [Excavator] core names.
  553 	* cpuid.man: Added some missing Intel spec updates.
  554 
  555 Wed Jan 15 2020 Todd Allen <todd.allen@etallen.com>
  556 	* cpuid.c: Added "(family synth)" and "(model synth)" to do the combined
  557 	  values used by the linux kernel and AMD.  That is:
  558 	     Family = XF + F
  559 	     Model  = (XM << 4) + M
  560 	* cpuid.c: Hunt down the fallback (synth) decodings that just list tons
  561 	  of different possible meanings, all copied from the more specific
  562 	  lines above them.  They almost always are wrong; if they were right,
  563 	  the more specific tests would've detected them.  So, they're pure
  564 	  guesswork.  Replace them with "(unknown type)", which is more honest.
  565 	* cpuid.c: Simplified Intel Xeon Scalable descriptions.
  566 	* cpuid.c: Eliminated reiteration of i3-XXXX, i5-XXXX, i7-XXXX CPUs,
  567 	  using i*-XXXX instead.
  568 	* cpuid.c: Added (synth) decoding for Core i*-4000U seen in the wild.
  569 	* cpuid.c: Correct missing = symbol in 0x80000001/eax transmeta leaf.
  570 	* cpuid.c: Added [K6], [K7], [K8] (synth) clarifications for AMD K8 CPUs.
  571 	* cpuid.c: Added (6,15),(6,5) (synth) based on sample from Alexandros
  572 	  Couloumbis.
  573 	* cpuid.c: Added AMD "*-Series" queries for the various latters and
  574 	  (synth) rules to use them.  Added more rules for AMD architectures
  575 	  that used this nomenclature.
  576 	* cpuid.c: Changed dO query to sO.
  577 
  578 Wed Jan 15 2020 Todd Allen <todd.allen@etallen.com>
  579 	* cpuid.c: Clarified (synth) for each microarchitecture to include
  580 	  process-neutral microarchitecture names too:
  581 	  {P6}           = (Pentium Pro, Klamath, Deschutes, Katmai, Coppermine,
  582 	                    Tualatin, Mendocino, Cascades)
  583 	  {Netburst}     = [Willamette, Northwood, Prescott, Cedar Mill]
  584 	  {P6 Pentium M} = (Banias), [Dothan, Yonah]
  585 	  {Core}         = [Merom, Penryn]
  586 	  {Nehalem}      = [Nehalem, Westmere]
  587 	  {Sandy Bridge} = (Sandy Bridge, Ivy Bridge)
  588 	  {Haswell}      = (Haswell, Broadwell)
  589 	  {Skylake}      = (Skylake, Kaby Lake, Coffee Lake, Whiskey Lake,
  590 	                    Amber Lake, Cascade Lake, Comet Lake, Cooper Lake,
  591 	                    Cannon Lake)
  592 	  {Sunny Cove}   = (Ice Lake, Tiger Lake)
  593 	  The similarities are hazy in places.  But this seems useful to help
  594 	  people who, for example, don't know "Cedar Mill", but do know
  595 	  "Netburst".  Also the number of Skylake-related architecture names
  596 	  exploded, and not all "Lake" names belong to Skylake, so this helps to
  597 	  clarify.
  598 	* cpuid.c: Corrected (synth) for Tolapai to 90nm process.
  599 
  600 Tue Jan 14 2020 Todd Allen <todd.allen@etallen.com>
  601 	* cpuid.c: Clarified Arrandale & Clarkdale as [Westmere].
  602 	* cpuid.c: Clarified Bloomfield, Gainestown & Beckton as [Nehalem].
  603 	* cpuid.c: Added [Merom] clarification to a couple CPUs that missed it.
  604 	* cpuid.c: Added [Cedar Mill] clarification to a couple CPUs that missed
  605 	  it.
  606 	* cpuid.c: Clarified Dothan, Stealey, Crofton & Tolopai as [Dothan].
  607 	* cpuid.c: Clarified Yonah, Sossaman as [Yonah].
  608 	* cpuid.c: Did not clarify Banias as [Banias] because it appears there
  609 	  are no non-Banias chips based on it.
  610 	* cpuid.man: Added handy wiki pages about microarchitectures.
  611 
  612 Mon Jan 13 2020 Todd Allen <todd.allen@etallen.com>
  613 	* cpuid.c: Added 6/eax HW_FEEDBACK flag.
  614 	* cpuid.c: Added 7/0/ecx ENQCMD flag.
  615 	* cpuid.c: Added 7/0/edx AVX512_VP2INTERSECT flag.
  616 	* cpuid.c: Added 7/1/eax AVX512_BF16 flag.
  617 	* cpuid.c: Added 0xd/0/eax flags for CET_U & CET_S state.
  618 	* cpuid.c: Added 0x80000008/ebx WBNOINVD flag.
  619 	* cpuid.c: Added 0x80000008/ebx SSBD flags from AMD white paper.
  620 	* cpuid.c: In 7/0/edx leaf, clarified PCONFIG as an instruction.
  621 	* cpuid.c: Added synth detection for Cyrix MediaGX (circa 1997 SoC).
  622 	* cpuid.c: Added 7/0/ecx TME flag, discovered in the linux-5.5-rc6
  623 	  kernel source.
  624 	* cpuid.c: Added 0x80000008/ebx additional STIBP always on flag,
  625 	  discovered in the linux-5.5-rc6 kernel source.
  626 	* cpuid.man: Added AMD SSBD white paper.
  627 	* cpuid.man: Added linux kernel note and clue on what to look for.
  628 
  629 Sun Jan 12 2020 Todd Allen <todd.allen@etallen.com>
  630 	* cpuid.c: Added Matisse B0 stepping based on sample from Steven Noonan.
  631 	* cpuid.c: Removed redundant dR lines from Pinnacle Ridge.  (They could
  632 	  come back if I see an EPYC based on Pinnacle Ridge, but they're
  633 	  redundant now.)
  634 
  635 Sun Jan 12 2020 Todd Allen <todd.allen@etallen.com>
  636 	* Made new release.
  637 
  638 Sun Jan 12 2020 Todd Allen <todd.allen@etallen.com>
  639 	* Makefile, cpuid.proto.spec: Added INSTALL_STRIP to allow disabling the
  640 	  install -s option.  This makes rpmbuild & find-debuginfo.sh happy,
  641 	  because they can find the cpuid debug information and create the
  642 	  cpuid-debuginfo rpm.
  643 	* Makefile: Updated release target to move debugsource rpms too.
  644 
  645 Sun Jan 12 2020 Todd Allen <todd.allen@etallen.com>
  646 	* cpuid.c: Added 0x40000004 leaf for Xen hypervisor.
  647 	* cpuid.c: Added 0x40000005 leaf for Xen hypervisor.
  648 	* cpuid.c: Fixed errors with static ccstring arrays that were not large
  649 	  enough to hold NULLs for all reserved bit field values.
  650 	* cpuid.c: Added AMD's CMT "compute unit" concept to print_apic_synth
  651 	  by adding that architectural level above the "cores" level, which
  652 	  relects AMD's portrayal.  This level is displayed only if it is
  653 	  present.
  654 	* cpuid.c: Added some undocumented synth decodings found on
  655 	  https://en.wikichip.org/wiki/amd/cpuid.  Not everything there makes
  656 	  sense, so I didn't take everything.  Marked with comments.
  657 	* cpuid.c: Added architecture tags to Intel synth decodings:
  658 	  [Willamette], [Northwood], [Prescott], [Merom], [Penryn], [Nehalem],
  659 	  [Westmere].  After that, Intel dropped the hyper-specific code names
  660 	  in favor of suffix letters.
  661 	* cpuid.c: Added architecture tags to Intel synth decodings: [Bonnell],
  662 	  [Saltwell], [Silvermont], [Airmont], [Goldmont], [Goldmont Plus].
  663 	  Intel continues to use hyper-specific names for Atom CPUs.
  664 
  665 Sat Jan 11 2020 Todd Allen <todd.allen@etallen.com>
  666 	* Makefile: Added -Wimplicit-fallthrough -Wunused-parameter options.
  667 	* cpuid.c: Clarified 4/edx WBINV/INVD flag.
  668 	* cpuid.c: Added new 7/edx flags, especially including new features to
  669 	  mitigate speculative execution exploits.
  670 	* cpuid.c: Cleaned up output of 0x10 subleaves.
  671 	* cpuid.c: Added 0x12/0/ebx CPINFO for #CP exceptions in enclave.
  672 	* cpuid.c: Properly display 0x18 sub-leaf number.
  673 	* cpuid.c: Added leaf 0x1f V2 Topology logic to decode_mp_synth() and
  674 	  print_apic_synth().  I have no physical examples, so I only could test
  675 	  with artificial input files.
  676 	* cpuid.c: Added 3-way and 6-way associativity to 0x80000006 and
  677 	  0x80000019 leaves.
  678 	* cpuid.c: Fixed incorrect fallthrough in switch for "41322 3.74:
  679 	  table 16".
  680 	* cpuid.c: Fixed incorrect fallthrough's in switch for Family 12h tables.
  681 	* cpuid.c: Added UNUSED macro to make newer gcc's shut up about unused
  682 	  formals.  (They have one complaint if the name is omitted, and another
  683 	  complaint if it's specified but unused.  There's just no pleasing gcc.)
  684 	* cpuid.c: Added break after usage() to make gcc shut up about a
  685 	  nonexistent fallthrough (even though it was marked with NOTREACHED).
  686 	* cpuid.c: Added missing newlines to all the print_2_byte Cyrix/VIA
  687 	  special cases.
  688 	* cpuid.c: Fixed print_f_0_edx: QoS monitoring was in 0xf/0 bit 1, not
  689 	  bit 0.
  690 	* cpuid.c: Added print_40000001_edx_kvm and appropriate call.
  691 	* cpuid.c: For 0x80000001/ebx amd, display PkgType for all family 16h
  692 	  or higher systems, even if no specific BrandId breakdown is known.
  693 	  Added encodings from AMD BKDG and PPR documents.
  694 
  695 Sat Jan 11 2020 Todd Allen <todd.allen@etallen.com>
  696 	* cpuid.c: Added proper synth decoding for Atom C3000 (Denverton).
  697 	* cpuid.c: Clarified Goldmont into eithe Apollo Lake or Denverton.
  698 	* cpuid.c: Corrected (0,6),(9,14) synth decoding to be Coffee Lake.
  699 	* cpuid.c: Added (0,6),(9,14) Coffee Lake synth decoding steppings.
  700 	* cpuid.c: Added (0,6),(9,14) Coffee Lake synth decoding for Xeon E-2100
  701 	  & E-2200.
  702 	* cpuid.c: Added (0,6),(5,5),7 synth decoding for Xeon 2nd Gen Scalable.
  703 	* cpuid.c: Added (0,6),(5,5),7 synth decoding for Xeon D-2100.
  704 	* cpuid.c: Added synth decoding for Gemini Lake R0 stepping (same as B0).
  705 	* cpuid.c: Added vague synth decoding for (0,6),(6,6) Cannon Lake.
  706 	* cpuid.c: Added vague synth decoding for (0,6),(6,10) Ice Lake.
  707 	* cpuid.c: Added vague synth decoding for (0,6),(6,12) Ice Lake.
  708 	* cpuid.c: Added vague synth decoding for (0,6),(7,13) Ice Lake.
  709 	* cpuid.c: Added additional synth decodings for AMD Ryzen, including
  710 	  Pinnacle Ridge.
  711 	* cpuid.c: Differentiate Ryzen from EPYC using brand string and new
  712 	  query functions.
  713 	* cpuid.man: Added new spec updates, revision guides, etc.
  714 
  715 Sat Jan 11 2020 Todd Allen <todd.allen@etallen.com>
  716 	* Prettification of Masanori Misono's 0x40000001/eax KVM fields.
  717 	* Formatting changes & URL removal from Jeffrey Walton's SunOS patch.
  718 	* Prettification of Thomas Friebel's 0x40000003 leaf fix: while loop.
  719 	* Reverted print_header() to use !raw (personal preference of mine).
  720 	* Format changes to & rearrangement of fanjinke's Hygon patch.
  721 
  722 Fri Jan  3 2020 Thomas Friebel <friebelt@amazon.de>
  723 	* Fixed bug that skipped half the subleaves in the 0x40000003 hypervisor
  724 	  leaf.
  725 	* Fixed contradictory try logic in print_header() for leaf 0x40000003.
  726 	* Fixed to use 0x40000003/ebx for high 32 bits of vtsc_offset,
  727 	  instead of using eax for both high & low 32 bits.
  728 
  729 Mon May 13 2019 fanjinke <fanjinke@hygon.cn>
  730 	* Added Hygon support.
  731 
  732 Wed May  8 2019 Jeffrey Walton <noloader@gmail.com>
  733 	* cpuid.c: Added support for SunOS build.
  734 
  735 Sat Mar  2 2019 Masanori Misonoc <m.misono760@gmail.com>
  736 	* cpuid.c: Added 0x40000001/eax KVM bit fields.
  737 
  738 Fri Jun  1 2018 Tony Luck <tony.luck@intel.com>
  739 	* cpuid.c: Added decoding of 0x10/3 subleaf.
  740 
  741 Sat May 26 2018 Todd Allen <todd.allen@etallen.com>
  742 	* cpuid.c: Fixed 7/ecx spelling error: intruction.
  743 	* cpuid.c: Fixed main spelling error: unrecogized.
  744 
  745 Sat May 19 2018 Todd Allen <todd.allen@etallen.com>
  746 	* Made new release.
  747 
  748 Sat May 19 2018 Todd Allen <todd.allen@etallen.com>
  749 	* cpuid.c: Added some more fields reported by Stefan Kanthak, after
  750 	  tracking down some documentation that explains them:
  751 	* cpuid.c: Added 7/ecx bit 7: CET_SS and 7/edx bit 20: CET_IBT fields.
  752 	  So far, the only documentation for these is Control-flow Enforcement
  753 	  Technology Preview (334525), section 8.2 Feature Enumeration.
  754 	* cpuid.c: Added 7/ecx bit 16: 5-level paging.  So far, the only
  755 	  documentation for this is 5-Level Paging and 5-Level EPT White Paper
  756 	  (335252).
  757 	* cpuid.c: Improved 14/0/ecx descriptions.
  758 	* cpuid.c: Added hypervisor leaf descriptions from Microsoft's
  759 	  Hypervisor Top Level Functional Specification (Released Version 5.0b).
  760 	* cpuid.man: Added the above mentioned docs.
  761 
  762 Thu May 17 2018 Todd Allen <todd.allen@etallen.com>
  763 	* cpuid.c: Added CPUID features documented in PPR for AMD Family 17h
  764 	  Model 01h B1 (54945 Rev 1.14):
  765 	* cpuid.c: Added PCOMMIT to 7/ebx: PCOMMIT instruction (a deprecated
  766 	  instruction).
  767 	* cpuid.c: Added bits to 80000001/ecx (amd).
  768 	* cpuid.c: Added 80000007/ebx.
  769 	* cpuid.c: Added 80000007/ecx.
  770 	* cpuid.c: Added bits to 80000007/edx.
  771 	* cpuid.c: Added 80000008/ebx.
  772 	* cpuid.c: Added bits to 8000000a/edx.
  773 	* cpuid.c: Added bits to 8000001a/eax.
  774 	* cpuid.c: Added bits to 8000001b/eax.
  775 	* cpuid.c: Added tentative 8000001f descriptions.  Information obtained
  776 	  from Linux kernel 4.17-rc5 arch/x86/kernel/cpu/scattered.c (as patched
  777 	  by Tom Lendacky of AMD on 18-Apr-2017 via LKML), and from Secure
  778 	  Encrypted Virtualization API Version 0.16 Technical Preview
  779 	  (55766 Rev 3.06).
  780 	* cpuid.man: Added 54945 & 55766 docs.
  781 
  782 Thu Apr 19 2018 Todd Allen <todd.allen@etallen.com>
  783 	* Made new release.
  784 
  785 Wed Apr 19 2018 Todd Allen <todd.allen@etallen.com>
  786 	* cpuid.c: Fixed various bugs reported by Stefan Kanthak:
  787 	* cpuid.c: Fixed bug in print_2_meaning: 0x49 normal & special cases.
  788 	* cpuid.c: Fixed bug in print_2_meaning: 0x63 additional 2M/4M, 4-way,
  789 	  32 entries item.
  790 	* cpuid.c: Collapsed print_2_meaning into print_2_byte so that the
  791 	  prefix and CONT are known in one place.
  792 	* cpuid.c: Fixed bug in print_2_byte: 0x7d is not sectored.
  793 	* cpuid.c: Fixed bug in print_2_byte: 0xc2 is 4K, not 4M.
  794 	* cpuid.c: Changed 6/ecx bit 0 to "hardware coordination feedback".
  795 	* cpuid.c; Changed 7/ebx bit 3 to "BMI1 instructions".
  796 	* cpuid.c: Change 7/ebx bit 12 to RDT-M.
  797 	* cpuid.c: Change 7/ebx bit 15 to RDT-A.
  798 	* cpuid.c: Corrected "0x40000003/ecx" label.
  799 	* cpuid.c; print_40000003_edx_microsoft: corrected "idle" spelling.
  800 
  801 Wed Apr 19 2018 Todd Allen <todd.allen@etallen.com>
  802 	* cpuid.c: Added mnemonic letters for some 1/ecx, 1/edx, and 7/ebx leaf
  803 	  fields.
  804 	* cpuid.c: Fixed bug with 4/ecx: field name should be "number of sets".
  805 	* cpuid.c: Fixed bug with 4/ecx leaf: pass ECX to it!
  806 	* cpuid.c; Fixed bug with 0x10/ecx: pass ECX to it!
  807 	* cpuid.c: Fixed bug with 0x10/edx: pass EDX to it!
  808 
  809 Sun Apr  8 2018 Todd Allen <todd.allen@etallen.com>
  810 	* cpuid.c: Added 2 leaf 0xfe encoding: TLB data in leaf 0x18.
  811 	* cpuid.c: Added new Intel 6/eax bit fields.
  812 	* cpuid.c: Added new Intel a/edx bit field: anythread deprecation.
  813 	* cpuid.c: Added new Intel d/0/eax bit field: IA32_XSS HDC state.
  814 	* cpuid.c: Added new Intel 10/0/ebx bit field: memory bandwidth alloc.
  815 	* cpuid.c: Added new Intel 12/0/eax bit fields
  816 	* cpuid.c: Added new Intel 18 leaf: deterministic address translation.
  817 	* cpuid.c: Added new Intel 7/ecx bit fields from Intel Architecture
  818 	  Instruction Set Extensions and Future Features Programming Reference.
  819 	* cpuid.c: Added new Intel 1b leaf from Intel Architecture
  820 	  Instruction Set Extensions and Future Features Programming Reference.
  821 	* cpuid.c: Added synth decoding for Avoton C0 stepping (same as B0).
  822 	* cpuid.c: Corrected synth decoding for Bay Trail-M C0 steppings.
  823 	* cpuid.c: Added synth decoding for Bay Trail-I (E3800).
  824 	* cpuid.c: Added synth decoding for Xeon D-1500N (Broadwell-DE A1).
  825 	* cpuid.c: Added synth decoding for Xeon E7-4800/8800 (Broadwell-EX B0).
  826 	* cpuid.c: Correct synth decoding for Bay Trail A0.
  827 	* cpuid.c: Added synth decoding for Bay Trail D0.
  828 	* cpuid.c: Added synth decoding for Core X-Series (Skylake-X).
  829 	* cpuid.c: Added synth decoding for Xeon Scalable (Bronze, Silver, Gold,
  830 	  Platinium) (Skylake).
  831 	* cpuid.c: Added synth decoding for Pentium Silver (Gemini Lake).
  832 	* cpuid.c: Added synth decoding for AMD Zen.
  833 	* cpuid.man: Added new spec updates & PPR.
  834 
  835 Fri Nov  3 2017 Todd Allen <todd.allen@etallen.com>
  836 	* cpuid.c, cpuid.man: Attribute whitepaper to Shih Kuo.
  837 
  838 Wed Jun 22 2017 Lars Wendler <polynomial-c@gentoo.org>
  839 	* cpuid.c: recent glibc versions no longer automagically include
  840 	  sysmacros.h headers. This needs to be done by the source files itself
  841 	  now.
  842 
  843 Fri Mar  3 2017 Todd Allen <todd.allen@etallen.com>
  844 	* cpuid.c: Added missing SDBG bit to 1/ecx leaf.
  845 
  846 Sun Jan 22 2017 Todd Allen <todd.allen@etallen.com>
  847 	* Made new release.
  848 	* cpuid.c: Use __cpuid_count macro for "cpuid" instruction if possible.
  849 	  This macro is present in gcc 4.3.0 and later, and works around the fact
  850 	  that the cpuid instruction writes on the PIC register.  This is only
  851 	  important when compiling PIC/PIE.
  852 	* cpuid.c: Added synth decoding for Intel Knights Landing B0.  The Intel
  853 	  docs still don't specify the stepping numbers, but all examples seen
  854 	  so far have stepping number 1, and so far B0 is the only stepping.
  855 	* cpuid.c: Added new synth decodings for Intel Kaby Lake.
  856 	* cpuid.c: Fixed synth decodings for AMD Steamroller.
  857 	* cpuid.c: Fixed synth decodings for AMD Jaguar.
  858 	* cpuid.c: Added synth decodings for AMD Puma.
  859 	* cpuid.c: Added synth decodings for AMD Excavator.
  860 	* cpuid.c: For (6,15),(0,2) Piledriver processors, detect FX series
  861 	  and report it as Vishera instead of Abu Dhabi/Seoul/Delhi.
  862 	* cpuid.c: Added general microarchitecure names for AMD (e.g.
  863 	  Piledriver) in addition to specific core names (e.g. Trinity) for
  864 	  later generation processors.  If I have trouble remembering these,
  865 	  it seems likely other people do too.
  866 	* cpuid.c: Added synth decoding for Quark X1000.
  867 	* cpuid.c: Added Intel Atom Z2760 (Clover Trail).
  868 	* cpuid.c: Added extra synth decodings for some Sandy Bridge processors.
  869 	* cpuid.c: Added extra synth decodings for some Ivy Bridge processors.
  870 	* cpuid.man: Added new & missing spec updates & revision guides.
  871 	* FUTURE: Cleaned this up somewhat.
  872 
  873 Mon Dec  5 2016 Todd Allen <todd.allen@etallen.com>
  874 	* cpuid.c: Removed stale len variable from do_file().
  875 
  876 Thu Dec  1 2016 Todd Allen <todd.allen@etallen.com>
  877 	* Made new release.
  878 
  879 Wed Nov 30 2016 Todd Allen <todd.allen@etallen.com>
  880 	* cpuid.c: Fixed bugs in the subleaf walks for 0x8000001d (AMD cache
  881 	  information) and 0x40000003 (Xen hypervisor information) because the
  882 	  code for them was under wholly the wrong loops.  Thanks to Brice
  883 	  Goglin for detecting this and working out the cause of the bug.
  884 
  885 Wed Nov 16 2016 Todd Allen <todd.allen@etallen.com>
  886 	* cpuid.c: Updated comments referencing 325462 Table 35-1 to also
  887 	  specify Volume 3.
  888 	* cpuinfo2cpuid: Added grep commands to EXAMPLES.
  889 
  890 Mon Nov 14 2016 Todd Allen <todd.allen@etallen.com>
  891 	* Made new release.
  892 	* cpuid.man: Added 334663 & 334820 spec updates.
  893 
  894 Sun Nov 13 2016 Todd Allen <todd.allen@etallen.com>
  895 	* cpuid.c: Fixed bug reported by Andrew Cooper where, in do_real, for
  896 	  the 0xd leaf, the lower half of the valid bit set for XSS should've
  897 	  used 0xd/1/ecx instead of 0xd/1/eax.  Sadly, this bug affects raw
  898 	  dumps too.
  899 	* cpuid.c: Added -l/--leaf and -s/--subleaf options to cause cpuid
  900 	  to dump just the specified leaf and subleaf.  If -s/--subleaf is not
  901 	  specified, it is assumed to be 0.  The intended purpose for this is
  902 	  to display raw dumps of not-yet-supported leaves, or to workaround
  903 	  bugs like the above.
  904 
  905 Sat Nov 12 2016 Todd Allen <todd.allen@etallen.com>
  906 	* cpuid.c: In bits_needed, add a further check for !defined(__ILP32__),
  907 	  which should help with building a 32-bit version of cpuid on a 64-bit
  908 	  system.
  909 
  910 Sat Nov 12 2016 Todd Allen <todd.allen@etallen.com>
  911 	* cpuid.c: Made editorial changes to Piotr Luc's patches (spelling,
  912 	  capitalization, register order, comments, etc.).
  913 	* cpuid.c: Added AVX512DQ, AVX512IFMA, AVX512BW, AVX512VL, and CLWB
  914 	  decoding to 7/ebx.
  915 	* cpuid.c: Added AVX512VBMI to 7/ecx.
  916 	* cpuid.c: Added print_f_0_edx to show L3 cache QoS monitoring support.
  917 	* cpuid.c: Added total & local bandwidth monitoring to 0xf/1/edx.
  918 	* cpuid.c: Added 0x15/ecx nominal core crystal clock decoding.
  919 	* cpuid.c: In print_17_0_ebx, corrected reversed scheme encodings.
  920 	* cpuid.c: Added synth decoding for Xeon D-1500 (Broadwell-DE) Y0
  921 	  stepping.
  922 	* cpuid.c: Added synth decoding comment about Braswell D1 stepping, but
  923 	  its stepping number isn't documented.
  924 	* cpuid.c: Added synth decoding for (0,6),(8,14) Kaby Lake processors.
  925 	* cpuid.c: Added synth decoding for Apollo Lake processors.
  926 	* cpuid.c: Added vague synth decoding for (0,6),(9,14) Kaby Lake
  927 	  processors.
  928 	* cpuid.c: Re-sorted (0,6),(5,7) Knights Landing to correct position.
  929 	* cpuid.c: Re-sorted (0,6),(5,15) Goldmont to correct position.
  930 
  931 Sat Oct 27 2016 Piotr Luc <Piotr.Luc@intel.com>
  932 	* cpuid.c: Add AVX512_4VNNIW & AVX512_4FMAPS flags.
  933 	* cpuid.c: Add Knights Mill (KNM) CPUID.
  934 
  935 Sun Aug 14 2016 Todd Allen <todd.allen@etallen.com>
  936 	* Made new release.
  937 	* Makefile: Added clean rules to remove tarballs & rpm's with other
  938 	  version numbers.
  939 
  940 Sun Aug 14 2016 Todd Allen <todd.allen@etallen.com>
  941 	* cpuinfo2cpuid: Added a script that takes input from a /proc/cpuinfo
  942 	  file and converts it into suitable input to cpuid.  The information
  943 	  that cpuid is capable of producing based on this very limited input
  944 	  information is slight, but apparently there is interest in getting the
  945 	  synthesized (synth) leaf from this.  There isn't much value in using
  946 	  it with an actual /proc/cpuinfo file on the local system, because just
  947 	  allowing cpuid to read the local cpuid info will provide better
  948 	  output.  But it could be useful for interpreted saved /proc/cpuinfo
  949 	  files from another system.  I slapped together the basic logic, and
  950 	  Jirka Hladky turned it into a proper perl script, with actual options,
  951 	  a help screen, and even documentation.  I then made some changes to
  952 	  give it some more uniform indentation, whitespace, and such.  And to
  953 	  give Jirka Hladky more credit, since his contribution to the script is
  954 	  larger than my own.
  955 	* Makefile: Added rules to generate cpuinfo2cpuid.man from the =pod data
  956 	  in the script.
  957 	* Makefile: Added cpuinfo2cpuid & cpuinfo2cpuid.man to the released
  958 	  materials.
  959 	* cpuid.proto.spec: Added cpuinfo2cpuid & cpuinfo2cpuid.1.gz to released
  960 	  materials.
  961 
  962 Sun Aug 14 2016 Todd Allen <todd.allen@etallen.com>
  963 	* cpuid.c: Changed instances of Kb to KB.  In print_2_meaning, changed
  964 	  an instance of 4k to 4K.
  965 
  966 Sat Aug 13 2016 Todd Allen <todd.allen@etallen.com>
  967 	* cpuid.c: Added 7/ebx SGX & FDP_EXCPTN_ONLY flags.
  968 	* cpuid.c: Added 7/ecx BNDLDX/BNDSTX MAWAU value field, RDPID & SGX_LC.
  969 	* cpuid.c: Added d/0/eax MPX state field.
  970 	* cpuid.c: In print_d_0_eax, split MPX and AVX-512 all_or_none fields
  971 	  into their component parts.  Also added IA32_XSS PT state.
  972 	* cpuid.c: In print_d_n_ecx, clarify XCR0 as user state and IA32_CXX as
  973 	  supervisor state.
  974 	* cpuid.c: In print_d_n, add MPX and PT features.
  975 	* cpuid.c: Renamed leaf 0x10 to Intel's new name.  Corrected totally
  976 	  bogus interpretation of subleaf 0.
  977 	* cpuid.c: Generalize subleaf 0x10/1 to also include 0x10/2, and
  978 	  provide new Intel correct names for each.
  979 	* cpuid.c: Added 0x14/0 PTWRITE & power event trace.
  980 	* cpuid.c: Added description for leaf 0x12 (SGX Capability) and all its
  981 	  subleaves.
  982 	* cpuid.c: Added descriptionf or leaf 0x17 (SoC vendor) and its
  983 	  subleaves.
  984 	* cpuid.c: Decode new leaf 2 cache descriptors: 0x64 & 0xc4.
  985 	* cpuid.c: Updated Atom C2000 (Avoton) with A0/A1 steppings.
  986 	* cpuid.c: Added Atom Z3n00 (Bay Trail-T B2/B3) specific stepping 1.
  987 	* cpuid.c: Added Xeon D-1500 (Broadwell-DE) V2 stepping.
  988 	* cpuid.c: Corrected Atom Z8000 (Cherry Trail) with correct model, per
  989 	  changes in its spec update.
  990 	* cpuid.c: Change the (0,6),(5,14) Skylake descriptions to be more vague
  991 	  to reflect the larger set of existing processors now.
  992 	* cpuid.c: Add actual information for the (0,6),(4,14) Skylake
  993 	  processors.
  994 	* cpuid.c: Add actual information for the (0,6),(5,14) Broadwell-E
  995 	  processors.
  996 	* cpuid.c: Add actual information for the (0,6),(4,15) Broadwell and
  997 	  Broadwell-EX processors.
  998 	* cpuid.c: Added vague mentions of Goldmont (0,6),(5,12) and (0,6),(5,15)
  999 	  based on 325462 Table 35-1.
 1000 	* cpuid.c: Add Atom S1200 (Centerton) under (0,6),(3,6) thanks to an
 1001 	  example provided by Jirka Hladky.
 1002 	* cpuid.c: Added Eden to the list of possible meanings of VIA
 1003 	  (0,6),(6,13).  An example provided by Daniel Wyatt shows that they
 1004 	  sometimes use the simple Eden brand for this architecture.
 1005 	* cpuid.man: Added various new Intel documents used while making the
 1006 	  above changes.
 1007 	* cpuid.c: Made -f - operate on stdin.
 1008 
 1009 Wed Jun 22 2016 Alan Cox <alan@lxorguk.ukuu.org.uk>
 1010 	* cpuid.c: Added out-of-memory checks to strregexp.
 1011 
 1012 Mon Oct 19 2015 Todd Allen <todd.allen@etallen.com>
 1013 	* Updated cpuid.man's list of information sources with new sources used
 1014 	  in the 20151017 release (and one renamed source).
 1015 
 1016 Sat Oct 17 2015 Todd Allen <todd.allen@etallen.com>
 1017 	* Made new release.
 1018 	* cpuid.c: Updated synth decoding for Broadwell processors.
 1019 	* cpuid.c: Added 0xd leaf field.
 1020 	* cpuid.c: Updated and expanded 0x14 leaf fields.
 1021 	* cpuid.c: Added synth decoding for Intel Xeon E7 v2 (Ivy Bridge-EX).
 1022 	* cpuid.c: Added synth decoding for Intel Core i5/i7 (Skylake).
 1023 	* cpuid.c: Added vague synth decodings for a few more future processor
 1024 	  models from Intel 64 and IA-32 Architectures Software Developer's
 1025 	  Manual (325462), Table 35-1.
 1026 
 1027 Thu Oct 15 2015 Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>
 1028 	* cpuid.c: Decode new leaf 2 cache descriptors: 6a, 6b, 6c, 6d.
 1029 	* cpuid.c: added synth decoding for Knights Landing.
 1030 	  [NOTE FROM Todd Allen: There is no datasheet or spec update for
 1031 	  Knights Landing yet, but Intel 64 and IA-32 Architectures Software
 1032 	  Developer's Manual (325462), Table 35-1 mentions that it will have the
 1033 	  family & model (0,6),(5,7).
 1034 
 1035 Sat Jun  6 2015 Todd Allen <todd.allen@etallen.com>
 1036 	* Made new release.
 1037 	* cpuid.man: Added 325462 manual.
 1038 	* cpuid.c: Added new & missing decodings for: 4/ecx, 6/eax, 7/ebx, 7/ecx.
 1039 	* cpuid.c: Overhauled handling of 0xd leaf, based on new and more
 1040 	  extensive information in the Intel CPUID documentation, particularly
 1041 	  on how to decide which leaves are valid.  The approach functions
 1042 	  correctly for the subset described in the AMD documentation, too.
 1043 	  This overhaul includes information on the XSAVEC, XGETBV, and
 1044 	  XSAVES/XRSTORS instructions.
 1045 	* cpuid.c: Renamed 0xf leaves to include "Monitoring".
 1046 	* cpuid.c: Added 0x10 leaves for QoS Enforcement.
 1047 	* cpuid.c: Added new leaf 2 cache meanings: 0x1d, 0x24, 0xa0, 0xc3.
 1048 	* cpuid.c: Added missing i7 synth decoding for (0,6),(3,14).
 1049 	* cpuid.c: Corrected Atom Z3000 model & stepping which were bafflingly
 1050 	  wrong: (0,6)(3,5),1 -> (0,6)(3,7),8.
 1051 	* cpuid.c: Corrected other Bay Trail stepping names for Celeron/Pentium
 1052 	  N and J series.
 1053 	* cpuid.man: Added references to a bunch of new Intel manuals.
 1054 	* cpuid.c: Added synth decoding for Intel Xeon Phi (Knights Corner).
 1055 	* cpuid.c: Added synth decoding for Intel Atom C2000 (Avoton).
 1056 	* cpuid.c: Added synth decoding for Intel Xeon E5-x600 (Haswell-EP).
 1057 	* cpuid.c: Added synth decoding for Intel Xeon E5-[48]800 (Haswell-EP).
 1058 	* cpuid.c: Added synth decoding for Intel Core M (Broadwell-Y).
 1059 	* cpuid.c: Added synth decoding for Intel Xeon D-1500 (Broadwell-DE).
 1060 	* cpuid.c: Added synth decoding for Intel i7-5000 Extreme (Haswell R2).
 1061 	* cpuid.c: Added synth decoding for Intel Atom Z8000 (Cherry Trail).
 1062 	* cpuid.c: Added synth decoding for Intel Pentium/Celeron N3000
 1063 	  (Braswell).
 1064 	* cpuid.c: Added synth decoding for Intel i7 5th gen (Broadwell).
 1065 	* cpuid.c: Added synth decoding for Intel E3-1200 v4 (Broadwell).
 1066 	* cpuid.c: Added Xeon E5-4600 to synth decoding for other Sandy Bridge
 1067 	  E5 processors (it was omitted accidentally).
 1068 	* cpuid.c: Added Pentium D 9xx Processor to synth decoding for Presler
 1069 	  D0 (it was omitted accidentally).
 1070 
 1071 Fri Mar 21 2014 Todd Allen <todd.allen@etallen.com>
 1072 	* cpuid.c: Deal with 0-width PKG_width fields in print_apic_synth(),
 1073 	  for CPUs where the SMT_width + CORE_width >= 8.  This happens on
 1074 	  Xeon Phi chips.
 1075 
 1076 Wed Feb 12 2014 Todd Allen <todd.allen@etallen.com>
 1077 	* cpuid.c: Added CLFLUSHOPT instruction field to leaf 7, ebx.
 1078 	* cpuid.c: Added Processor Frequency Information leaf (0x16).
 1079 
 1080 Tue Feb 11 2014 Todd Allen <todd.allen@etallen.com>
 1081 	* Makefile: Added src_tar rule.
 1082 
 1083 Tue Feb 11 2014 Todd Allen <todd.allen@etallen.com>
 1084 	* cpuid.c: Made changes to allow building and running on kFreeBSD.  This
 1085 	  started out as a patch from Andrey Rahmatullin, but I refactored it.
 1086 	  The changes to disable the cpuid kernel support are protected by a
 1087 	  USE_CPUID_MODULE definition.  And there's an additional sanity check
 1088 	  to reject -k in that case.  The changes to use the library versions of
 1089 	  sched_setaffinity are protected by USE_KERNEL_SCHED_SETAFFINITY.  I
 1090 	  continue to go straight to the kernel on linux, though.
 1091 
 1092 Tue Feb 11 2014 Todd Allen <todd.allen@etallen.com>
 1093 	* Makefile: Reorganized Andrey Rahmatullin's changes a bit and used
 1094 	  them in my development build rules (make todd) too.
 1095 
 1096 Tue Feb 11 2014 Andrey Rahmatullin <wrar@wrar.name>
 1097 	* Makefile: Honor CPPFLAGS, CFLAGS and LDFLAGS from the environment.
 1098 
 1099 Mon Jan 27 2014 Todd Allen <todd.allen@etallen.com>
 1100 	* Makefile: Change to my development build rules (make todd) to use ld's
 1101 	  --hash-style=both to avoid a SIGFPE when running on very old 32-bit
 1102 	  systems.  It has no effect on the tool for anyone else.
 1103 
 1104 Thu Jan 23 2014 Todd Allen <todd.allen@etallen.com>
 1105 	* Made new release.
 1106 
 1107 Thu Jan 23 2014 Todd Allen <todd.allen@etallen.com>
 1108 	* cpuid.c: Stop displaying raw hex for 0xc and 0xe leaves, because they
 1109 	  are reserved and just contain zeroes.
 1110 	* cpuid.c: Fixed missing leaf 0xf subleaf 1 in do_real().
 1111 	* cpuid.man: Added reference to Intel Architecture Instruction Set
 1112 	  Extensions Programming Reference (319433).
 1113 	* cpuid.c: Added new feature flags from that document.
 1114 
 1115 Sun Jan 12 2014 Todd Allen <todd.allen@etallen.com>
 1116 	* Made new release.
 1117 
 1118 Sun Jan 12 2014 Todd Allen <todd.allen@etallen.com>
 1119 	* cpuid.c: Added Celeron B800 synth decoding.
 1120 	* cpuid.c: Added Pentium G3000 & Celeron G1800 synth decoding.
 1121 	* cpuid.c: Added 4th Gen Core family mobile processors synth decoding.
 1122 	* cpuid.c: Added information about E5 v2 processors (no longer just
 1123 	  engineering samples) and related Ivy Bridge-EP processors.
 1124 	* cpuid.c: Added Bay Trail (Atom Z3000, etc.) processors synth decoding.
 1125 
 1126 Sun Jan 12 2014 Todd Allen <todd.allen@etallen.com>
 1127 	* cpuid.man: Added reference to Intel decoding from Intel 64 and IA-32
 1128 	  Architectures Software Developer's Manual Volume 2A: Instruction Set
 1129 	  Reference, A-M (253666).
 1130 	* cpuid.c: Added new Intel decodings from that document.
 1131 
 1132 Sun Jan 12 2014 Todd Allen <todd.allen@etallen.com>
 1133 	* cpuid.c: Added new (instruction supported synth) field to report on
 1134 	  instruction support when knowledge of that is scattered across
 1135 	  multiple CPUID leaves.  PREFETCH/PREFETCHW is the weirdest example.
 1136 	* cpuid.c: Clarified the raw PREFETCH/PREFETCHW field in 80000001 edx
 1137 	  leaf with the 3DNow! prefix, similar to the description in the AMD
 1138 	  CPUID docs.  Thanks to Chris Orgill for reporting these two issues.
 1139 
 1140 Fri Sep 27 2013 Todd Allen <todd.allen@etallen.com>
 1141 	* cpuid.c: Added missing break to decode_amd_model(), family (0,15),
 1142 	  model (4,0), case 0x18.  Thanks to David Binderman for reporting this.
 1143 
 1144 Mon Jun 10 2013 Todd Allen <todd.allen@etallen.com>
 1145 	* Made new release.
 1146 
 1147 Mon Jun 10 2013 Todd Allen <todd.allen@etallen.com>
 1148 	* cpuid.c: Added mention of Opteron 3200 (Zurich) chips, accidentally
 1149 	  omitted from yesterday's updates.
 1150 
 1151 Sun Jun  9 2013 Todd Allen <todd.allen@etallen.com>
 1152 	* Made new release.
 1153 
 1154 Sun Jun  9 2013 Todd Allen <todd.allen@etallen.com>
 1155 	* cpuid.c: Updated 14h Model 00h-0Fh AMD model tables.
 1156 	* cpuid.c: Added synth decoding for Opteron x300 (Piledriver) chips.
 1157 	* cpuid.c: Added synth decoding for family 16h processors, tentatively
 1158 	  identified as Steamroller.
 1159 	* cpuid.man: Added new AMD 15h Model 10h-1Fh, and AMD 16h Model 00h-0Fh
 1160 	  manuals.
 1161 
 1162 Sat Jun  8 2013 Todd Allen <todd.allen@etallen.com>
 1163 	* cpuid.c: Added sanity check to 0xCxxxxxxx leaves to check for an
 1164 	  unreasonably large indicated maximum leaf number.  If found, further
 1165 	  walk of them is halted.
 1166 	* cpuid.c: Skip 0x4xxxxxxx leaves if cpuid does not indicate that the
 1167 	  environment is a guest.  This was suggested by Steven Levine, although
 1168 	  I implemented it differently.
 1169 
 1170 Sat Jun  8 2013 Todd Allen <todd.allen@etallen.com>
 1171 	* cpuid.c: Clarified some KVM hypervisor leaf feature flags that Eduardo
 1172 	  Habkost pointed out.  Added a couple new flags.
 1173 
 1174 Sat Jun  8 2013 Todd Allen <todd.allen@etallen.com>
 1175 	* cpuid.c: Extended Eduardo Habkost's stash separation to include the
 1176 	  0x80000008 leaf, and the leaves that inform transmeta_info.
 1177 
 1178 Sat Jun  8 2013 Eduardo Habkost <ehabkost@raisama.net>
 1179 	* cpuid.c: This patch separates the code that changes fields in the
 1180 	  'stash' struct from the code that prints that information. This way,
 1181 	  the stash struct will get updated even when in raw mode, so other
 1182 	  parts of the code can use that information.
 1183 	  [NOTE FROM Todd Allen: It used to be that the stash was only set and
 1184 	  used in cooked mode, but some uses dealing with the hypervisor snuck
 1185 	  out and were used all the time.  This new separation is only really
 1186 	  necessary for the hypervisor fields, but it's good practice to do all
 1187 	  the fields this way, so I'm accepting the patch as is.]
 1188 
 1189 Sat Jun  8 2013 Todd Allen <todd.allen@etallen.com>
 1190 	* cpuid.c: Added synth decoding for Celeron G400/G500.
 1191 	* cpuid.c: Added synth decoding for Cedarview B3.
 1192 	* cpuid.c: Added synth decoding for Ivy Bridge i3 processors.
 1193 	* cpuid.c: Added synth decoding for Ivy Bridge Pentium G1600/G2000/G2100.
 1194 	* cpuid.c: Added synth decoding for Ivy Bridge Pentium
 1195 	  900/1000/2000/2100.
 1196 	* cpuid.c: Clarified that Ivy Bridge Xeon E3-1200 is actually E3-1200 v2.
 1197 	* cpuid.c: Added vague synth decoding for Haswell, but spec updates
 1198 	  show no specific chips or steppings yet.
 1199 	* cpuid.c: Expanded A100/A110 synth decoding to include semi-official
 1200 	  Pentium M (Crofton) processors in Apple TV boxes.
 1201 	* cpuid.c: Added Xeon E5-2600 v2 engineering sample.  Perhaps this will
 1202 	  be the final synth decoding for them, but for now it's just marked as
 1203 	  an engineering sample.
 1204 	* cpuid.man: Added new Intel manuals.
 1205 
 1206 Fri Aug 24 2012 Todd Allen <todd.allen@etallen.com>
 1207 	* cpuid.c: Added sanity check to 0x4xxxxxxx leaves to check for an
 1208 	  unrecognized hypervisor and an unreasonably large indicated maximum
 1209 	  leaf number.  If found, further walk of them is halted.
 1210 
 1211 Tue Aug 21 2012 Todd Allen <todd.allen@etallen.com>
 1212 	* cpuid.c: Cleaned up printf(name) statements that were admonished by
 1213 	  clang.
 1214 
 1215 Fri Jun  1 2012 Todd Allen <todd.allen@etallen.com>
 1216 	* Made new release.
 1217 
 1218 Thu May 31 2012 Todd Allen <todd.allen@etallen.com>
 1219 	* cpuid.c: Updated CPUID feature flags.
 1220 	* cpuid.c: Updated CPUID function 7 to support sub-leaves (mostly for
 1221 	  future functionality that might be added to them).
 1222 	* cpuid.c: Updated synth decoding for Intel Dothan C0 because some use
 1223 	  65nm process now.
 1224 	* cpuid.c: Updated Intel EP80579 synth to mention 65nm process.
 1225 	* cpuid.c: Added synth decoding for Intel Atom E600 series.
 1226 	* cpuid.c: Updated synth decoding for Intel Sandy Bridge D2 to include J1
 1227 	  and Q0, which have the same CPUID.
 1228 	* cpuid.c: Added synth decoding for Intel Atom D2000/N2000 (Cedarview).
 1229 	* cpuid.c: Added synth decoding for Intel Sandy Bridge-E.
 1230 	* cpuid.c: Added synth decoding for AMD Llano.
 1231 	* cpuid.c: Improved distinction between AMD Interlagos & Zambezi.
 1232 	* cpuid.c: Added synth decoding for RDC IAD 100.
 1233 	* cpuid.c: Fixed some formatting bugs for Transmeta-specific leaves.
 1234 	* cpuid.c: Added synth decoding for some of VIA's versions of WinChips.
 1235 	* cpuid.man: Added mentions of spec updates for several Atoms, i7 for
 1236 	  LGA-2011, and Xeon E5; and AMD 12h family.
 1237 
 1238 Wed May 30 2012 Todd Allen <todd.allen@etallen.com>
 1239 	* cpuid.c: Fixed ancient bug in distinguishing Irwindale from Nocona
 1240 	  (they differ only by L2 cache size).
 1241 	* cpuid.c: Added synth decoding for desktop and mobile Ivy Bridge.
 1242 
 1243 Sat Feb 25 2012 Todd Allen <todd.allen@etallen.com>
 1244 	* Made new release.
 1245 	* cpuid.c: Cleaned up hypervisor-specific leaves for KVM.
 1246 	* cpuid.man: Added mention of KVM cpuid documentation.
 1247 
 1248 Fri Feb 24 2012 Todd Allen <todd.allen@etallen.com>
 1249 	* cpuid.c: Added synth decoding for Intel Westmere-EX processors.
 1250 	* cpuid.c: Added synth decoding for AMD family 15h chips: AMD FX
 1251 	  (Zambezi), Opteron 6200 (Interlagos), and Opteron 4200 (Valencia).
 1252 	* cpuid.c: Added synth decoding for AMD Z-Series and other Fusion
 1253 	  chip ON-C0 steppings.
 1254 	* cpuid.c: Added synth decoding for Atom Z600 (Lincroft).
 1255 	* cpuid.c: Updated AMD model decoding for family 10h processors.
 1256 	* cpuid.man: Added mention of AMD family 14h and 15h documents, and
 1257 	  Intel Westmere-EX & Lincroft documents.
 1258 	* cpuid.man: Removed obsolete limitation about 0x8000001b.
 1259 	* cpuid.c: Added support for hypervisor leaves (0x4000000 and after).
 1260 	  Interpreted known generic leaves.  Interpreted hypervisor-specific
 1261 	  leaves for Xen (deduced from source, as no documentation on them
 1262 	  exists).  Interpreted hypervisor-specific leaves for KVM.  Interpreted
 1263 	  hypervisor-specific leaves for Microsoft.
 1264 
 1265 Tue Jan  3 2012 Todd Allen <todd.allen@etallen.com>
 1266 	* cpuid.c: Added synth decoding for Athlon 64 (Venice DH-E6) chips.
 1267 
 1268 Wed Nov  2 2011 Todd Allen <todd.allen@etallen.com>
 1269 	* cpuid.c: Added saw_4 and saw_b stash flags to deal with chips that
 1270 	  report 0xc codes but still omit 0xb codes.  This way, a maximum code
 1271 	  of 0xc no longer implies the presence of 0xb codes for things like
 1272 	  APIC decoding.
 1273 
 1274 Mon Mar 28 2011 Todd Allen <todd.allen@etallen.com>
 1275 	* cpuid.c: Added APIC synth decoding for AMD, deduced by analogy to Intel
 1276 	  code and the multiprocessor synth logic.
 1277 
 1278 Mon Mar  7 2011 Todd Allen <todd.allen@etallen.com>
 1279 	* cpuid.c: Added some decoding for VIA 0xc0000002 codes, based on
 1280 	  information from Juerg Haefliger.  Very incomplete because VIA
 1281 	  doesn't document their functions well.
 1282 	* cpuid.c: Fixed output of 0xc0000001 raw dump to conform to new style.
 1283 
 1284 Sat Mar  5 2011 Todd Allen <todd.allen@etallen.com>
 1285 	* Made new release.
 1286 
 1287 Fri Mar  4 2011 Todd Allen <todd.allen@etallen.com>
 1288 	* cpuid.c,cpuid.man: Added Celeron T1000 series, previously missing.
 1289 	* cpuid.c,cpuid.man: Added Celeron Mobile P4000, U3000 series.
 1290 	* cpuid.c,cpuid.man: Added current Sandy Bridge processors.
 1291 
 1292 Thu Mar  3 2011 Todd Allen <todd.allen@etallen.com>
 1293 	* cpuid.c: Added detection of PCIDs & TSC-DEADLINE.
 1294 	* cpuid.c: Verified Mike Stroyan CPUID 2 cache meanings from Intel CPUID
 1295 	  document (241618-037).  Added 0x76 meaning.
 1296 	* cpuid.c: Added various new flags from Intel 241618-037.
 1297 	* cpuid.c,cpuid.man: Added AMD family 14h processors.
 1298 	* cpuid.c,cpuid.man: Updated Intel process id table, mostly as just
 1299 	  generalizations.
 1300 
 1301 Tue Nov  9 2010 Todd Allen <todd.allen@etallen.com>
 1302 	* cpuid.c: Update the usage() screen, since some of its -i and -1
 1303 	  comments are incorrect now.
 1304 
 1305 Mon Oct  4 2010 Todd Allen <todd.allen@etallen.com>
 1306 	* cpuid.c, cpuid.man: Added AMD Geode LX.
 1307 	* cpuid.c: Added NSC Geode GX2 and AMD Geode GX.
 1308 	* cpuid.c, cpuid.man: Added AMD Geode NX.
 1309 
 1310 Sat Oct  2 2010 Todd Allen <todd.allen@etallen.com>
 1311 	* Made new release.
 1312 	* cpuid.c,cpuid.man: Added Intel Atom N500.
 1313 
 1314 Thu Sep 30 2010 Todd Allen <todd.allen@etallen.com>
 1315 	* cpuid.c,cpuid.man: Added support for Intel Tolapai (SoC).
 1316 	* cpuid.c,cpuid.man: Added support for Intel Clarkdale chips from
 1317 	  specification update 323179.
 1318 	* cpuid.c: Generalized decode_amd_model by adding full brand tables for
 1319 	  AMD chips.  If a BIOS doesn't recognize a chip it writes
 1320 	  "model unknown" into its brand string via MSR's.
 1321 	  decode_override_brand detects that and uses the decode_amd_model brand
 1322 	  to differentiate CPUs.
 1323 	* cpuid.c: Corrected 80000001/ebx PkgType, BrandId, and str1 bit fields.
 1324 	* cpuid.c: Corrected problems with brand field decoding because its bit
 1325 	  field with differs from architecture to architecture.
 1326 	* cpuid.c: decode_amd_model: the partialmodel decrement special case
 1327 	  applies only to XF=1,F=15; and not to XF=2,F=15.
 1328 
 1329 Mon Sep 27 2010 Todd Allen <todd.allen@etallen.com>
 1330 	* cpuid.c: Added support for NSC/AMD Geode GX1.
 1331 
 1332 Wed Sep  8 2010 Todd Allen <todd.allen@etallen.com>
 1333 	* cpuid.c: Corrected the Transmeta processor revisions, which should've
 1334 	  been in hex instead of octal.
 1335 
 1336 Thu Sep  2 2010 Todd Allen <todd.allen@etallen.com>
 1337 	* cpuid.c: Added a couple vague steppings for Transmeta Efficeon TM8000
 1338 	  processors.  Updated some transmeta bitfields.  This is all done
 1339 	  blind, as I have no examples of these chips, little documentation, and
 1340 	  the company is long defunct.
 1341 
 1342 Thu Sep  2 2010 Todd Allen <todd.allen@etallen.com>
 1343 	* Made new release.
 1344 	* cpuid.c: Fixed a few header strings that had incorrect function hex
 1345 	  codes or registers.
 1346 
 1347 Wed Sep  1 2010 Todd Allen <todd.allen@etallen.com>
 1348 	* Made new release.
 1349 	* cpuid.c: Fixed buffer size in do_file() to be able to read new
 1350 	  raw dumps with ecx information.  It needed a couple more characters.
 1351 	* cpuid.c: Added Celeron M (Yonah D0) & Celeron M (Merom-L1 A1) synth
 1352 	  entries.
 1353 	* cpuid.c: added Xeon Processor LV (Sossaman D0).
 1354 	* cpuid.c: Update Itanium chips in the synth tables.  Sadly, this all
 1355 	  still is being done blind, as I have no access to any Itanium chips.
 1356 	* cpuid.c: Wrote an x86_64 counterpart to the assembly code for
 1357 	  bits_needed().
 1358 	* Makefile, cpuid.proto.spec: Changed to support building for both i386
 1359 	  and x86_64.
 1360 
 1361 Tue Aug 31 2010 Todd Allen <todd.allen@etallen.com>
 1362 	* Made new release.
 1363 	* cpuid.c: Rearranged synth rules and substantially simplified query
 1364 	  macros into something like the form I was hoping for when I started
 1365 	  this redesign.
 1366 	* cpuid.c: Added changes from the new AMD CPUID document that claims to
 1367 	  have been released in September 2010!
 1368 	* cpuid.c: Changed raw dump to include %ecx values to accomodate CPUID
 1369 	  functions with gaps in the useful %ecx range (e.g. 0xd).  The file
 1370 	  parser accepts either the old or new forms.
 1371 	* Makefile, cpuid.proto.spec: Updated build scheme for my current
 1372 	  systems.
 1373 	* LICENSE: Changed to a GPL license.
 1374 
 1375 Mon Aug 30 2010 Todd Allen <todd.allen@etallen.com>
 1376 	* cpuid.c: Semi-mechanically eliminated the codes used to
 1377 	  disambiguate in the synth string and replaced them with queries,
 1378 	  which I think will be more general-purpose and will allow me to
 1379 	  eliminate a lot of the problem with codes appropriate for one
 1380 	  model being a problem for subsequent models (e.g. the Core Solo
 1381 	  vs. Core Duo distinction).  There still are general-purpose
 1382 	  queries like there were general-purpose codes, but the
 1383 	  special-case queries will only matter for those families that
 1384 	  care about them.  This does mean that it's possible for multiple
 1385 	  queries to register as true, so I have to be more careful with
 1386 	  the order of chips in the synth tables.
 1387 
 1388 Fri Aug 27 2010 Todd Allen <todd.allen@etallen.com>
 1389 	* Tested on a variety of CPUs.
 1390 	* cpuid.c: Corrected Mobile Turion checking in decode_brand.
 1391 	* cpuid.c: Added synth entries for 6/15/4 pre-production
 1392 	  Conroe B0/Woodcrest B0.
 1393 	* cpuid.c: Added synth entries for Santa Rosa F3 stepping
 1394 	  (undocumented).
 1395 	* cpuid.c: Fixed synth entries for Brisbane, Toledo, and Windsor to
 1396 	  expect code DA (for dual-core Athlons).
 1397 	* cpuid.c: Generalized the check for Intel Extreme Edition chips.
 1398 	* cpuid.c: Added synth entries Core 2 Quad (Conroe) chips.
 1399 	* cpuid.c: Added synth entry for VIA 6/13/0 chip.  Unfortunately, there
 1400 	  is no documentation and very little anecdotal evidence of this chip,
 1401 	  so the description is vague.
 1402 	* cpuid.c: Added addition CPUID function 2 cache codes from Mike
 1403 	  Stroyan.
 1404 	* cpuid.c: Fixed some cut&paste errors that had EAX where it should
 1405 	  have been EBX, as reported by Mike Stroyan
 1406 	* cpuid.c: Added very short synth table for SiS chips.  I found no
 1407 	  documentation on these, so I just have the one case.
 1408 	* cpuid.c: Fixed the (synth) strings for oddball chips, which suffered
 1409 	  from a cut&paste error.
 1410 	* cpuid.c: Simplified some of the fallback strings that had grown
 1411 	  ridiculously long.
 1412 
 1413 Thu Aug 26 2010 Todd Allen <todd.allen@etallen.com>
 1414 	* Tested on a variety of CPUs.
 1415 	* cpuid.c: Added more logic for Woodcrest pre-production chips.
 1416 	* cpuid.c: Corrected synth logic for VIA Antaur chips.
 1417 	* cpuid.c: Added synth for plain vanilla Thoroughbred Athlon.
 1418 
 1419 Wed Aug 25 2010 Todd Allen <todd.allen@etallen.com>
 1420 	* Tested on a variety of CPUs.
 1421 	* cpuid.c: Fixed a couple bugs with decoding processor numbers in
 1422 	  print_synth_amd_model.
 1423 
 1424 Tue Aug 24 2010 Todd Allen <todd.allen@etallen.com>
 1425 	* cpuid.c: Further changes to mp_synth decoding, including tracking
 1426 	  of the decoding method used (there are around 4 major approaches,
 1427 	  depending on how you count).
 1428 	* cpuid.c: Added apic_synth decoding to find the appropriate field
 1429 	  widths and decode the process local APIC physical ID.  This is useful
 1430 	  in its own right, but also helps convince me that many Intel chips
 1431 	  really do claim to have hyperthreads even though they don't.
 1432 	* cpuid.c: Added support for direct instruction (-i) functionality to
 1433 	  report on all CPUs by calling sched_setaffinity to reschedule the
 1434 	  process on each CPU.  This is now the default behavior for -i, but
 1435 	  it can be overridden with the -1 option.
 1436 	* cpuid.c: added Barcelona B1 (undocumented chip) synth decoding.
 1437 
 1438 Mon Aug 23 2010 Todd Allen <todd.allen@etallen.com>
 1439 	* cpuid.c: Made real_get pass the requested ecx values even when
 1440 	  using -k.  Modern linux kernel expect the ecx values in the upper
 1441 	  32 bits of the file offset (i.e. lseek64).
 1442 	* cpuid.c: Worked out a fallback for determining mp_synth information
 1443 	  for Intel chips which lack CPUID function 4.
 1444 	* cpuid.c: Added mechanism for determining mp_synth information from
 1445 	  CPUID function 11 information if it's available (because if it's
 1446 	  present on Intel chips, it's the only reliable way; the older
 1447 	  mechanisms return gibberish).
 1448 
 1449 Fri Aug 20 2010 Todd Allen <todd.allen@etallen.com>
 1450 	* cpuid.c, cpuid.man: Added to synth even more Nehalem chips.
 1451 	* cpuid.c: Added 6/15 model for VIA Nano, but there's very little
 1452 	  detailed information on this chip, so that's it.
 1453 	* cpuid.c: Corrected some AMD codename confusion from 2006:
 1454 	  Dublin->ClawHammer/Odessa, Sonora->Dublin,
 1455 	  Palermo(mobile)->Georgetown/Sonora, Lancaster->Lancaster/Richmond,
 1456 	  Richmond->Taylor/Trinidad.
 1457 	* cpuid.c: Overhauled the AMD model dumping code to understand new
 1458 	  families.
 1459 	* cpuid.c: Tweaked decode_mp_synth to use ApicIdCoreIdSize, per AMD's
 1460 	  CPUID recommendations.
 1461 
 1462 Thu Aug 19 2010 Todd Allen <todd.allen@etallen.com>
 1463 	* cpuid.c, cpuid.man: Updated synth tables for Intel Xeons.
 1464 	* cpuid.c: Removed all the "How to distinguish" comments, since
 1465 	  it seems to be very common for Intel to have indistinguishable
 1466 	  processors nowadays (the old cache-checking tricks are unreliable
 1467 	  now).
 1468 	* cpuid.c, cpuid.man: Added to synth additional Nehalem chips as I'm
 1469 	  able to hunt them down.
 1470 
 1471 Wed Aug 18 2010 Todd Allen <todd.allen@etallen.com>
 1472 	* cpuid.c, cpuid.man: Updated synth tables for Intel Core 2, Atom,
 1473 	  Celeron, and Pentium chips based on the same cores.
 1474 
 1475 Tue Aug 17 2010 Todd Allen <todd.allen@etallen.com>
 1476 	* cpuid.c, cpuid.man: Updated synth tables for AMD family 10h (K10)
 1477 	  and family 11h processors.
 1478 	* cpuid.c: simplified print_x_synth_amd by pruning its table down to
 1479 	  just the three families that differ from normal 1/eax simple synth,
 1480 	  and falling back on 1/eax simple synth otherwise.
 1481 
 1482 Mon Aug 16 2010 Todd Allen <todd.allen@etallen.com>
 1483 	* cpuid.c: Added new steppings to synth tables using latest spec
 1484 	  updates for all AMD processor families already in them.
 1485 	* cpuid.c, cpuid.man: Updated synth tables for AMD family 0Fh (K8)
 1486 	  processors.
 1487 
 1488 Fri Aug 13 2010 Todd Allen <todd.allen@etallen.com>
 1489 	* cpuid.c: Updated raw data dump based on latest CPUID documentation
 1490 	  from Intel & AMD.
 1491 	* cpuid.c: Fixed dump of function 4 to iterate over all caches.
 1492 
 1493 Thu Aug 12 2010 Todd Allen <todd.allen@etallen.com>
 1494 	* cpuid.c: Reorganized synth tables to always use extended family
 1495 	  and extended model numbers since they are so prevalent on modern
 1496 	  chips.
 1497 	* cpuid.c: Added new steppings to synth tables using latest spec
 1498 	  updates for all Intel processor families already in them.
 1499 
 1500 Sun Nov 26 2006 Todd Allen <todd.allen@etallen.com>
 1501 	* cpuid.c: Recognize Intel Core 2 Extreme Edition from brand string.
 1502 	  Thanks to Tony Freitas for explaining that Ennnn means desktop while
 1503 	  Xnnnn means Extreme Edition for those processors.
 1504 
 1505 Wed Nov 22 2006 Todd Allen <todd.allen@etallen.com>
 1506 	* cpuid.c: Recognize Itanium2 Montecito C2.
 1507 	* cpuid.c: Recognize Intel Core 2 Duo Mobile (Conroe B2).
 1508 	* cpuid.c: Recognize Intel Quad-Core Xeon Processor 5300 (Woodcrest B3)
 1509 	  and Intel Core 2 Extreme Quad-Core Processor QX6700 (Woodcrest B3).
 1510 	* cpuid.c: Recognize Intel Celeron D Processor 36x (Cedar Mill D0).
 1511 	* cpuid.c: Distinguish Core 2 Duo from Core 2 Extreme Edition based on
 1512 	  presence or absence of hyperthreading.  Thanks to Tony Seacow for
 1513 	  providing output for numerous processors and the advice about
 1514 	  hyperthreading.
 1515 
 1516 Thu Nov  2 2006 Todd Allen <todd.allen@etallen.com>
 1517 	* cpuid.c: Changed "number of logical CPU cores - 1" to "number of CPU
 1518 	  cores - 1".
 1519 
 1520 Sun Sep 17 2006 Todd Allen <todd.allen@etallen.com>
 1521 	* Made new release.
 1522 	* cpuid.c: Made the cpuid instruction (-i, --inst options) the default.
 1523 	* cpuid.c: Added -k, --kernel option to cause the kernel module to be
 1524 	   used.
 1525 	* cpuid.c: Removed confusing CPU number from output when using
 1526 	  the cpuid instruction.
 1527 	* cpuid.man: Updated with new options.
 1528 	* cpuid.c, Makefile: Changed i386 _llseek kludge to workaround
 1529 	  offsets >= 0x80000000.  Now using -D_FILE_OFFSET_BITS=64 in the
 1530 	  Makefile instead.  This should allow the i386 cpuid to work on
 1531 	  an x86_64 system.
 1532 	* cpuid.c: Added knowledge of CPU modules to synthesized field: Tulsa,
 1533 	  Woodcrest B1 (pre-production)
 1534 	* cpuid.c: In synthesized model field, properly distinguish between
 1535 	  Intel Pentium D Processor 8x0 and Intel Pentium Extreme Edition
 1536 	  Processor 840 (both Smithfields).
 1537 	* cpuid.man: Added mention of new 7100 series spec updates.
 1538 	* cpuid.spec: Changed Copyright to License.
 1539 
 1540 Thu Aug 23 2006 Todd Allen <todd.allen@etallen.com>
 1541 	* cpuid.c: Removed unnecessary one_cpu argument from do_file.
 1542 	* cpuid.c: Added -v option to display version number.
 1543 
 1544 Wed Aug 23 2006 Todd Allen <todd.allen@etallen.com>
 1545 	* Made new release.
 1546 
 1547 Tue Aug 22 2006 Todd Allen <todd.allen@etallen.com>
 1548 	* cpuid.c, cpuid.man: Added -i option to use the CPUID instruction
 1549 	  directly instead of the CPUID kernel module.
 1550 	* cpuid.c: Change Pentium Processor 9x0 to 9xx because of 9x5
 1551 	  processors.
 1552 	* cpuid.man: Updated information about determining synthesized model
 1553 	  information, and added information about determining synthesized
 1554 	  multiprocessor information.
 1555 
 1556 Mon Aug  7 2006 Todd Allen <todd.allen@etallen.com>
 1557 	* cpuid.proto.spec: Change URL to cpuid-specific page.
 1558 
 1559 Sun Aug  6 2006 Todd Allen <todd.allen@etallen.com>
 1560 	* Made new release.
 1561 
 1562 Sat Aug  5 2006 Todd Allen <todd.allen@etallen.com>
 1563 	* cpuid.c: Added support for differentiating Core 2 Duo CPUs from Xeon
 1564 	  5100 CPUs based on the brand string.
 1565 	* cpuid.c: Clarified that CPUID 4 ECX contains one less than the
 1566 	  number of sets.
 1567 	* cpuid.c: Added support for CPUID 5 ecx & edx.
 1568 	* cpuid.c: Added support for CPUID 6 ecx.
 1569 	* cpuid.c: Added support for CPUID 0xa eax & ebx.
 1570 	* cpuid.c: Made CPUID functions 7, 8, and 9 reserved (i.e. say nothing
 1571 	  until and unless they are defined).
 1572 	* cpuid.c: Corrected CPUID 1 ecx xTPR disabnle.
 1573 
 1574 Wed Aug  2 2006 Todd Allen <todd.allen@etallen.com>
 1575 	* cpuid.c: Corrected bug with Core 2 Duo recognition.
 1576 	* cpuid.c: Distinguish between Allendale and Conroe cores based on
 1577 	  L2 cache size.
 1578 	* cpuid.c: Added VIA C7 & C7-M names to Esther WinChip C5J core CPUs.
 1579 	* cpuid.man: Mention wikipedia pages for CPUs.
 1580 
 1581 Tue Aug  1 2006 Todd Allen <todd.allen@etallen.com>
 1582 	* cpuid.c: On help screen, clarified that -f option reads output from
 1583 	  -r option.
 1584 	* cpuid.proto.spec: Used %{} macros for external command invocations.
 1585 
 1586 Mon Jul 31 2006 Todd Allen <todd.allen@etallen.com>
 1587 	* Makefile: Removed install -o 0 -g 0 options.  For installations
 1588 	  from the tarball, the user will have to be root anyway.  And for
 1589 	  rpm, the %defattr() attribute in the spec is handling this more
 1590 	  cleanly.  Finally, those options are causing some non-root
 1591 	  installations to have to be done by the root user, which is
 1592 	  undesirable.
 1593 	* cpuid.c: Improved identification for VIA C3 (Samuel WinChip C5A core).
 1594 	* cpuid.c: Loosened up check for "Mobile AMD Athlon(tm) XP" by
 1595 	  removing "-M" suffix.
 1596 	* cpuid.c: Recognize mobile Athlon XP (Thoroughbred).
 1597 
 1598 Sun Jul 30 2006 Todd Allen <todd.allen@etallen.com>
 1599 	* Made new release.
 1600 	* cpuid.c: Fixed "deterministic cache parameters (4)", so that its
 1601 	  children aren't staggered.
 1602 	* cpuid.c: Corrected Venice and Palermo processors with DH-E3 and
 1603 	  DH-E6 steppings that had been reported as Toledo processors
 1604 	  incorrectly.
 1605 	* cpuid.c: Corrected codename for the Athlon Thoroughbred's Duron
 1606 	  counterpart: Applebred.
 1607 	* cpuid.c: Added code to distinguish Athlon XP Thortons from Bartons,
 1608 	  based on L2 cache size.
 1609 	* cpuid.c: Added code to distinguish Athlon 64 X2 Manchester E6 from
 1610 	  Athlon 64 X2 Toledo.
 1611 	* cpuid.c: Added Celeron Yonah C0.
 1612 	* cpuid.c: Added Core Yonah D0.
 1613 	* cpuid.c: Added Xeon Nocona R0 / Irwindale R0 stepping.
 1614 	* cpuid.c: Added Pentium 4 Cedar Mill C1, Pentium D Presler C1, and
 1615 	  Xeon Dempsey C1.
 1616 	* cpuid.c: Added Xeon Woodcrest B2.
 1617 	* cpuid.c: Added Core 2 Conroe B1 & B2 & Core 2 Extreme Processor B1 &
 1618 	  B2.
 1619 	* cpuid.c: Updated Itanium2 processors.
 1620 	* cpuid.man: Added Intel specification updates for new CPUs.
 1621 
 1622 Wed Jul 26 2006 Todd Allen <todd.allen@etallen.com>
 1623 	* cpuid.c: In decode_brand, added check for "Athlon(TM) XP", equivalent
 1624 	  to "Athlon(tm) XP".
 1625 	* cpuid.c: Fixed "80000002" typo in print_80860002_eax().
 1626 
 1627 Mon Jul 24 2006 Todd Allen <todd.allen@etallen.com>
 1628 	* cpuid.c: Distinguish properly between Core Solo, Core Duo, and
 1629 	  Xeon Processor LV.  Reorganized multi-processor decoding to
 1630 	  support that.
 1631 
 1632 Sun Jul 23 2006 Todd Allen <todd.allen@etallen.com>
 1633 	* cpuid.c: Fixed emission of raw values for cpuid code 2.
 1634 	* cpuid.c: Added -f file option to read raw hexadecimal input from a
 1635 	  file and parse it instead of executing the cpuid instruction, and
 1636 	  code reorganization to support this.
 1637 
 1638 Mon May 22 2006 Todd Allen <todd.allen@etallen.com>
 1639 	* cpuid.c: Fixed "unrecogninzed" typo in error.
 1640 
 1641 Fri Apr  7 2006 Todd Allen <todd.allen@etallen.com>
 1642 	* cpuid.proto.spec: Added %defattr so that the files in the rpm's are
 1643 	  owned by "root" and not "todd".  (Why did no one scream bloody murder
 1644 	  about this before?)
 1645 
 1646 Mon Apr  3 2006 Todd Allen <todd.allen@etallen.com>
 1647 	* Made new release.
 1648 	* cpuid.c: Added code to distinguish between the two different Dual-Core
 1649 	  Xeon (Paxville A0) and Dual-Core Xeon Processor 7000 (Paxville A0).
 1650 	  Empirically, the significant differences are the VMX flag and the
 1651 	  "execution disable" flag.  The VMX flag is in an Intel-defined
 1652 	  CPUID function, so it's used.  Thanks to Jason Nicholls for providing
 1653 	  the Dual-Core Xeon (Paxville A0) output that made this possible.
 1654 	* cpuid.c: Added detection for Xeon Processor LV (Sossaman C0).
 1655 
 1656 Mon Mar 13 2006 Todd Allen <todd.allen@etallen.com>
 1657 	* Made new release.
 1658 	* cpuid.c: Fixed code that distinguished processors based on
 1659 	  presence or absence of L3 cache.  Some of the cache codes weren't
 1660 	  being recognized as L3 cache.
 1661 
 1662 Sun Feb 26 2006 Todd Allen <todd.allen@etallen.com>
 1663 	* Made new release.
 1664 
 1665 Wed Feb 22 2006 Todd Allen <todd.allen@etallen.com>
 1666 	* cpuid.c: Added VMX: virtual machine extensions to CPUID function 1,
 1667 	  register ecx.
 1668 	* cpuid.c: Added SVM LBR virtualization to CPUID function 8000000a,
 1669 	  register edx.
 1670 	* cpuid.c: Fixed cut & paste header error in print_8000000a_eax.
 1671 
 1672 Tue Feb 21 2006 Todd Allen <todd.allen@etallen.com>
 1673 	* cpuid.c: Renamed "hyper-threading technology" field to
 1674 	  "hyper-threading / multi-core supported" to eliminate some confusing
 1675 	  situations, such as Northwood chips which nominally support hyper-
 1676 	  threading, but where it is disabled in the chip; or where hyper-
 1677 	  threading is disabled in the BIOS; or AMD multi-core chips, which
 1678 	  indicate TRUE here, but all of which lack hyper-threading at present.
 1679 	* cpuid.c: Updated family 15 description, which had grown very stale.
 1680 	* cpuid.c: Generalized Intel Pentium D Processor 900 to 9x0.
 1681 	* cpuid.c: Added Processor Number info to Smithfield processors.
 1682 
 1683 Wed Feb  8 2006 Todd Allen <todd.allen@etallen.com>
 1684 	* Made new release.
 1685 	* cpuid.c: Use defined(i386) instead of __LONG_MAX__ to determine
 1686 	  whether or not it's necessary to use _llseek().  Fixes handling of
 1687 	  functions >= 2**31 on some build systems, like the one I used to
 1688 	  build the binary rpm.  (D'oh!)  And also indirectly affects the
 1689 	  (synth) field.
 1690 	* cpuid.c: Fix a busted error check in read_reg() that caused it to
 1691 	  return success if the read() failed and quiet was true.
 1692 	* LICENSE: Created LICENSE file (using content straight out of the
 1693 	  man page).
 1694 
 1695 Tue Feb  7 2006 Todd Allen <todd.allen@etallen.com>
 1696 	* Made new release.
 1697 	* cpuid.c: Correctly distinguish Egypt/Italy processors.
 1698 	* cpuid.c: Fixed minor problems in error checking in open_file().
 1699 	* cpuid.spec: Fixed bad Packager field.
 1700 	* cpuid.spec: Include ChangeLog.
 1701 	* cpuid.man: Added -r/--raw description.
 1702 	* cpuid.man: Clarified info used for (synth) field.
 1703 	* cpuid.man: Fixed version number & date.
 1704 	* Makefile: Reworked to make it easy for people other than me to build
 1705 	  and install.
 1706 	* cpuid.spec: Used new Makefile organization
 1707 	* Makefile: Fixed production of spec file so that it's possible to
 1708 	  rebuild with the srpm without having to specify %version and
 1709 	  %release.
 1710 
 1711 Mon Feb  6 2006 Todd Allen <todd.allen@etallen.com>
 1712 	* Initial public release.