"Fossies" - the Fresh Open Source Software Archive

Member "alec64-1.13/src/6502.h" (4 Aug 1996, 5031 Bytes) of package /linux/misc/old/alec64-1.13.tar.gz:


As a special service "Fossies" has tried to format the requested source page into HTML format using (guessed) C and C++ source code syntax highlighting (style: standard) with prefixed line numbers and code folding option. Alternatively you can here view or download the uninterpreted source code file.

    1 /*
    2  *  The C64 emulator
    3  *
    4  *  Copyright 1992,1996 by ALE.
    5  *  written by Lutz Sammer.
    6  *
    7  *  6502/6510 Emulation Headerfile
    8  *-----------------------------------------------------------------------------
    9  * $Id: 6502.h,v 1.7 1996/05/23 02:26:08 root Exp root $
   10  * $Log: 6502.h,v $
   11  * Revision 1.7  1996/05/23 02:26:08  root
   12  * New IRQ handling writen.
   13  *
   14  * Revision 1.6  1996/04/08 16:25:44  johns
   15  * Commented, Cleaned up
   16  *
   17  * Revision 1.5  1994/06/02  14:56:27  johns
   18  * version 1.07 ci
   19  *
   20  * Revision 1.4  1992/07/28  19:47:42  johns
   21  * Change of 6502 register names.
   22  *
   23  * Revision 1.1  1992/07/11  17:57:22  johns
   24  * Initial revision
   25  *
   26  *-----------------------------------------------------------------------------
   27  */
   28 
   29 #ifndef __6502_H__  /* { */
   30 #define __6502_H__
   31 
   32 /*
   33 **  Processor instructions
   34 */
   35 enum Instructions {
   36     BRK,    ORA_IX, ILL02,  ILL03,  ILL04,  ORA_D,  ASL_D,  ILL07,
   37     PHP,    ORA_IM, ASL,    ILL0B,  ILL0C,  ORA_A,  ASL_A,  ILL0F,
   38 
   39     BPL,    ORA_IY, ILL12,  ILL13,  ILL14,  ORA_DX, ASL_DX, ILL17,
   40     CLC,    ORA_AY, ILL1A,  ILL1B,  ILL1C,  ORA_AX, ASL_AX, ILL1F,
   41 
   42     JSR,    AND_IX, ILL22,  ILL23,  BIT_D,  AND_D,  ROL_D,  ILL27,
   43     PLP,    AND_IM, ROL,    ILL2B,  BIT_A,  AND_A,  ROL_A,  ILL2F,
   44 
   45     BMI,    AND_IY, ILL32,  ILL33,  ILL34,  AND_DX, ROL_DX, ILL37,
   46     SEC,    AND_AY, ILL3A,  ILL3B,  ILL3C,  AND_AX, ROL_AX, ILL3F,
   47 
   48     RTI,    EOR_IX, ILL42,  ILL43,  ILL44,  EOR_D,  LSR_D,  ILL47,
   49     PHA,    EOR_IM, LSR,    ILL4B,  JMP_A,  EOR_A,  LSR_A,  ILL4F,
   50 
   51     BVC,    EOR_IY, ILL52,  ILL53,  ILL54,  EOR_DX, LSR_DX, ILL57,
   52     CLI,    EOR_AY, ILL5A,  ILL5B,  ILL5C,  EOR_AX, LSR_AX, ILL5F,
   53 
   54     RTS,    ADC_IX, ILL62,  ILL63,  ILL64,  ADC_D,  ROR_D,  ILL67,
   55     PLA,    ADC_IM, ROR,    ILL6B,  JMP_AI, ADC_A,  ROR_A,  ILL6F,
   56 
   57     BVS,    ADC_IY, ILL72,  ILL73,  ILL74,  ADC_DX, ROR_DX, ILL77,
   58     SEI,    ADC_AY, ILL7A,  ILL7B,  ILL7C,  ADC_AX, ROR_AX, ILL7F,
   59 
   60     ILL80,  STA_IX, ILL82,  ILL83,  STY_D,  STA_D,  STX_D,  ILL87,
   61     DEY,    ILL89,  TXA,    ILL8B,  STY_A,  STA_A,  STX_A,  ILL8F,
   62 
   63     BCC,    STA_IY, ILL92,  ILL93,  STY_DX, STA_DX, STX_DY, ILL97,
   64     TYA,    STA_AY, TXS,    ILL9B,  ILL9C,  STA_AX, ILL9E,  ILL9F,
   65 
   66     LDY_IM, LDA_IX, LDX_IM, ILLA3,  LDY_D,  LDA_D,  LDX_D,  ILLA7,
   67     TAY,    LDA_IM, TAX,    ILLAB,  LDY_A,  LDA_A,  LDX_A,  ILLAF,
   68 
   69     BCS,    LDA_IY, ILLB2,  ILLB3,  LDY_DX, LDA_DX, LDX_DY, ILLB7,
   70     CLV,    LDA_AY, TSX,    ILLBB,  LDY_AX, LDA_AX, LDX_AY, ILLBF,
   71 
   72     CPY_IM, CMP_IX, ILLC2,  ILLC3,  CPY_D,  CMP_D,  DEC_D,  ILLC7,
   73     INY,    CMP_IM, DEX,    ILLCB,  CPY_A,  CMP_A,  DEC_A,  ILLCF,
   74 
   75     BNE,    CMP_IY, ILLD2,  ILLD3,  ILLD4,  CMP_DX, DEC_DX, ILLD7,
   76     CLD,    CMP_AY, ILLDA,  ILLDB,  ILLDC,  CMP_AX, DEC_AX, ILLDF,
   77 
   78     CPX_IM, SBC_IX, ILLE2,  ILLE3,  CPX_D,  SBC_D,  INC_D,  ILLE7,
   79     INX,    SBC_IM, NOP,    ILLEB,  CPX_A,  SBC_A,  INC_A,  ILLEF,
   80 
   81     BEQ,    SBC_IY, ILLF2,  ILLF3,  ILLF4,  SBC_DX, INC_DX, ILLF7,
   82     SED,    SBC_AY, ILLFA,  ILLFB,  ILLFC,  SBC_AX, INC_AX, ILLFF
   83 };
   84 
   85 /*
   86 **  Processor flags
   87 */
   88 #define FLAG_CARRY  1
   89 #define FLAG_ZERO   2
   90 #define FLAG_INTERRUPT  4
   91 #define FLAG_DECIMAL    8
   92 #define FLAG_BREAK  16
   93 #define FLAG_UNDEFINED  32
   94 #define FLAG_OVERFLOW   64
   95 #define FLAG_NEGATIVE   128
   96 
   97 /*
   98 **  Processor vectors
   99 */
  100 #define NMI_VECTOR 0xFFFA
  101 #define RST_VECTOR 0xFFFC
  102 #define IRQ_VECTOR 0xFFFE
  103 
  104 /*
  105 **  C emulated byte register.
  106 **      This is used to avoid byte -> long conversions.
  107 */
  108 union reg6502 {
  109     unsigned char   Byte[4];    /* ENDIAN Low significant byte !! */
  110     unsigned        Int;
  111 };
  112 
  113 /*
  114 **  LowByte:    access low byte of an integer.
  115 */
  116 #ifdef BIG_ENDIAN
  117 #   define LowByte(v)   ((v).Byte[3])
  118 #endif
  119 #ifdef LITTLE_ENDIAN
  120 #   define LowByte(v)   ((v).Byte[0])
  121 #endif
  122 
  123 /*
  124 **  Integer:    access byte register as integer.
  125 */
  126 #define Integer(v)  ((v).Int)
  127 
  128 /*
  129 **  Processor registers
  130 */
  131 extern  union reg6502   GlobalRegA;
  132 extern  union reg6502   GlobalRegX;
  133 extern  union reg6502   GlobalRegY;
  134 extern  union reg6502   GlobalRegP;
  135 extern  union reg6502   GlobalRegS;
  136 extern  unsigned    GlobalRegPC;
  137 
  138 /*
  139 **  Hardware emulation
  140 */
  141 extern  int     IrqLine;        /* Interupt line state */
  142 extern  int     IrqFlag;        /* Interupt flag */
  143 extern  unsigned    Cycle;          /* Current 6502 cycle */
  144 extern  unsigned    Action;         /* Next processor action */
  145 #ifdef NEW_ACTION
  146 extern  unsigned    HwAction;       /* Next hardware action */
  147 #endif
  148 extern  void        (*ActionFunction)(void);/* Hardware action function */
  149 
  150 /*-----------------------------------------------------------------------------
  151  *  Stack (0x100-0x1FF) access:
  152  *---------------------------------------------------------------------------*/
  153 
  154 /*
  155 **  Read word from stack used by monitor and disassembler.
  156 */
  157 #define RWStack(x) \
  158     (Ram[0x100+((x)&0xFF)]|(Ram[0x100+(((x)+1)&0xFF)]<<8))
  159 
  160 /*
  161 **  Push a byte on processor stack.
  162 */
  163 #define PushB(x) \
  164     do {                        \
  165     Ram[0x100+Integer(RegS)]=(x); LowByte(RegS)--;  \
  166     } while( 0 )
  167 
  168 /*
  169 **  Pop a byte from processor stack.
  170 */
  171 #define PopB(x) \
  172     (++LowByte(RegS), (x)=Ram[0x100+Integer(RegS)])
  173 
  174 /*
  175 **  Push a word on processor stack.
  176 */
  177 #define PushW(x) \
  178     do {                        \
  179     PushB((x)>>8); PushB((x)&0xFF);         \
  180     } while( 0 )
  181 
  182 /*
  183 **  Pop a word from processor stack.
  184 */
  185 #define PopW(x) \
  186     do {                        \
  187     register unsigned __w;              \
  188     ++LowByte(RegS);                \
  189     __w=Ram[0x100+Integer(RegS)];           \
  190     ++LowByte(RegS);                \
  191     __w|=Ram[0x100+Integer(RegS)]<<8;       \
  192     (x)=__w;                    \
  193     } while( 0 )
  194 
  195 #endif  /* } !__6502_H__ */