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Source code changes of the file "target/arm/helper.c" between
qemu-6.0.0-rc1.tar.xz and qemu-6.0.0-rc2.tar.xz

About: QEMU is a generic machine/processor emulator and virtualizer. Release candidate.

helper.c  (qemu-6.0.0-rc1.tar.xz):helper.c  (qemu-6.0.0-rc2.tar.xz)
skipping to change at line 41 skipping to change at line 41
#include "qapi/qapi-commands-machine-target.h" #include "qapi/qapi-commands-machine-target.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "qemu/guest-random.h" #include "qemu/guest-random.h"
#ifdef CONFIG_TCG #ifdef CONFIG_TCG
#include "arm_ldst.h" #include "arm_ldst.h"
#include "exec/cpu_ldst.h" #include "exec/cpu_ldst.h"
#include "semihosting/common-semi.h" #include "semihosting/common-semi.h"
#endif #endif
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
#define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx, MMUAccessType access_type, ARMMMUIdx mmu_idx,
bool s1_is_el0, bool s1_is_el0,
hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
target_ulong *page_size_ptr, target_ulong *page_size_ptr,
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
__attribute__((nonnull)); __attribute__((nonnull));
skipping to change at line 1149 skipping to change at line 1150
PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
PMXEVTYPER_M | PMXEVTYPER_MT | \ PMXEVTYPER_M | PMXEVTYPER_MT | \
PMXEVTYPER_EVTCOUNT) PMXEVTYPER_EVTCOUNT)
#define PMCCFILTR 0xf8000000 #define PMCCFILTR 0xf8000000
#define PMCCFILTR_M PMXEVTYPER_M #define PMCCFILTR_M PMXEVTYPER_M
#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
static inline uint32_t pmu_num_counters(CPUARMState *env) static inline uint32_t pmu_num_counters(CPUARMState *env)
{ {
ARMCPU *cpu = env_archcpu(env); return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT;
} }
/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
static inline uint64_t pmu_counter_mask(CPUARMState *env) static inline uint64_t pmu_counter_mask(CPUARMState *env)
{ {
return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
} }
typedef struct pm_event { typedef struct pm_event {
uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */
skipping to change at line 5755 skipping to change at line 5754
.resetfn = gt_hyp_timer_reset, .resetfn = gt_hyp_timer_reset,
.readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write },
{ .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
.type = ARM_CP_IO, .type = ARM_CP_IO,
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
.access = PL2_RW, .access = PL2_RW,
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl),
.resetvalue = 0, .resetvalue = 0,
.writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
#endif #endif
/* The only field of MDCR_EL2 that has a defined architectural reset value
* is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
*/
{ .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
.access = PL2_RW, .resetvalue = PMCR_NUM_COUNTERS,
.fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
{ .name = "HPFAR", .state = ARM_CP_STATE_AA32, { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
.access = PL2_RW, .accessfn = access_el3_aa32ns, .access = PL2_RW, .accessfn = access_el3_aa32ns,
.fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
{ .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
.access = PL2_RW, .access = PL2_RW,
.fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
{ .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
.cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
skipping to change at line 6684 skipping to change at line 6690
} }
} }
static void define_pmu_regs(ARMCPU *cpu) static void define_pmu_regs(ARMCPU *cpu)
{ {
/* /*
* v7 performance monitor control register: same implementor * v7 performance monitor control register: same implementor
* field as main ID register, and we implement four counters in * field as main ID register, and we implement four counters in
* addition to the cycle count register. * addition to the cycle count register.
*/ */
unsigned int i, pmcrn = pmu_num_counters(&cpu->env); unsigned int i, pmcrn = PMCR_NUM_COUNTERS;
ARMCPRegInfo pmcr = { ARMCPRegInfo pmcr = {
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
.access = PL0_RW, .access = PL0_RW,
.type = ARM_CP_IO | ARM_CP_ALIAS, .type = ARM_CP_IO | ARM_CP_ALIAS,
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
.accessfn = pmreg_access, .writefn = pmcr_write, .accessfn = pmreg_access, .writefn = pmcr_write,
.raw_writefn = raw_write, .raw_writefn = raw_write,
}; };
ARMCPRegInfo pmcr64 = { ARMCPRegInfo pmcr64 = {
.name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
.access = PL0_RW, .accessfn = pmreg_access, .access = PL0_RW, .accessfn = pmreg_access,
.type = ARM_CP_IO, .type = ARM_CP_IO,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
.resetvalue = cpu->isar.reset_pmcr_el0, .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) |
PMCRLC,
.writefn = pmcr_write, .raw_writefn = raw_write, .writefn = pmcr_write, .raw_writefn = raw_write,
}; };
define_one_arm_cp_reg(cpu, &pmcr); define_one_arm_cp_reg(cpu, &pmcr);
define_one_arm_cp_reg(cpu, &pmcr64); define_one_arm_cp_reg(cpu, &pmcr64);
for (i = 0; i < pmcrn; i++) { for (i = 0; i < pmcrn; i++) {
char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i); char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i);
char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i); char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i);
char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i); char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i);
char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i); char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i);
ARMCPRegInfo pmev_regs[] = { ARMCPRegInfo pmev_regs[] = {
{ .name = pmevcntr_name, .cp = 15, .crn = 14, { .name = pmevcntr_name, .cp = 15, .crn = 14,
.crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
skipping to change at line 7820 skipping to change at line 7826
.access = PL2_RW, .accessfn = access_el3_aa32ns, .access = PL2_RW, .accessfn = access_el3_aa32ns,
.resetvalue = vmpidr_def, .type = ARM_CP_ALIAS, .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
.fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) }, .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
{ .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
.access = PL2_RW, .access = PL2_RW,
.resetvalue = vmpidr_def, .resetvalue = vmpidr_def,
.fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
REGINFO_SENTINEL REGINFO_SENTINEL
}; };
/*
* The only field of MDCR_EL2 that has a defined architectural reset
* value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
*/
ARMCPRegInfo mdcr_el2 = {
.name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
.access = PL2_RW, .resetvalue = pmu_num_counters(env),
.fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2),
};
define_one_arm_cp_reg(cpu, &mdcr_el2);
define_arm_cp_regs(cpu, vpidr_regs); define_arm_cp_regs(cpu, vpidr_regs);
define_arm_cp_regs(cpu, el2_cp_reginfo); define_arm_cp_regs(cpu, el2_cp_reginfo);
if (arm_feature(env, ARM_FEATURE_V8)) { if (arm_feature(env, ARM_FEATURE_V8)) {
define_arm_cp_regs(cpu, el2_v8_cp_reginfo); define_arm_cp_regs(cpu, el2_v8_cp_reginfo);
} }
if (cpu_isar_feature(aa64_sel2, cpu)) { if (cpu_isar_feature(aa64_sel2, cpu)) {
define_arm_cp_regs(cpu, el2_sec_cp_reginfo); define_arm_cp_regs(cpu, el2_sec_cp_reginfo);
} }
/* RVBAR_EL2 is only implemented if EL2 is the highest EL */ /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
if (!arm_feature(env, ARM_FEATURE_EL3)) { if (!arm_feature(env, ARM_FEATURE_EL3)) {
 End of changes. 7 change blocks. 
17 lines changed or deleted 12 lines changed or added

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