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Source code changes of the file "target/arm/cpu_tcg.c" between
qemu-6.0.0-rc1.tar.xz and qemu-6.0.0-rc2.tar.xz

About: QEMU is a generic machine/processor emulator and virtualizer. Release candidate.

cpu_tcg.c  (qemu-6.0.0-rc1.tar.xz):cpu_tcg.c  (qemu-6.0.0-rc2.tar.xz)
skipping to change at line 304 skipping to change at line 304
cpu->isar.id_isar1 = 0x12112111; cpu->isar.id_isar1 = 0x12112111;
cpu->isar.id_isar2 = 0x21232031; cpu->isar.id_isar2 = 0x21232031;
cpu->isar.id_isar3 = 0x11112131; cpu->isar.id_isar3 = 0x11112131;
cpu->isar.id_isar4 = 0x00111142; cpu->isar.id_isar4 = 0x00111142;
cpu->isar.dbgdidr = 0x15141000; cpu->isar.dbgdidr = 0x15141000;
cpu->clidr = (1 << 27) | (2 << 24) | 3; cpu->clidr = (1 << 27) | (2 << 24) | 3;
cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
cpu->reset_auxcr = 2; cpu->reset_auxcr = 2;
cpu->isar.reset_pmcr_el0 = 0x41002000;
define_arm_cp_regs(cpu, cortexa8_cp_reginfo); define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
} }
static const ARMCPRegInfo cortexa9_cp_reginfo[] = { static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
/* /*
* power_control should be set to maximum latency. Again, * power_control should be set to maximum latency. Again,
* default to 0 and set by private hook * default to 0 and set by private hook
*/ */
{ .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .resetvalue = 0, .access = PL1_RW, .resetvalue = 0,
skipping to change at line 377 skipping to change at line 376
cpu->isar.id_mmfr3 = 0x00002111; cpu->isar.id_mmfr3 = 0x00002111;
cpu->isar.id_isar0 = 0x00101111; cpu->isar.id_isar0 = 0x00101111;
cpu->isar.id_isar1 = 0x13112111; cpu->isar.id_isar1 = 0x13112111;
cpu->isar.id_isar2 = 0x21232041; cpu->isar.id_isar2 = 0x21232041;
cpu->isar.id_isar3 = 0x11112131; cpu->isar.id_isar3 = 0x11112131;
cpu->isar.id_isar4 = 0x00111142; cpu->isar.id_isar4 = 0x00111142;
cpu->isar.dbgdidr = 0x35141000; cpu->isar.dbgdidr = 0x35141000;
cpu->clidr = (1 << 27) | (1 << 24) | 3; cpu->clidr = (1 << 27) | (1 << 24) | 3;
cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
cpu->isar.reset_pmcr_el0 = 0x41093000;
define_arm_cp_regs(cpu, cortexa9_cp_reginfo); define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
} }
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{ {
MachineState *ms = MACHINE(qdev_get_machine()); MachineState *ms = MACHINE(qdev_get_machine());
/* /*
* Linux wants the number of processors from here. * Linux wants the number of processors from here.
skipping to change at line 448 skipping to change at line 446
cpu->isar.id_isar0 = 0x02101110; cpu->isar.id_isar0 = 0x02101110;
cpu->isar.id_isar1 = 0x13112111; cpu->isar.id_isar1 = 0x13112111;
cpu->isar.id_isar2 = 0x21232041; cpu->isar.id_isar2 = 0x21232041;
cpu->isar.id_isar3 = 0x11112131; cpu->isar.id_isar3 = 0x11112131;
cpu->isar.id_isar4 = 0x10011142; cpu->isar.id_isar4 = 0x10011142;
cpu->isar.dbgdidr = 0x3515f005; cpu->isar.dbgdidr = 0x3515f005;
cpu->clidr = 0x0a200023; cpu->clidr = 0x0a200023;
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
cpu->isar.reset_pmcr_el0 = 0x41072000;
define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
} }
static void cortex_a15_initfn(Object *obj) static void cortex_a15_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
cpu->dtb_compatible = "arm,cortex-a15"; cpu->dtb_compatible = "arm,cortex-a15";
set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_V7VE);
set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_NEON);
skipping to change at line 491 skipping to change at line 488
cpu->isar.id_isar0 = 0x02101110; cpu->isar.id_isar0 = 0x02101110;
cpu->isar.id_isar1 = 0x13112111; cpu->isar.id_isar1 = 0x13112111;
cpu->isar.id_isar2 = 0x21232041; cpu->isar.id_isar2 = 0x21232041;
cpu->isar.id_isar3 = 0x11112131; cpu->isar.id_isar3 = 0x11112131;
cpu->isar.id_isar4 = 0x10011142; cpu->isar.id_isar4 = 0x10011142;
cpu->isar.dbgdidr = 0x3515f021; cpu->isar.dbgdidr = 0x3515f021;
cpu->clidr = 0x0a200023; cpu->clidr = 0x0a200023;
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
cpu->isar.reset_pmcr_el0 = 0x410F3000;
define_arm_cp_regs(cpu, cortexa15_cp_reginfo); define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
} }
static void cortex_m0_initfn(Object *obj) static void cortex_m0_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V6); set_feature(&cpu->env, ARM_FEATURE_V6);
set_feature(&cpu->env, ARM_FEATURE_M); set_feature(&cpu->env, ARM_FEATURE_M);
cpu->midr = 0x410cc200; cpu->midr = 0x410cc200;
skipping to change at line 724 skipping to change at line 720
cpu->isar.id_mmfr3 = 0x0211; cpu->isar.id_mmfr3 = 0x0211;
cpu->isar.id_isar0 = 0x02101111; cpu->isar.id_isar0 = 0x02101111;
cpu->isar.id_isar1 = 0x13112111; cpu->isar.id_isar1 = 0x13112111;
cpu->isar.id_isar2 = 0x21232141; cpu->isar.id_isar2 = 0x21232141;
cpu->isar.id_isar3 = 0x01112131; cpu->isar.id_isar3 = 0x01112131;
cpu->isar.id_isar4 = 0x0010142; cpu->isar.id_isar4 = 0x0010142;
cpu->isar.id_isar5 = 0x0; cpu->isar.id_isar5 = 0x0;
cpu->isar.id_isar6 = 0x0; cpu->isar.id_isar6 = 0x0;
cpu->mp_is_up = true; cpu->mp_is_up = true;
cpu->pmsav7_dregion = 16; cpu->pmsav7_dregion = 16;
cpu->isar.reset_pmcr_el0 = 0x41151800;
define_arm_cp_regs(cpu, cortexr5_cp_reginfo); define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
} }
static void cortex_r5f_initfn(Object *obj) static void cortex_r5f_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
cortex_r5_initfn(obj); cortex_r5_initfn(obj);
cpu->isar.mvfr0 = 0x10110221; cpu->isar.mvfr0 = 0x10110221;
cpu->isar.mvfr1 = 0x00000011; cpu->isar.mvfr1 = 0x00000011;
 End of changes. 5 change blocks. 
5 lines changed or deleted 0 lines changed or added

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