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Source code changes of the file "target/arm/cpu64.c" between
qemu-6.0.0-rc1.tar.xz and qemu-6.0.0-rc2.tar.xz

About: QEMU is a generic machine/processor emulator and virtualizer. Release candidate.

cpu64.c  (qemu-6.0.0-rc1.tar.xz):cpu64.c  (qemu-6.0.0-rc2.tar.xz)
skipping to change at line 143 skipping to change at line 143
cpu->isar.id_aa64mmfr0 = 0x00001124; cpu->isar.id_aa64mmfr0 = 0x00001124;
cpu->isar.dbgdidr = 0x3516d000; cpu->isar.dbgdidr = 0x3516d000;
cpu->clidr = 0x0a200023; cpu->clidr = 0x0a200023;
cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
cpu->dcz_blocksize = 4; /* 64 bytes */ cpu->dcz_blocksize = 4; /* 64 bytes */
cpu->gic_num_lrs = 4; cpu->gic_num_lrs = 4;
cpu->gic_vpribits = 5; cpu->gic_vpribits = 5;
cpu->gic_vprebits = 5; cpu->gic_vprebits = 5;
cpu->isar.reset_pmcr_el0 = 0x41013000;
define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
} }
static void aarch64_a53_initfn(Object *obj) static void aarch64_a53_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
cpu->dtb_compatible = "arm,cortex-a53"; cpu->dtb_compatible = "arm,cortex-a53";
set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_V8);
set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_NEON);
skipping to change at line 197 skipping to change at line 196
cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
cpu->isar.dbgdidr = 0x3516d000; cpu->isar.dbgdidr = 0x3516d000;
cpu->clidr = 0x0a200023; cpu->clidr = 0x0a200023;
cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
cpu->dcz_blocksize = 4; /* 64 bytes */ cpu->dcz_blocksize = 4; /* 64 bytes */
cpu->gic_num_lrs = 4; cpu->gic_num_lrs = 4;
cpu->gic_vpribits = 5; cpu->gic_vpribits = 5;
cpu->gic_vprebits = 5; cpu->gic_vprebits = 5;
cpu->isar.reset_pmcr_el0 = 0x41033000;
define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
} }
static void aarch64_a72_initfn(Object *obj) static void aarch64_a72_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
cpu->dtb_compatible = "arm,cortex-a72"; cpu->dtb_compatible = "arm,cortex-a72";
set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_V8);
set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_NEON);
skipping to change at line 249 skipping to change at line 247
cpu->isar.id_aa64mmfr0 = 0x00001124; cpu->isar.id_aa64mmfr0 = 0x00001124;
cpu->isar.dbgdidr = 0x3516d000; cpu->isar.dbgdidr = 0x3516d000;
cpu->clidr = 0x0a200023; cpu->clidr = 0x0a200023;
cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
cpu->dcz_blocksize = 4; /* 64 bytes */ cpu->dcz_blocksize = 4; /* 64 bytes */
cpu->gic_num_lrs = 4; cpu->gic_num_lrs = 4;
cpu->gic_vpribits = 5; cpu->gic_vpribits = 5;
cpu->gic_vprebits = 5; cpu->gic_vprebits = 5;
cpu->isar.reset_pmcr_el0 = 0x41023000;
define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
} }
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
{ {
/* /*
* If any vector lengths are explicitly enabled with sve<N> properties, * If any vector lengths are explicitly enabled with sve<N> properties,
* then all other lengths are implicitly disabled. If sve-max-vq is * then all other lengths are implicitly disabled. If sve-max-vq is
* specified then it is the same as explicitly enabling all lengths * specified then it is the same as explicitly enabling all lengths
* up to and including the specified maximum, which means all larger * up to and including the specified maximum, which means all larger
 End of changes. 3 change blocks. 
3 lines changed or deleted 0 lines changed or added

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