"Fossies" - the Fresh Open Source Software Archive  

Source code changes of the file "cyborg/tests/unit/fake_extarq.py" between
openstack-cyborg-8.0.0.tar.gz and openstack-cyborg-9.0.0.tar.gz

About: OpenStack Cyborg provides a general purpose management framework for acceleration resources.
The "Zed" series (latest release).

fake_extarq.py  (openstack-cyborg-8.0.0):fake_extarq.py  (openstack-cyborg-9.0.0)
skipping to change at line 291 skipping to change at line 291
inst_binding = {'path': '/instance_uuid', 'op': 'add', inst_binding = {'path': '/instance_uuid', 'op': 'add',
'value': arqs[0]['instance_uuid']} 'value': arqs[0]['instance_uuid']}
device_rp_uuid = 'fb16c293-5739-4c84-8590-926f9ab16669' device_rp_uuid = 'fb16c293-5739-4c84-8590-926f9ab16669'
patch_list = {} patch_list = {}
for newarq in arqs: for newarq in arqs:
dev_uuid = device_rp_uuid if same_device else newarq['device_rp_uuid'] dev_uuid = device_rp_uuid if same_device else newarq['device_rp_uuid']
dev_binding = {'path': '/device_rp_uuid', 'op': 'add', dev_binding = {'path': '/device_rp_uuid', 'op': 'add',
'value': dev_uuid} 'value': dev_uuid}
patch_list[newarq['uuid']] = [host_binding, inst_binding, dev_binding] patch_list[newarq['uuid']] = [host_binding, inst_binding, dev_binding]
return patch_list, device_rp_uuid return patch_list, device_rp_uuid
def get_fake_xilinx_fpga_extarq_objs():
arqs = [
{"uuid": 'b8c19eb2-e03c-47b4-b7cf-ced6086b2d11',
"device_profile_group_id": 0,
"state": "Initial",
"device_profile_name": "fake_xilinx_fpga_dp",
"hostname": "myhost",
"instance_uuid": "5922a70f-1e06-4cfd-88dd-a332120d7144",
"attach_handle_type": "PCI",
# attach_handle info should vary across ARQs but ignored for testing
"attach_handle_info": {
"bus": "3b",
"device": "00",
"domain": "0000",
"function": "0"
},
"device_profile_group": {
"trait:CUSTOM_FPGA_XILINX": "required",
"resources:FPGA": "1",
"trait:CUSTOM_FPGA_PRODUCT_ID_5000": "required"}
},
{"uuid": '012955c7-90f9-45a9-bb7d-7c2907d8997f',
"device_profile_group_id": 1,
"state": "Initial",
"device_profile_name": "fake_xilinx_fpga_dp",
"hostname": "myhost",
"instance_uuid": "5922a70f-1e06-4cfd-88dd-a332120d7144",
"attach_handle_type": "PCI",
# attach_handle info should vary across ARQs but ignored for testing
"attach_handle_info": {
"bus": "3b",
"device": "00",
"domain": "0000",
"function": "1"
},
"device_profile_group": {
"trait:CUSTOM_FPGA_XILINX": "required",
"resources:FPGA": "1",
"trait:CUSTOM_FPGA_PRODUCT_ID_5000": "required"}
},
]
return list(map(_convert_from_dict_to_obj, arqs))
 End of changes. 1 change blocks. 
0 lines changed or deleted 0 lines changed or added

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