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Source code changes of the file "tools/i2cget.8" between
i2c-tools-4.2.tar.gz and i2c-tools-4.3.tar.gz

About: i2c-tools are an heterogeneous set of I2C tools for Linux (originally part of the lm-sensors package).

i2cget.8  (i2c-tools-4.2):i2cget.8  (i2c-tools-4.3)
I2CGET(8) System Manager's Manual I2CGET(8) I2CGET(8) System Manager's Manual I2CGET(8)
NAME NAME
i2cget - read from I2C/SMBus chip registers i2cget - read from I2C/SMBus chip registers
SYNOPSIS SYNOPSIS
i2cget [-f] [-y] [-a] i2cbus chip-address [data-address [mode]] i2cget [-f] [-y] [-a] i2cbus chip-address [data-address [mode [length]]]
i2cget -V i2cget -V
DESCRIPTION DESCRIPTION
i2cget is a small helper program to read registers visible through the I2 C bus (or SMBus). i2cget is a small helper program to read registers visible through the I2 C bus (or SMBus).
OPTIONS OPTIONS
-V Display the version and exit. -V Display the version and exit.
-f Force access to the device even if it is already busy. By default , i2cget will refuse to access a -f Force access to the device even if it is already busy. By default , i2cget will refuse to access a
device which is already under the control of a kernel driver. Usin g this flag is dangerous, it can device which is already under the control of a kernel driver. Usin g this flag is dangerous, it can
skipping to change at line 34 skipping to change at line 34
-a Allow using addresses between 0x00 - 0x07 and 0x78 - 0x7f. Not rec ommended. -a Allow using addresses between 0x00 - 0x07 and 0x78 - 0x7f. Not rec ommended.
There are two required options to i2cget. i2cbus indicates the number or name of the I2C bus to be There are two required options to i2cget. i2cbus indicates the number or name of the I2C bus to be
scanned. This number should correspond to one of the busses listed by i 2cdetect -l. chip-address speci- scanned. This number should correspond to one of the busses listed by i 2cdetect -l. chip-address speci-
fies the address of the chip on that bus, and is an integer between 0x08 and 0x77. fies the address of the chip on that bus, and is an integer between 0x08 and 0x77.
data-address specifies the address on that chip to read from, and is an i nteger between 0x00 and 0xFF. If data-address specifies the address on that chip to read from, and is an i nteger between 0x00 and 0xFF. If
omitted, the currently active register will be read (if that makes sense for the considered chip). omitted, the currently active register will be read (if that makes sense for the considered chip).
The mode parameter, if specified, is one of the letters b, w or c, corr The mode parameter, if specified, is one of the letters b, w, c, or i, co
esponding to a read byte data, a rresponding to a read byte data,
read word data or a write byte/read byte transaction, respectively. A p c a read word data, a write byte/read byte, an SMBus block read, or an I2C
an also be appended to the mode block read transaction, respec-
parameter to enable PEC. If the mode parameter is omitted, i2cget defau tively. A p can also be appended to the mode parameter to enable PEC, ex
lts to a read byte data transac- cept for I2C block transactions.
tion, unless data-address is also omitted, in which case the default (and If the mode parameter is omitted, i2cget defaults to a read byte data tra
only valid) transaction is a nsaction, unless data-address is
single read byte. also omitted, in which case the default (and only valid) transaction is a
single read byte.
The length parameter, if applicable and specified, sets the length of the
block transaction. Valid values
are between 1 and 32. Default value is 32.
WARNING WARNING
i2cget can be extremely dangerous if used improperly. I2C and SMBus ar i2cget can be extremely dangerous if used improperly. I2C and SMBus are d
e designed in such a way that an esigned in such a way that an
SMBus read transaction can be seen as a write transaction by certain chip SMBus read transaction can be seen as a write transaction by certain chi
s. This is particularly true if ps. This is particularly true if
setting mode to cp (write byte/read byte with PEC). Be extremely careful using this program. setting mode to cp (write byte/read byte with PEC). Be extremely careful using this program.
EXAMPLES EXAMPLES
Get the value of 8-bit register 0x11 of the I2C device at 7-bit address 0 x2d on bus 1 (i2c-1), after user Get the value of 8-bit register 0x11 of the I2C device at 7-bit address 0 x2d on bus 1 (i2c-1), after user
confirmation: confirmation:
# i2cget 1 0x2d 0x11 # i2cget 1 0x2d 0x11
Get the value of 16-bit register 0x00 of the I2C device at 7-bit address 0x48 on bus 1 (i2c-1), after Get the value of 16-bit register 0x00 of the I2C device at 7-bit addr ess 0x48 on bus 1 (i2c-1), after
user confirmation: user confirmation:
# i2cget 1 0x48 0x00 w # i2cget 1 0x48 0x00 w
Set the internal pointer register of a 24C02 EEPROM at 7-bit address 0x5 0 on bus 9 (i2c-9) to 0x00, then Set the internal pointer register of a 24C02 EEPROM at 7-bit address 0x50 on bus 9 (i2c-9) to 0x00, then
read the first 2 bytes from that EEPROM: read the first 2 bytes from that EEPROM:
# i2cset -y 9 0x50 0x00 ; i2cget -y 9 0x50 ; i2cget -y 9 0x50 # i2cset -y 9 0x50 0x00 ; i2cget -y 9 0x50 ; i2cget -y 9 0x50
This assumes that the device automatically increments its internal pointe This assumes that the device automatically increments its internal poi
r register on every read, and nter register on every read, and
supports read byte transactions (read without specifying the register supports read byte transactions (read without specifying the register add
address, "Receive Byte" in SMBus ress, "Receive Byte" in SMBus
terminology.) Most EEPROM devices behave that way. Note that this is onl y safe as long as nobody else is terminology.) Most EEPROM devices behave that way. Note that this is onl y safe as long as nobody else is
accessing the I2C device at the same time. A safer approach would be to use a "Read Word" SMBus transac- accessing the I2C device at the same time. A safer approach would be to u se a "Read Word" SMBus transac-
tion instead, or an I2C Block Read transaction to read more than 2 bytes. tion instead, or an I2C Block Read transaction to read more than 2 bytes.
Set the internal pointer register of a 24C32 EEPROM at 7-bit address 0x53 on bus 9 (i2c-9) to 0x0000, Set the internal pointer register of a 24C32 EEPROM at 7-bit address 0x53 on bus 9 (i2c-9) to 0x0000,
then read the first 2 bytes from that EEPROM: then read the first 2 bytes from that EEPROM:
# i2cset -y 9 0x53 0x00 0x00 ; i2cget -y 9 0x53 ; i2cget -y 9 0x53 # i2cset -y 9 0x53 0x00 0x00 ; i2cget -y 9 0x53 ; i2cget -y 9 0x53
This again assumes that the device automatically increments its internal pointer register on every read, This again assumes that the device automatically increments its internal pointer register on every read,
and supports read byte transactions. While the previous example was for a small EEPROM using 8-bit inter- and supports read byte transactions. While the previous example was for a small EEPROM using 8-bit inter-
nal addressing, this example is for a larger EEPROM using 16-bit internal addressing. Beware that running nal addressing, this example is for a larger EEPROM using 16-bit internal addressing. Beware that running
this command on a small EEPROM using 8-bit internal addressing would actu ally write 0x00 to the first this command on a small EEPROM using 8-bit internal addressing would actually write 0x00 to the first
byte of that EEPROM. The safety concerns raised above still stand, howeve r in this case there is no SMBus byte of that EEPROM. The safety concerns raised above still stand, howeve r in this case there is no SMBus
equivalent, so this is the only way to read data from a large EEPROM if y our master isn't fully I2C capa- equivalent, so this is the only way to read data from a large EEPROM if y our master isn't fully I2C capa-
ble. With a fully I2C capable master, you would use i2ctransfer to achie ve the same in a safe and faster ble. With a fully I2C capable master, you would use i2ctransfer to achiev e the same in a safe and faster
way. way.
Read the first 8 bytes of an EEPROM device at 7-bit address 0x50 on bus 4
(i2c-4):
# i2cget -y 4 0x50 0x00 i 8
BUGS BUGS
To report bugs or send fixes, please write to the Linux I2C mailing list <linux-i2c@vger.kernel.org> with To report bugs or send fixes, please write to the Linux I2C mailing list <linux-i2c@vger.kernel.org> with
Cc to the current maintainer: Jean Delvare <jdelvare@suse.de>. Cc to the current maintainer: Jean Delvare <jdelvare@suse.de>.
SEE ALSO SEE ALSO
i2cdetect(8), i2cdump(8), i2cset(8), i2ctransfer(8) i2cdetect(8), i2cdump(8), i2cset(8), i2ctransfer(8)
AUTHOR AUTHOR
Jean Delvare Jean Delvare
This manual page was strongly inspired from those written by David Z Maze for i2cset. This manual page was strongly inspired from those written by David Z Maze for i2cset.
October 2017 I2CGET(8) July 2021 I2CGET(8)
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