"Fossies" - the Fresh Open Source Software Archive  

Source code changes of the file "cpuid.c" between
cpuid-20180519.src.tar.gz and cpuid-20200112.src.tar.gz

About: cpuid dumps detailed x86 CPUID information about the CPU(s).

cpuid.c  (cpuid-20180519.src):cpuid.c  (cpuid-20200112.src)
/* /*
** cpuid dumps CPUID information for each CPU. ** cpuid dumps CPUID information for each CPU.
** Copyright 2003,2004,2005,2006,2010,2011,2012,2013,2014,2015,2016,2017,2018 by ** Copyright 2003,2004,2005,2006,2010,2011,2012,2013,2014,2015,2016,2017,2018,
** Todd Allen. ** 2020 by Todd Allen.
** **
** This program is free software; you can redistribute it and/or ** This program is free software; you can redistribute it and/or
** modify it under the terms of the GNU General Public License ** modify it under the terms of the GNU General Public License
** as published by the Free Software Foundation; either version 2 ** as published by the Free Software Foundation; either version 2
** of the License, or (at your option) any later version. ** of the License, or (at your option) any later version.
** **
** This program is distributed in the hope that it will be useful, ** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of ** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details. ** GNU General Public License for more details.
** **
** You should have received a copy of the GNU General Public License ** You should have received a copy of the GNU General Public License
** along with this program; if not, write to the Free Software Foundation, Inc., ** along with this program; if not, write to the Free Software Foundation, Inc.,
** 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ** 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/ */
// MSR_CPUID_table* is a table that appears in Intel document 325462, "Intel 64
// and IA-32 Architectures Software Developer's Manual Combined Volumes: 1, 2A,
// 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4" (the name changes from version to version
// as more volumes are added). The table moves around from version to version,
// but in version 071US, was in "Volume 4: Model-Specific Registers", Table 2-1:
// "CPUID Signature Values of DisplayFamily_DisplayModel".
#ifdef __linux__ #ifdef __linux__
#define USE_CPUID_MODULE #define USE_CPUID_MODULE
#define USE_KERNEL_SCHED_SETAFFINITY #define USE_KERNEL_SCHED_SETAFFINITY
#endif #endif
#if __GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__ >= 40300 #if __GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__ >= 40300
#define USE_CPUID_COUNT #define USE_CPUID_COUNT
#endif #endif
#if defined(__GNUC__)
#define UNUSED __attribute((unused))
#else
#define UNUSED
#endif
#define _GNU_SOURCE #define _GNU_SOURCE
#include <stdio.h> #include <stdio.h>
#include <sys/types.h> #include <sys/types.h>
#include <sys/stat.h> #include <sys/stat.h>
#include <sys/sysmacros.h> #include <sys/sysmacros.h>
#include <fcntl.h> #include <fcntl.h>
#include <errno.h> #include <errno.h>
#include <unistd.h> #include <unistd.h>
#include <stdlib.h> #include <stdlib.h>
#include <string.h> #include <string.h>
#include <regex.h> #include <regex.h>
#include <getopt.h> #include <getopt.h>
#if defined(__sun)
#include <sys/processor.h>
#include <sys/procset.h>
#include <strings.h>
#include <pthread.h>
#endif
#ifdef USE_CPUID_MODULE #ifdef USE_CPUID_MODULE
#include <linux/major.h> #include <linux/major.h>
#endif #endif
#ifdef USE_CPUID_COUNT #ifdef USE_CPUID_COUNT
#include <cpuid.h> #include <cpuid.h>
#endif #endif
#ifdef USE_KERNEL_SCHED_SETAFFINITY #ifdef USE_KERNEL_SCHED_SETAFFINITY
#include <sys/syscall.h> #include <sys/syscall.h>
skipping to change at line 69 skipping to change at line 89
#define FALSE 0 #define FALSE 0
typedef char* string; typedef char* string;
typedef const char* cstring; typedef const char* cstring;
typedef const char* const ccstring; typedef const char* const ccstring;
#define SAME 0 #define SAME 0
#define STR(x) #x #define STR(x) #x
#define XSTR(x) STR(x) #define XSTR(x) STR(x)
#define MAX(l,r) ((l) > (r) ? (l) : (r)) #ifndef MAX
#define MAX(l,r) ((l) > (r) ? (l) : (r))
#endif
#define LENGTH(array, type) (sizeof(array) / sizeof(type)) #define LENGTH(array) (sizeof(array) / sizeof(array[0]))
#define STRLEN(s) (LENGTH(s,char) - 1)
#define BPI 32 #define BPI 32
#define POWER2(power) \ #define POWER2(power) \
(1 << (power)) (1 << (power))
#define RIGHTMASK(width) \ #define RIGHTMASK(width) \
(((width) >= BPI) ? ~0 : POWER2(width)-1) (((width) >= BPI) ? ~0 : POWER2(width)-1)
#define BIT_EXTRACT_LE(value, start, after) \ #define BIT_EXTRACT_LE(value, start, after) \
(((value) & RIGHTMASK(after)) >> start) (((value) & RIGHTMASK(after)) >> start)
#define WORD_EAX 0 #define WORD_EAX 0
skipping to change at line 199 skipping to change at line 220
VENDOR_AMD, VENDOR_AMD,
VENDOR_CYRIX, VENDOR_CYRIX,
VENDOR_VIA, VENDOR_VIA,
VENDOR_TRANSMETA, VENDOR_TRANSMETA,
VENDOR_UMC, VENDOR_UMC,
VENDOR_NEXGEN, VENDOR_NEXGEN,
VENDOR_RISE, VENDOR_RISE,
VENDOR_SIS, VENDOR_SIS,
VENDOR_NSC, VENDOR_NSC,
VENDOR_VORTEX, VENDOR_VORTEX,
VENDOR_RDC VENDOR_RDC,
VENDOR_HYGON
} vendor_t; } vendor_t;
typedef enum { typedef enum {
HYPERVISOR_UNKNOWN, HYPERVISOR_UNKNOWN,
HYPERVISOR_VMWARE, HYPERVISOR_VMWARE,
HYPERVISOR_XEN, HYPERVISOR_XEN,
HYPERVISOR_KVM, HYPERVISOR_KVM,
HYPERVISOR_MICROSOFT, HYPERVISOR_MICROSOFT,
} hypervisor_t; } hypervisor_t;
skipping to change at line 261 skipping to change at line 283
else if (__FMS(val) == _XF(xf)+_XM(xm)+_F(f)+_M(m)+_S(s) && (stash) && (q)) printf(str) else if (__FMS(val) == _XF(xf)+_XM(xm)+_F(f)+_M(m)+_S(s) && (stash) && (q)) printf(str)
#define DEFAULT(str) \ #define DEFAULT(str) \
else printf(str) else printf(str)
#define FALLBACK(code) \ #define FALLBACK(code) \
else code else code
typedef struct { typedef struct {
vendor_t vendor; vendor_t vendor;
boolean saw_4; boolean saw_4;
boolean saw_b; boolean saw_b;
boolean saw_1f;
unsigned int val_0_eax; unsigned int val_0_eax;
unsigned int val_1_eax; unsigned int val_1_eax;
unsigned int val_1_ebx; unsigned int val_1_ebx;
unsigned int val_1_ecx; unsigned int val_1_ecx;
unsigned int val_1_edx; unsigned int val_1_edx;
unsigned int val_4_eax; unsigned int val_4_eax;
unsigned int val_b_eax[2]; unsigned int val_b_eax[2];
unsigned int val_b_ebx[2]; unsigned int val_b_ebx[2];
unsigned int val_1f_eax[6];
unsigned int val_1f_ebx[6];
unsigned int val_1f_ecx[6];
unsigned int val_80000001_eax; unsigned int val_80000001_eax;
unsigned int val_80000001_ebx; unsigned int val_80000001_ebx;
unsigned int val_80000001_ecx; unsigned int val_80000001_ecx;
unsigned int val_80000001_edx; unsigned int val_80000001_edx;
unsigned int val_80000008_ecx; unsigned int val_80000008_ecx;
unsigned int val_8000001e_ebx;
unsigned int transmeta_proc_rev; unsigned int transmeta_proc_rev;
char brand[48]; char brand[48+1];
char transmeta_info[48]; char transmeta_info[64+1];
char override_brand[48]; char override_brand[48*2+1];
char soc_brand[48]; char soc_brand[48+1];
hypervisor_t hypervisor; hypervisor_t hypervisor;
struct mp { struct mp {
const char* method; const char* method;
unsigned int cores; unsigned int cores;
unsigned int hyperthreads; unsigned int hyperthreads;
} mp; } mp;
struct br { struct br {
boolean mobile; boolean mobile;
skipping to change at line 317 skipping to change at line 344
boolean phenom; boolean phenom;
boolean series; boolean series;
boolean geode; boolean geode;
boolean turion; boolean turion;
boolean neo; boolean neo;
boolean athlon_fx; boolean athlon_fx;
boolean athlon_mp; boolean athlon_mp;
boolean duron_mp; boolean duron_mp;
boolean opteron; boolean opteron;
boolean fx; boolean fx;
boolean ryzen;
boolean epyc;
boolean embedded; boolean embedded;
int cores; int cores;
}; };
} br; } br;
struct bri { struct bri {
boolean desktop_pentium; boolean desktop_pentium;
boolean desktop_celeron; boolean desktop_celeron;
boolean mobile_pentium; boolean mobile_pentium;
boolean mobile_pentium_m; boolean mobile_pentium_m;
skipping to change at line 353 skipping to change at line 382
boolean L2_2M; /* Nocona lacks, Irwindale has */ boolean L2_2M; /* Nocona lacks, Irwindale has */
/* Conroe has more, Allendale has this */ /* Conroe has more, Allendale has this */
boolean L2_6M; /* Yorkfield C1/E0 has this, M1/R0 has less */ boolean L2_6M; /* Yorkfield C1/E0 has this, M1/R0 has less */
boolean L3; /* Cranford lacks, Potomac has */ boolean L3; /* Cranford lacks, Potomac has */
boolean L2_256K; /* Barton has more, Thorton has this */ boolean L2_256K; /* Barton has more, Thorton has this */
boolean L2_512K; /* Toledo has more, Manchester E6 has this */ boolean L2_512K; /* Toledo has more, Manchester E6 has this */
} code_stash_t; } code_stash_t;
#define NIL_STASH { VENDOR_UNKNOWN, \ #define NIL_STASH { VENDOR_UNKNOWN, \
FALSE, FALSE, \ FALSE, FALSE, FALSE, \
0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, \
{ 0, 0 }, \ { 0, 0 }, \
{ 0, 0 }, \ { 0, 0 }, \
0, 0, 0, 0, 0, 0, \ { 0, 0, 0, 0, 0, 0 }, \
{ 0, 0, 0, 0, 0, 0 }, \
{ 0, 0, 0, 0, 0, 0 }, \
0, 0, 0, 0, 0, 0, 0, \
"", "", "", "", \ "", "", "", "", \
HYPERVISOR_UNKNOWN, \ HYPERVISOR_UNKNOWN, \
{ NULL, -1, -1 }, \ { NULL, -1, -1 }, \
{ FALSE, \ { FALSE, \
{ FALSE, FALSE, FALSE, FALSE, FALSE, \ { FALSE, FALSE, FALSE, FALSE, FALSE, \
FALSE, FALSE, FALSE, FALSE }, \ FALSE, FALSE, FALSE, FALSE }, \
{ FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ { FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \
FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \
FALSE, \ FALSE, FALSE, FALSE, \
FALSE, 0 } }, \ FALSE, 0 } }, \
{ FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE }, \ { FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE }, \
FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \
FALSE, FALSE, FALSE, \ FALSE, FALSE, FALSE, \
FALSE, FALSE } FALSE, FALSE }
static void static void
decode_amd_model(const code_stash_t* stash, decode_amd_model(const code_stash_t* stash,
const char** brand_pre, const char** brand_pre,
const char** brand_post, const char** brand_post,
skipping to change at line 909 skipping to change at line 941
case PG(1) + NC(3) + STR2(6): s2 = "KH HE"; break; case PG(1) + NC(3) + STR2(6): s2 = "KH HE"; break;
case PG(1) + NC(3) + STR2(7): s2 = "KS HE"; break; case PG(1) + NC(3) + STR2(7): s2 = "KS HE"; break;
case PG(1) + NC(5) + STR2(1): s2 = "QS"; break; case PG(1) + NC(5) + STR2(1): s2 = "QS"; break;
case PG(1) + NC(5) + STR2(2): s2 = "KS HE"; break; case PG(1) + NC(5) + STR2(2): s2 = "KS HE"; break;
default: s2 = NULL; break; default: s2 = NULL; break;
} }
break; break;
case 1: case 1:
/* 41322 3.74: table 16: String1 Values for AM2r2 and AM3 Processors */ /* 41322 3.74: table 16: String1 Values for AM2r2 and AM3 Processors */
switch (PG(pg) + NC(nc) + STR1(str1)) { switch (PG(pg) + NC(nc) + STR1(str1)) {
case PG(0) + NC(0) + STR1(2): *brand_pre = "AMD Sempron(tm)"; s1 = "1"; case PG(0) + NC(0) + STR1(2): *brand_pre = "AMD Sempron(tm)"; s1 = "1"; break;
/* This case obviously collides with one later */ /* This case obviously collides with one later */
/* case PG(0) + NC(0) + STR1(3): *brand_pre = "AMD Athlon(tm) II"; s1 = "AMD Athlon(tm) II 1"; */ /* case PG(0) + NC(0) + STR1(3): *brand_pre = "AMD Athlon(tm) II"; s1 = "AMD Athlon(tm) II 1"; */
case PG(0) + NC(0) + STR1(1): *brand_pre = "AMD Athlon(tm)"; s1 = ""; break; case PG(0) + NC(0) + STR1(1): *brand_pre = "AMD Athlon(tm)"; s1 = ""; break;
case PG(0) + NC(0) + STR1(3): *brand_pre = "AMD Athlon(tm) II X2"; s1 = "2"; break; case PG(0) + NC(0) + STR1(3): *brand_pre = "AMD Athlon(tm) II X2"; s1 = "2"; break;
case PG(0) + NC(0) + STR1(4): *brand_pre = "AMD Athlon(tm) II X2"; s1 = "B"; break; case PG(0) + NC(0) + STR1(4): *brand_pre = "AMD Athlon(tm) II X2"; s1 = "B"; break;
case PG(0) + NC(0) + STR1(5): *brand_pre = "AMD Athlon(tm) II X2"; s1 = ""; break; case PG(0) + NC(0) + STR1(5): *brand_pre = "AMD Athlon(tm) II X2"; s1 = ""; break;
case PG(0) + NC(0) + STR1(7): *brand_pre = "AMD Phenom(tm) II X2"; s1 = "5"; break; case PG(0) + NC(0) + STR1(7): *brand_pre = "AMD Phenom(tm) II X2"; s1 = "5"; break;
case PG(0) + NC(0) + STR1(10): *brand_pre = "AMD Phenom(tm) II X2"; s1 = ""; break; case PG(0) + NC(0) + STR1(10): *brand_pre = "AMD Phenom(tm) II X2"; s1 = ""; break;
case PG(0) + NC(0) + STR1(11): *brand_pre = "AMD Phenom(tm) II X2"; s1 = "B"; break; case PG(0) + NC(0) + STR1(11): *brand_pre = "AMD Phenom(tm) II X2"; s1 = "B"; break;
case PG(0) + NC(0) + STR1(12): *brand_pre = "AMD Sempron(tm) X2"; s1 = "1"; break; case PG(0) + NC(0) + STR1(12): *brand_pre = "AMD Sempron(tm) X2"; s1 = "1"; break;
skipping to change at line 1132 skipping to change at line 1164
default: s1 = NULL; brea k; default: s1 = NULL; brea k;
} }
/* 44739 3.10: table 7: String2 Values for FS1 Processors */ /* 44739 3.10: table 7: String2 Values for FS1 Processors */
switch (PG(pg) + NC(nc) + STR2(str2)) { switch (PG(pg) + NC(nc) + STR2(str2)) {
case PG(0) + NC(1) + STR2(1): s2 = "M"; break; case PG(0) + NC(1) + STR2(1): s2 = "M"; break;
case PG(0) + NC(1) + STR2(2): s2 = "MX"; break; case PG(0) + NC(1) + STR2(2): s2 = "MX"; break;
case PG(0) + NC(3) + STR2(1): s2 = "M"; break; case PG(0) + NC(3) + STR2(1): s2 = "M"; break;
case PG(0) + NC(3) + STR2(2): s2 = "MX"; break; case PG(0) + NC(3) + STR2(2): s2 = "MX"; break;
default: s2 = NULL; break; default: s2 = NULL; break;
} }
break;
case 2: case 2:
/* 44739 3.10: table 8: String1 Values for FM1 Processors */ /* 44739 3.10: table 8: String1 Values for FM1 Processors */
switch (PG(pg) + NC(nc) + STR1(str1)) { switch (PG(pg) + NC(nc) + STR1(str1)) {
case PG(0) + NC(1) + STR1(1): *brand_pre = "AMD"; s1 = "A4-33"; break; case PG(0) + NC(1) + STR1(1): *brand_pre = "AMD"; s1 = "A4-33"; break;
case PG(0) + NC(1) + STR1(2): *brand_pre = "AMD"; s1 = "E2-32"; break; case PG(0) + NC(1) + STR1(2): *brand_pre = "AMD"; s1 = "E2-32"; break;
case PG(0) + NC(1) + STR1(4): *brand_pre = "AMD Athlon(tm) II X2"; s1 = "2"; break; case PG(0) + NC(1) + STR1(4): *brand_pre = "AMD Athlon(tm) II X2"; s1 = "2"; break;
case PG(0) + NC(1) + STR1(5): *brand_pre = "AMD"; s1 = "A4-34"; break; case PG(0) + NC(1) + STR1(5): *brand_pre = "AMD"; s1 = "A4-34"; break;
case PG(0) + NC(1) + STR1(12): *brand_pre = "AMD Sempron(tm) X2"; s1 = "1"; break; case PG(0) + NC(1) + STR1(12): *brand_pre = "AMD Sempron(tm) X2"; s1 = "1"; break;
case PG(0) + NC(2) + STR1(5): *brand_pre = "AMD"; s1 = "A6-35"; break; case PG(0) + NC(2) + STR1(5): *brand_pre = "AMD"; s1 = "A6-35"; break;
case PG(0) + NC(3) + STR1(5): *brand_pre = "AMD"; s1 = "A8-38"; break; case PG(0) + NC(3) + STR1(5): *brand_pre = "AMD"; s1 = "A8-38"; break;
skipping to change at line 1155 skipping to change at line 1188
} }
/* 44739 3.10: table 9: String2 Values for FM1 Processors */ /* 44739 3.10: table 9: String2 Values for FM1 Processors */
switch (PG(pg) + NC(nc) + STR2(str2)) { switch (PG(pg) + NC(nc) + STR2(str2)) {
case PG(0) + NC(1) + STR2(1): s2 = " APU with Radeon(tm) HD Graphic s"; break; case PG(0) + NC(1) + STR2(1): s2 = " APU with Radeon(tm) HD Graphic s"; break;
case PG(0) + NC(1) + STR2(2): s2 = " Dual-Core Processor"; break; case PG(0) + NC(1) + STR2(2): s2 = " Dual-Core Processor"; break;
case PG(0) + NC(2) + STR2(1): s2 = " APU with Radeon(tm) HD Graphic s"; break; case PG(0) + NC(2) + STR2(1): s2 = " APU with Radeon(tm) HD Graphic s"; break;
case PG(0) + NC(3) + STR2(1): s2 = " APU with Radeon(tm) HD Graphic s"; break; case PG(0) + NC(3) + STR2(1): s2 = " APU with Radeon(tm) HD Graphic s"; break;
case PG(0) + NC(3) + STR2(3): s2 = " Quad-Core Processor"; break; case PG(0) + NC(3) + STR2(3): s2 = " Quad-Core Processor"; break;
default: s2 = NULL; break; default: s2 = NULL; break;
} }
break;
default: default:
s1 = NULL; s1 = NULL;
s2 = NULL; s2 = NULL;
break; break;
} }
} else if (__F(stash->val_1_eax) == _XF(5) + _F(15)) { } else if (__F(stash->val_1_eax) == _XF(5) + _F(15)) {
partialmodel--; partialmodel--;
/* Family 14h Models 00h-0Fh tables */ /* Family 14h Models 00h-0Fh tables */
switch (pkgtype) { switch (pkgtype) {
skipping to change at line 1237 skipping to change at line 1271
char* p = proc; char* p = proc;
p += sprintf(p, "%s%02d", s1, partialmodel); p += sprintf(p, "%s%02d", s1, partialmodel);
if (s2) sprintf(p, "%s", s2); if (s2) sprintf(p, "%s", s2);
} }
} }
} }
static void static void
decode_override_brand(code_stash_t* stash) decode_override_brand(code_stash_t* stash)
{ {
if (stash->vendor == VENDOR_AMD if ((stash->vendor == VENDOR_AMD
|| stash->vendor == VENDOR_HYGON)
&& strstr(stash->brand, "model unknown") != NULL) { && strstr(stash->brand, "model unknown") != NULL) {
/* /*
** AMD has this exotic architecture where the BIOS decodes the brand ** AMD has this exotic architecture where the BIOS decodes the brand
** string from tables and feeds it back into the CPU via MSR's. If an old ** string from tables and feeds it back into the CPU via MSR's. If an old
** BIOS cannot understand a new CPU, it uses the string "model unknown". ** BIOS cannot understand a new CPU, it uses the string "model unknown".
** In this case, I use my own copies of tables to deduce the brand string ** In this case, I use my own copies of tables to deduce the brand string
** and decode that. ** and decode that.
*/ */
const char* brand_pre; const char* brand_pre;
const char* brand_post; const char* brand_post;
skipping to change at line 1442 skipping to change at line 1477
stash->br.phenom = strstr(brand, "Phenom") != NULL; stash->br.phenom = strstr(brand, "Phenom") != NULL;
stash->br.series = strstr(brand, "Series") != NULL; stash->br.series = strstr(brand, "Series") != NULL;
stash->br.geode = strstr(brand, "Geode") != NULL; stash->br.geode = strstr(brand, "Geode") != NULL;
stash->br.turion = strstr(brand, "Turion") != NULL; stash->br.turion = strstr(brand, "Turion") != NULL;
stash->br.neo = strstr(brand, "Neo") != NULL; stash->br.neo = strstr(brand, "Neo") != NULL;
stash->br.athlon_fx = strstr(brand, "Athlon(tm) 64 FX") != NULL; stash->br.athlon_fx = strstr(brand, "Athlon(tm) 64 FX") != NULL;
stash->br.athlon_mp = strstr(brand, "Athlon(tm) MP") != NULL; stash->br.athlon_mp = strstr(brand, "Athlon(tm) MP") != NULL;
stash->br.duron_mp = strstr(brand, "Duron(tm) MP") != NULL; stash->br.duron_mp = strstr(brand, "Duron(tm) MP") != NULL;
stash->br.opteron = strstr(brand, "Opteron") != NULL; stash->br.opteron = strstr(brand, "Opteron") != NULL;
stash->br.fx = strstr(brand, "AMD FX") != NULL; stash->br.fx = strstr(brand, "AMD FX") != NULL;
stash->br.ryzen = strstr(brand, "Ryzen") != NULL;
stash->br.epyc = strstr(brand, "EPYC") != NULL;
stash->br.embedded = strstr(brand, "Embedded") != NULL; stash->br.embedded = strstr(brand, "Embedded") != NULL;
if (strstr(brand, "Dual Core") != NULL if (strstr(brand, "Dual Core") != NULL
|| strstr(brand, " X2 ") != NULL) { || strstr(brand, " X2 ") != NULL) {
stash->br.cores = 2; stash->br.cores = 2;
} else if (strstr(brand, "Triple-Core") != NULL } else if (strstr(brand, "Triple-Core") != NULL
|| strstr(brand, " X3 ") != NULL) { || strstr(brand, " X3 ") != NULL) {
stash->br.cores = 3; stash->br.cores = 3;
} else if (strstr(brand, "Quad-Core") != NULL } else if (strstr(brand, "Quad-Core") != NULL
|| strstr(brand, " X4 ") != NULL) { || strstr(brand, " X4 ") != NULL) {
skipping to change at line 1589 skipping to change at line 1626
** ?N = think Neo ** ?N = think Neo
*/ */
#define dA (is_amd && !is_mobile && stash->br.athlon) #define dA (is_amd && !is_mobile && stash->br.athlon)
#define dX (is_amd && !is_mobile && stash->br.athlon_xp) #define dX (is_amd && !is_mobile && stash->br.athlon_xp)
#define dF (is_amd && !is_mobile && stash->br.athlon_fx) #define dF (is_amd && !is_mobile && stash->br.athlon_fx)
#define df (is_amd && !is_mobile && stash->br.fx) #define df (is_amd && !is_mobile && stash->br.fx)
#define dD (is_amd && !is_mobile && stash->br.duron) #define dD (is_amd && !is_mobile && stash->br.duron)
#define dS (is_amd && !is_mobile && stash->br.sempron) #define dS (is_amd && !is_mobile && stash->br.sempron)
#define dO (is_amd && !is_mobile && stash->br.opteron) #define dO (is_amd && !is_mobile && stash->br.opteron)
#define dp (is_amd && !is_mobile && stash->br.phenom) #define dp (is_amd && !is_mobile && stash->br.phenom)
#define dR (is_amd && !is_mobile && stash->br.ryzen)
#define sA (is_amd && !is_mobile && stash->br.athlon_mp) #define sA (is_amd && !is_mobile && stash->br.athlon_mp)
#define sD (is_amd && !is_mobile && stash->br.duron_mp) #define sD (is_amd && !is_mobile && stash->br.duron_mp)
#define sE (is_amd && !is_mobile && stash->br.epyc)
#define MA (is_amd && is_mobile && stash->br.athlon) #define MA (is_amd && is_mobile && stash->br.athlon)
#define MX (is_amd && is_mobile && stash->br.athlon_xp) #define MX (is_amd && is_mobile && stash->br.athlon_xp)
#define ML (is_amd && is_mobile && stash->br.athlon_lv) #define ML (is_amd && is_mobile && stash->br.athlon_lv)
#define MD (is_amd && is_mobile && stash->br.duron) #define MD (is_amd && is_mobile && stash->br.duron)
#define MS (is_amd && is_mobile && stash->br.sempron) #define MS (is_amd && is_mobile && stash->br.sempron)
#define Mp (is_amd && is_mobile && stash->br.phenom) #define Mp (is_amd && is_mobile && stash->br.phenom)
#define Ms (is_amd && is_mobile && stash->br.series) #define Ms (is_amd && is_mobile && stash->br.series)
#define MG (is_amd && stash->br.geode) #define MG (is_amd && stash->br.geode)
#define MT (is_amd && stash->br.turion) #define MT (is_amd && stash->br.turion)
#define Mn (is_amd && stash->br.turion && stash->br.neo) #define Mn (is_amd && stash->br.turion && stash->br.neo)
skipping to change at line 1690 skipping to change at line 1729
/* Semprons, distinguished by number of processors */ /* Semprons, distinguished by number of processors */
#define DS (dS && stash->br.cores == 2) #define DS (dS && stash->br.cores == 2)
/* Egypt, distinguished from Italy; and /* Egypt, distinguished from Italy; and
Athens, distingushed from Troy */ Athens, distingushed from Troy */
#define d8 (dO && is_amd_egypt_athens_8xx(stash)) #define d8 (dO && is_amd_egypt_athens_8xx(stash))
/* Thorton A2, distinguished from Barton A2 */ /* Thorton A2, distinguished from Barton A2 */
#define dt (dX && stash->L2_256K) #define dt (dX && stash->L2_256K)
/* Manchester E6, distinguished from from Toledo E6 */ /* Manchester E6, distinguished from from Toledo E6 */
#define dm (dA && stash->L2_512K) #define dm (dA && stash->L2_512K)
/* Propus, distinguished from Regor */ /* Propus, distinguished from Regor */
#define dR (dA && stash->L2_512K) #define dr (dA && stash->L2_512K)
/* Trinidad, distinguished from Taylor */ /* Trinidad, distinguished from Taylor */
#define Mt (MT && stash->L2_512K) #define Mt (MT && stash->L2_512K)
/* /*
** Transmeta major queries ** Transmeta major queries
** **
** t2 = TMx200 ** t2 = TMx200
** t4 = TMx400 ** t4 = TMx400
** t5 = TMx500 ** t5 = TMx500
** t6 = TMx600 ** t6 = TMx600
skipping to change at line 1754 skipping to change at line 1793
DEBUGQ(Dc); DEBUGQ(Dc);
DEBUGQ(Qc); DEBUGQ(Qc);
DEBUGQ(XE); DEBUGQ(XE);
DEBUGQ(sQ); DEBUGQ(sQ);
DEBUGQ(s7); DEBUGQ(s7);
DEBUGQ(de); DEBUGQ(de);
DEBUGQ(Me); DEBUGQ(Me);
DEBUGQ(Qe); DEBUGQ(Qe);
DEBUGQ(se); DEBUGQ(se);
DEBUGQ(ML);
DEBUGQ(MX);
DEBUGQ(MD);
DEBUGQ(MA);
DEBUGQ(MS);
DEBUGQ(Mp);
DEBUGQ(Ms);
DEBUGQ(Mn);
DEBUGQ(MN);
DEBUGQ(MT);
DEBUGQ(dO); DEBUGQ(dO);
DEBUGQ(dp); DEBUGQ(dp);
DEBUGQ(dX); DEBUGQ(dX);
DEBUGQ(dF); DEBUGQ(dF);
DEBUGQ(df);
DEBUGQ(dD);
DEBUGQ(dS);
DEBUGQ(dO);
DEBUGQ(dp);
DEBUGQ(dR);
DEBUGQ(sA); DEBUGQ(sA);
DEBUGQ(sD); DEBUGQ(sD);
DEBUGQ(sE);
DEBUGQ(dD); DEBUGQ(dD);
DEBUGQ(dA); DEBUGQ(dA);
DEBUGQ(dS); DEBUGQ(dS);
DEBUGQ(ML);
DEBUGQ(MX);
DEBUGQ(MD);
DEBUGQ(MA);
DEBUGQ(MS);
DEBUGQ(Mp);
DEBUGQ(Ms);
DEBUGQ(MG);
DEBUGQ(MT);
DEBUGQ(Mn);
DEBUGQ(MN);
DEBUGF(is_amd_egypt_athens_8xx); DEBUGF(is_amd_egypt_athens_8xx);
DEBUGQ(EO); DEBUGQ(EO);
DEBUGQ(DO); DEBUGQ(DO);
DEBUGQ(SO); DEBUGQ(SO);
DEBUGQ(DA); DEBUGQ(DA);
DEBUGQ(TA); DEBUGQ(TA);
DEBUGQ(QA); DEBUGQ(QA);
DEBUGQ(Dp); DEBUGQ(Dp);
DEBUGQ(Tp); DEBUGQ(Tp);
DEBUGQ(Qp); DEBUGQ(Qp);
DEBUGQ(Sp); DEBUGQ(Sp);
DEBUGQ(DS); DEBUGQ(DS);
DEBUGQ(d8); DEBUGQ(d8);
DEBUGQ(dt); DEBUGQ(dt);
DEBUGQ(dm); DEBUGQ(dm);
DEBUGQ(dR); DEBUGQ(dr);
DEBUGQ(Mt); DEBUGQ(Mt);
DEBUGQ(t2); DEBUGQ(t2);
DEBUGQ(t4); DEBUGQ(t4);
DEBUGQ(t5); DEBUGQ(t5);
DEBUGQ(t6); DEBUGQ(t6);
DEBUGQ(t8); DEBUGQ(t8);
#undef DEBUGQ #undef DEBUGQ
#undef DEBUGF #undef DEBUGF
skipping to change at line 1974 skipping to change at line 2021
FMSQ( 0, 6, 0,14, 12, Dc, "Intel Core Duo (Yonah D0), 65nm"); FMSQ( 0, 6, 0,14, 12, Dc, "Intel Core Duo (Yonah D0), 65nm");
FMSQ( 0, 6, 0,14, 12, dc, "Intel Core Solo (Yonah D0), 65nm"); FMSQ( 0, 6, 0,14, 12, dc, "Intel Core Solo (Yonah D0), 65nm");
FMS ( 0, 6, 0,14, 12, "Intel Core Solo (Yonah D0) / Core Duo (Yonah D 0) / Xeon Processor LV (Sossaman D0) / Pentium Dual-Core Mobile T2000 (Yonah D0) / Celeron M (Yonah D0), 65nm"); FMS ( 0, 6, 0,14, 12, "Intel Core Solo (Yonah D0) / Core Duo (Yonah D 0) / Xeon Processor LV (Sossaman D0) / Pentium Dual-Core Mobile T2000 (Yonah D0) / Celeron M (Yonah D0), 65nm");
FMS ( 0, 6, 0,14, 13, "Intel Pentium Dual-Core Mobile T2000 (Yonah M0 ), 65nm"); FMS ( 0, 6, 0,14, 13, "Intel Pentium Dual-Core Mobile T2000 (Yonah M0 ), 65nm");
FMQ ( 0, 6, 0,14, sX, "Intel Xeon Processor LV (Sossaman), 65nm"); FMQ ( 0, 6, 0,14, sX, "Intel Xeon Processor LV (Sossaman), 65nm");
FMQ ( 0, 6, 0,14, dC, "Intel Celeron (Yonah), 65nm"); FMQ ( 0, 6, 0,14, dC, "Intel Celeron (Yonah), 65nm");
FMQ ( 0, 6, 0,14, MP, "Intel Pentium Dual-Core Mobile (Yonah), 65nm") ; FMQ ( 0, 6, 0,14, MP, "Intel Pentium Dual-Core Mobile (Yonah), 65nm") ;
FMQ ( 0, 6, 0,14, Dc, "Intel Core Duo (Yonah), 65nm"); FMQ ( 0, 6, 0,14, Dc, "Intel Core Duo (Yonah), 65nm");
FMQ ( 0, 6, 0,14, dc, "Intel Core Solo (Yonah), 65nm"); FMQ ( 0, 6, 0,14, dc, "Intel Core Solo (Yonah), 65nm");
FM ( 0, 6, 0,14, "Intel Core Solo (Yonah) / Core Duo (Yonah) / X eon Processor LV (Sossaman) / Celeron (Yonah) / Pentium Dual-Core Mobile (Yonah) , 65nm"); FM ( 0, 6, 0,14, "Intel Core Solo (Yonah) / Core Duo (Yonah) / X eon Processor LV (Sossaman) / Celeron (Yonah) / Pentium Dual-Core Mobile (Yonah) , 65nm");
FMSQ( 0, 6, 0,15, 2, sX, "Intel Dual-Core Xeon Processor 3000 (Conroe L2 FMSQ( 0, 6, 0,15, 2, sX, "Intel Dual-Core Xeon Processor 3000 (Conroe L2
), 65nm"); ) [Merom], 65nm");
FMSQ( 0, 6, 0,15, 2, Mc, "Intel Core Duo Mobile (Merom L2), 65nm"); FMSQ( 0, 6, 0,15, 2, Mc, "Intel Core Duo Mobile (Merom L2) [Merom], 65nm
FMSQ( 0, 6, 0,15, 2, dc, "Intel Core Duo (Conroe L2), 65nm"); ");
FMSQ( 0, 6, 0,15, 2, dP, "Intel Pentium Dual-Core Desktop Processor E200 FMSQ( 0, 6, 0,15, 2, dc, "Intel Core Duo (Conroe L2) [Merom], 65nm");
0 (Allendale L2), 65nm"); FMSQ( 0, 6, 0,15, 2, dP, "Intel Pentium Dual-Core Desktop Processor E200
FMS ( 0, 6, 0,15, 2, "Intel Core Duo (Conroe L2) / Core Duo Mobile ( 0 (Allendale L2) [Merom], 65nm");
Merom L2) / Pentium Dual-Core Desktop Processor E2000 (Allendale L2) / Dual-Core FMS ( 0, 6, 0,15, 2, "Intel Core Duo (Conroe L2) / Core Duo Mobile (
Xeon Processor 3000 (Conroe L2), 65nm"); Merom L2) / Pentium Dual-Core Desktop Processor E2000 (Allendale L2) / Dual-Core
FMS ( 0, 6, 0,15, 4, "Intel Core 2 Duo (Conroe B0) / Xeon Processor Xeon Processor 3000 (Conroe L2) [Merom], 65nm");
5100 (Woodcrest B0) (pre-production), 65nm"); FMS ( 0, 6, 0,15, 4, "Intel Core 2 Duo (Conroe B0) / Xeon Processor
FMSQ( 0, 6, 0,15, 5, QW, "Intel Dual-Core Xeon Processor 5100 (Woodcrest 5100 (Woodcrest B0) (pre-production) [Merom], 65nm");
B1) (pre-production), 65nm"); FMSQ( 0, 6, 0,15, 5, QW, "Intel Dual-Core Xeon Processor 5100 (Woodcrest
FMSQ( 0, 6, 0,15, 5, XE, "Intel Core 2 Extreme Processor (Conroe B1), 65 B1) (pre-production) [Merom], 65nm");
nm"); FMSQ( 0, 6, 0,15, 5, XE, "Intel Core 2 Extreme Processor (Conroe B1) [Me
FMSQ( 0, 6, 0,15, 5, da, "Intel Core 2 Duo (Allendale B1), 65nm"); rom], 65nm");
FMSQ( 0, 6, 0,15, 5, dc, "Intel Core 2 Duo (Conroe B1), 65nm"); FMSQ( 0, 6, 0,15, 5, da, "Intel Core 2 Duo (Allendale B1) [Merom], 65nm"
FMS ( 0, 6, 0,15, 5, "Intel Core 2 Duo (Conroe/Allendale B1) / Core );
2 Extreme Processor (Conroe B1), 65nm"); FMSQ( 0, 6, 0,15, 5, dc, "Intel Core 2 Duo (Conroe B1) [Merom], 65nm");
FMSQ( 0, 6, 0,15, 6, Xc, "Intel Core 2 Extreme Processor (Conroe B2), 65 FMS ( 0, 6, 0,15, 5, "Intel Core 2 Duo (Conroe/Allendale B1) / Core
nm"); 2 Extreme Processor (Conroe B1) [Merom], 65nm");
FMSQ( 0, 6, 0,15, 6, Mc, "Intel Core 2 Duo Mobile (Merom B2), 65nm"); FMSQ( 0, 6, 0,15, 6, Xc, "Intel Core 2 Extreme Processor (Conroe B2) [Me
FMSQ( 0, 6, 0,15, 6, da, "Intel Core 2 Duo (Allendale B2), 65nm"); rom], 65nm");
FMSQ( 0, 6, 0,15, 6, dc, "Intel Core 2 Duo (Conroe B2), 65nm"); FMSQ( 0, 6, 0,15, 6, Mc, "Intel Core 2 Duo Mobile (Merom B2) [Merom], 65
FMSQ( 0, 6, 0,15, 6, dC, "Intel Celeron M (Conroe B2), 65nm"); nm");
FMSQ( 0, 6, 0,15, 6, sX, "Intel Dual-Core Xeon Processor 3000 (Conroe B2 FMSQ( 0, 6, 0,15, 6, da, "Intel Core 2 Duo (Allendale B2) [Merom], 65nm"
) / Dual-Core Xeon Processor 5100 (Woodcrest B2), 65nm"); );
FMS ( 0, 6, 0,15, 6, "Intel Core 2 Duo (Conroe/Allendale B2) / Core FMSQ( 0, 6, 0,15, 6, dc, "Intel Core 2 Duo (Conroe B2) [Merom], 65nm");
2 Extreme Processor (Conroe B2) / Dual-Core Xeon Processor 3000 (Conroe B2) / Du FMSQ( 0, 6, 0,15, 6, dC, "Intel Celeron M (Conroe B2) [Merom], 65nm");
al-Core Xeon Processor 5100 (Woodcrest B2) / Core 2 Duo Mobile (Conroe B2), 65nm FMSQ( 0, 6, 0,15, 6, sX, "Intel Dual-Core Xeon Processor 3000 (Conroe B2
"); ) / Dual-Core Xeon Processor 5100 (Woodcrest B2) [Merom], 65nm");
FMSQ( 0, 6, 0,15, 7, sX, "Intel Quad-Core Xeon Processor 3200 (Kentsfiel FMS ( 0, 6, 0,15, 6, "Intel Core 2 Duo (Conroe/Allendale B2) / Core
d B3) / Quad-Core Xeon Processor 5300 (Clovertown B3), 65nm"); 2 Extreme Processor (Conroe B2) / Dual-Core Xeon Processor 3000 (Conroe B2) / Du
FMSQ( 0, 6, 0,15, 7, Xc, "Intel Core 2 Extreme Quad-Core Processor QX6xx al-Core Xeon Processor 5100 (Woodcrest B2) / Core 2 Duo Mobile (Conroe B2) [Mero
0 (Kentsfield B3), 65nm"); m], 65nm");
FMS ( 0, 6, 0,15, 7, "Intel Quad-Core Xeon Processor 3200 (Kentsfiel FMSQ( 0, 6, 0,15, 7, sX, "Intel Quad-Core Xeon Processor 3200 (Kentsfiel
d B3) / Quad-Core Xeon Processor 5300 (Clovertown B3) / Core 2 Extreme Quad-Core d B3) / Quad-Core Xeon Processor 5300 (Clovertown B3) [Merom], 65nm");
Processor QX6700 (Clovertown B3)a, 65nm"); FMSQ( 0, 6, 0,15, 7, Xc, "Intel Core 2 Extreme Quad-Core Processor QX6xx
FMSQ( 0, 6, 0,15, 10, Mc, "Intel Core 2 Duo Mobile (Merom E1), 65nm"); 0 (Kentsfield B3) [Merom], 65nm");
FMSQ( 0, 6, 0,15, 10, dC, "Intel Celeron Processor 500 (Merom E1), 65nm") FMS ( 0, 6, 0,15, 7, "Intel Quad-Core Xeon Processor 3200 (Kentsfiel
; d B3) / Quad-Core Xeon Processor 5300 (Clovertown B3) / Core 2 Extreme Quad-Core
FMS ( 0, 6, 0,15, 10, "Intel Core 2 Duo Mobile (Merom E1) / Celeron P Processor QX6700 (Clovertown B3)a [Merom], 65nm");
rocessor 500 (Merom E1), 65nm"); FMSQ( 0, 6, 0,15, 10, Mc, "Intel Core 2 Duo Mobile (Merom E1) [Merom], 65
FMSQ( 0, 6, 0,15, 11, sQ, "Intel Quad-Core Xeon Processor 5300 (Clovertow nm");
n G0), 65nm"); FMSQ( 0, 6, 0,15, 10, dC, "Intel Celeron Processor 500 (Merom E1) [Merom]
FMSQ( 0, 6, 0,15, 11, sX, "Intel Xeon Processor 3000 (Conroe G0) / Xeon P , 65nm");
rocessor 3200 (Kentsfield G0) / Xeon Processor 7200/7300 (Tigerton G0), 65nm"); FMS ( 0, 6, 0,15, 10, "Intel Core 2 Duo Mobile (Merom E1) / Celeron P
FMSQ( 0, 6, 0,15, 11, Xc, "Intel Core 2 Extreme Quad-Core Processor QX6xx rocessor 500 (Merom E1) [Merom], 65nm");
0 (Kentsfield G0), 65nm"); FMSQ( 0, 6, 0,15, 11, sQ, "Intel Quad-Core Xeon Processor 5300 (Clovertow
FMSQ( 0, 6, 0,15, 11, Mc, "Intel Core 2 Duo Mobile (Merom G2), 65nm"); n G0) [Merom], 65nm");
FMSQ( 0, 6, 0,15, 11, Qc, "Intel Core 2 Quad (Conroe G0), 65nm"); FMSQ( 0, 6, 0,15, 11, sX, "Intel Xeon Processor 3000 (Conroe G0) / Xeon P
FMSQ( 0, 6, 0,15, 11, dc, "Intel Core 2 Duo (Conroe G0), 65nm"); rocessor 3200 (Kentsfield G0) / Xeon Processor 7200/7300 (Tigerton G0) [Merom],
FMS ( 0, 6, 0,15, 11, "Intel Core 2 Duo (Conroe G0) / Xeon Processor 65nm");
3000 (Conroe G0) / Xeon Processor 3200 (Kentsfield G0) / Xeon Processor 7200/730 FMSQ( 0, 6, 0,15, 11, Xc, "Intel Core 2 Extreme Quad-Core Processor QX6xx
0 (Tigerton G0) / Quad-Core Xeon Processor 5300 (Clovertown G0) / Core 2 Extreme 0 (Kentsfield G0) [Merom], 65nm");
Quad-Core Processor QX6xx0 (Kentsfield G0) / Core 2 Duo Mobile (Merom G2), 65nm FMSQ( 0, 6, 0,15, 11, Mc, "Intel Core 2 Duo Mobile (Merom G2) [Merom], 65
"); nm");
FMSQ( 0, 6, 0,15, 13, Mc, "Intel Core 2 Duo Mobile (Merom M1) / Celeron P FMSQ( 0, 6, 0,15, 11, Qc, "Intel Core 2 Quad (Conroe G0) [Merom], 65nm");
rocessor 500 (Merom E1), 65nm"); FMSQ( 0, 6, 0,15, 11, dc, "Intel Core 2 Duo (Conroe G0) [Merom], 65nm");
FMSQ( 0, 6, 0,15, 13, Qc, "Intel Core 2 Quad (Conroe M0), 65nm"); FMS ( 0, 6, 0,15, 11, "Intel Core 2 Duo (Conroe G0) / Xeon Processor
FMSQ( 0, 6, 0,15, 13, dc, "Intel Core 2 Duo (Conroe M0), 65nm"); 3000 (Conroe G0) / Xeon Processor 3200 (Kentsfield G0) / Xeon Processor 7200/730
FMSQ( 0, 6, 0,15, 13, dP, "Intel Pentium Dual-Core Desktop Processor E200 0 (Tigerton G0) / Quad-Core Xeon Processor 5300 (Clovertown G0) / Core 2 Extreme
0 (Allendale M0), 65nm"); Quad-Core Processor QX6xx0 (Kentsfield G0) / Core 2 Duo Mobile (Merom G2) [Mero
m], 65nm");
FMSQ( 0, 6, 0,15, 13, Mc, "Intel Core 2 Duo Mobile (Merom M1) / Celeron P
rocessor 500 (Merom E1) [Merom], 65nm");
FMSQ( 0, 6, 0,15, 13, Qc, "Intel Core 2 Quad (Conroe M0) [Merom], 65nm");
FMSQ( 0, 6, 0,15, 13, dc, "Intel Core 2 Duo (Conroe M0) [Merom], 65nm");
FMSQ( 0, 6, 0,15, 13, dP, "Intel Pentium Dual-Core Desktop Processor E200
0 (Allendale M0) [Merom], 65nm");
FMSQ( 0, 6, 0,15, 13, dC, "Intel Celeron Dual-Core E1000 (Allendale M0) / Celeron Dual-Core T1000 (Merom M0)"); FMSQ( 0, 6, 0,15, 13, dC, "Intel Celeron Dual-Core E1000 (Allendale M0) / Celeron Dual-Core T1000 (Merom M0)");
FMS ( 0, 6, 0,15, 13, "Intel Core 2 Duo (Conroe M0) / Core 2 Duo Mobi le (Merom M1) / Celeron Processor 500 (Merom E1) / Pentium Dual-Core Desktop Pro cessor E2000 (Allendale M0) / Celeron Dual-Core E1000 (Allendale M0) / Celeron D ual-Core T1000 (Merom M0)"); FMS ( 0, 6, 0,15, 13, "Intel Core 2 Duo (Conroe M0) / Core 2 Duo Mobi le (Merom M1) / Celeron Processor 500 (Merom E1) / Pentium Dual-Core Desktop Pro cessor E2000 (Allendale M0) / Celeron Dual-Core E1000 (Allendale M0) / Celeron D ual-Core T1000 (Merom M0)");
FMQ ( 0, 6, 0,15, sQ, "Intel Quad-Core Xeon (Woodcrest), 65nm"); FMQ ( 0, 6, 0,15, sQ, "Intel Quad-Core Xeon (Woodcrest) [Merom], 65nm
FMQ ( 0, 6, 0,15, sX, "Intel Dual-Core Xeon (Conroe / Woodcrest) / Qu ");
ad-Core Xeon (Kentsfield / Clovertown) / Core 2 Extreme Quad-Core (Clovertown) / FMQ ( 0, 6, 0,15, sX, "Intel Dual-Core Xeon (Conroe / Woodcrest) / Qu
Xeon (Tigerton G0), 65nm"); ad-Core Xeon (Kentsfield / Clovertown) / Core 2 Extreme Quad-Core (Clovertown) /
FMQ ( 0, 6, 0,15, Xc, "Intel Core 2 Extreme Processor (Conroe) / Core Xeon (Tigerton G0) [Merom], 65nm");
2 Extreme Quad-Core (Kentsfield), 65nm"); FMQ ( 0, 6, 0,15, Xc, "Intel Core 2 Extreme Processor (Conroe) / Core
FMQ ( 0, 6, 0,15, Mc, "Intel Core Duo Mobile / Core 2 Duo Mobile (Mer 2 Extreme Quad-Core (Kentsfield) [Merom], 65nm");
om) / Celeron (Merom), 65nm"); FMQ ( 0, 6, 0,15, Mc, "Intel Core Duo Mobile / Core 2 Duo Mobile (Mer
FMQ ( 0, 6, 0,15, Qc, "Intel Core 2 Quad (Conroe), 65nm"); om) / Celeron (Merom) [Merom], 65nm");
FMQ ( 0, 6, 0,15, dc, "Intel Core Duo / Core 2 Duo (Conroe), 65nm"); FMQ ( 0, 6, 0,15, Qc, "Intel Core 2 Quad (Conroe) [Merom], 65nm");
FMQ ( 0, 6, 0,15, dP, "Intel Pentium Dual-Core (Allendale), 65nm"); FMQ ( 0, 6, 0,15, dc, "Intel Core Duo / Core 2 Duo (Conroe) [Merom],
FMQ ( 0, 6, 0,15, dC, "Intel Celeron M (Conroe) / Celeron (Merom) / C 65nm");
eleron Dual-Core (Allendale), 65nm"); FMQ ( 0, 6, 0,15, dP, "Intel Pentium Dual-Core (Allendale) [Merom], 6
FM ( 0, 6, 0,15, "Intel Core Duo / Core 2 Duo (Conroe / Allendal 5nm");
e) / Core Duo Mobile (Merom) / Core 2 Duo Mobile (Merom) / Celeron (Merom) / Cor FMQ ( 0, 6, 0,15, dC, "Intel Celeron M (Conroe) / Celeron (Merom) / C
e 2 Extreme (Conroe) / Core 2 Extreme Quad-Core (Kentsfield) / Pentium Dual-Core eleron Dual-Core (Allendale) [Merom], 65nm");
(Allendale) / Celeron M (Conroe) / Celeron (Merom) / Celeron Dual-Core (Allenda FM ( 0, 6, 0,15, "Intel Core Duo / Core 2 Duo (Conroe / Allendal
le) / Quad-Core Xeon (Kentsfield / Clovertown / Woodcrest) / Core 2 Extreme Quad e) / Core Duo Mobile (Merom) / Core 2 Duo Mobile (Merom) / Celeron (Merom) / Cor
-Core (Clovertown) / Xeon (Tigerton) / Dual-Core Xeon (Conroe / Woodcrest), 65nm e 2 Extreme (Conroe) / Core 2 Extreme Quad-Core (Kentsfield) / Pentium Dual-Core
"); (Allendale) / Celeron M (Conroe) / Celeron (Merom) / Celeron Dual-Core (Allenda
le) / Quad-Core Xeon (Kentsfield / Clovertown / Woodcrest) / Core 2 Extreme Quad
-Core (Clovertown) / Xeon (Tigerton) / Dual-Core Xeon (Conroe / Woodcrest) [Mero
m], 65nm");
FMS ( 0, 6, 1, 5, 0, "Intel EP80579 (Tolapai B0), 65nm"); FMS ( 0, 6, 1, 5, 0, "Intel EP80579 (Tolapai B0), 65nm");
FMSQ( 0, 6, 1, 6, 1, MC, "Intel Celeron Processor 200/400/500 (Conroe-L/ FMSQ( 0, 6, 1, 6, 1, MC, "Intel Celeron Processor 200/400/500 (Conroe-L/
Merom-L A1), 65nm"); Merom-L A1) [Merom], 65nm");
FMSQ( 0, 6, 1, 6, 1, dC, "Intel Celeron M (Merom-L A1), 65nm"); FMSQ( 0, 6, 1, 6, 1, dC, "Intel Celeron M (Merom-L A1) [Merom], 65nm");
FMSQ( 0, 6, 1, 6, 1, Mc, "Intel Core 2 Duo Mobile (Merom A1), 65nm"); FMSQ( 0, 6, 1, 6, 1, Mc, "Intel Core 2 Duo Mobile (Merom A1) [Merom], 65
FMS ( 0, 6, 1, 6, 1, "Intel Core 2 Duo Mobile (Merom A1) / Celeron 2 nm");
00/400/500 (Conroe-L/Merom-L A1) / Celeron M (Merom-L A1), 65nm"); FMS ( 0, 6, 1, 6, 1, "Intel Core 2 Duo Mobile (Merom A1) / Celeron 2
FMQ ( 0, 6, 1, 6, MC, "Intel Celeron Processor 200/400/500 (Conroe-L/ 00/400/500 (Conroe-L/Merom-L A1) / Celeron M (Merom-L A1) [Merom], 65nm");
Merom-L), 65nm"); FMQ ( 0, 6, 1, 6, MC, "Intel Celeron Processor 200/400/500 (Conroe-L/
FMQ ( 0, 6, 1, 6, dC, "Intel Celeron M (Merom-L), 65nm"); Merom-L) [Merom], 65nm");
FMQ ( 0, 6, 1, 6, Mc, "Intel Core 2 Duo Mobile (Merom), 65nm"); FMQ ( 0, 6, 1, 6, dC, "Intel Celeron M (Merom-L) [Merom], 65nm");
FM ( 0, 6, 1, 6, "Intel Core 2 Duo Mobile (Merom) / Celeron (Con FMQ ( 0, 6, 1, 6, Mc, "Intel Core 2 Duo Mobile (Merom) [Merom], 65nm"
roe-L/Merom-L) / Celeron M (Merom-L), 65nm"); );
FMSQ( 0, 6, 1, 7, 6, sQ, "Intel Xeon Processor 3300 (Yorkfield C0) / Xeo FM ( 0, 6, 1, 6, "Intel Core 2 Duo Mobile (Merom) / Celeron (Con
n Processor 5200 (Wolfdale C0) / Xeon Processor 5400 (Harpertown C0), 45nm"); roe-L/Merom-L) / Celeron M (Merom-L) [Merom], 65nm");
FMSQ( 0, 6, 1, 7, 6, sX, "Intel Xeon Processor 3100 (Wolfdale C0) / Xeon FMSQ( 0, 6, 1, 7, 6, sQ, "Intel Xeon Processor 3300 (Yorkfield C0) / Xeo
Processor 5200 (Wolfdale C0) / Xeon Processor 5400 (Harpertown C0), 45nm"); n Processor 5200 (Wolfdale C0) / Xeon Processor 5400 (Harpertown C0) [Penryn], 4
FMSQ( 0, 6, 1, 7, 6, Xc, "Intel Core 2 Extreme QX9000 (Yorkfield C0), 45 5nm");
nm"); FMSQ( 0, 6, 1, 7, 6, sX, "Intel Xeon Processor 3100 (Wolfdale C0) / Xeon
FMSQ( 0, 6, 1, 7, 6, Me, "Intel Mobile Core 2 Duo (Penryn C0), 45nm"); Processor 5200 (Wolfdale C0) / Xeon Processor 5400 (Harpertown C0) [Penryn], 45
FMSQ( 0, 6, 1, 7, 6, Mc, "Intel Mobile Core 2 Duo (Penryn M0), 45nm"); nm");
FMSQ( 0, 6, 1, 7, 6, de, "Intel Core 2 Duo (Wolfdale C0), 45nm"); FMSQ( 0, 6, 1, 7, 6, Xc, "Intel Core 2 Extreme QX9000 (Yorkfield C0) [Pe
FMSQ( 0, 6, 1, 7, 6, dc, "Intel Core 2 Duo (Wolfdale M0), 45nm"); nryn], 45nm");
FMSQ( 0, 6, 1, 7, 6, dP, "Intel Pentium Dual-Core Processor E5000 (Wolfd FMSQ( 0, 6, 1, 7, 6, Me, "Intel Mobile Core 2 Duo (Penryn C0) [Penryn],
ale M0), 45nm"); 45nm");
FMS ( 0, 6, 1, 7, 6, "Intel Core 2 Duo (Wolfdale C0/M0) / Mobile Cor FMSQ( 0, 6, 1, 7, 6, Mc, "Intel Mobile Core 2 Duo (Penryn M0) [Penryn],
e 2 Duo (Penryn C0/M0) / Core 2 Extreme QX9000 (Yorkfield C0) / Pentium Dual-Cor 45nm");
e Processor E5000 (Wolfdale M0) / Xeon Processor 3100 (Wolfdale C0) / Xeon Proce FMSQ( 0, 6, 1, 7, 6, de, "Intel Core 2 Duo (Wolfdale C0) [Penryn], 45nm"
ssor 3300 (Yorkfield C0) / Xeon Processor 5200 (Wolfdale C0) / Xeon Processor 54 );
00 (Harpertown C0), 45nm"); FMSQ( 0, 6, 1, 7, 6, dc, "Intel Core 2 Duo (Wolfdale M0) [Penryn], 45nm"
FMSQ( 0, 6, 1, 7, 7, sQ, "Intel Xeon Processor 3300 (Yorkfield C1), 45nm );
"); FMSQ( 0, 6, 1, 7, 6, dP, "Intel Pentium Dual-Core Processor E5000 (Wolfd
FMSQ( 0, 6, 1, 7, 7, Xc, "Intel Core 2 Extreme QX9000 (Yorkfield C1), 45 ale M0) [Penryn], 45nm");
nm"); FMS ( 0, 6, 1, 7, 6, "Intel Core 2 Duo (Wolfdale C0/M0) / Mobile Cor
FMSQ( 0, 6, 1, 7, 7, Qe, "Intel Core 2 Quad-Core Q9000 (Yorkfield C1), 4 e 2 Duo (Penryn C0/M0) / Core 2 Extreme QX9000 (Yorkfield C0) / Pentium Dual-Cor
5nm"); e Processor E5000 (Wolfdale M0) / Xeon Processor 3100 (Wolfdale C0) / Xeon Proce
FMSQ( 0, 6, 1, 7, 7, Qc, "Intel Core 2 Quad-Core Q9000 (Yorkfield M1), 4 ssor 3300 (Yorkfield C0) / Xeon Processor 5200 (Wolfdale C0) / Xeon Processor 54
5nm"); 00 (Harpertown C0) [Penryn], 45nm");
FMS ( 0, 6, 1, 7, 7, "Intel Core 2 Quad-Core Q9000 (Yorkfield C1/M1) FMSQ( 0, 6, 1, 7, 7, sQ, "Intel Xeon Processor 3300 (Yorkfield C1) [Penr
/ Core 2 Extreme QX9000 (Yorkfield C1) / Xeon Processor 3300 (Yorkfield C1), 45 yn], 45nm");
nm"); FMSQ( 0, 6, 1, 7, 7, Xc, "Intel Core 2 Extreme QX9000 (Yorkfield C1) [Pe
FMSQ( 0, 6, 1, 7, 10, Me, "Intel Mobile Core 2 (Penryn E0), 45nm"); nryn], 45nm");
FMSQ( 0, 6, 1, 7, 10, Mc, "Intel Mobile Core 2 (Penryn R0), 45nm"); FMSQ( 0, 6, 1, 7, 7, Qe, "Intel Core 2 Quad-Core Q9000 (Yorkfield C1) [P
FMSQ( 0, 6, 1, 7, 10, Qe, "Intel Core 2 Quad-Core Q9000 (Yorkfield E0), 4 enryn], 45nm");
5nm"); FMSQ( 0, 6, 1, 7, 7, Qc, "Intel Core 2 Quad-Core Q9000 (Yorkfield M1) [P
FMSQ( 0, 6, 1, 7, 10, Qc, "Intel Core 2 Quad-Core Q9000 (Yorkfield R0), 4 enryn], 45nm");
5nm"); FMS ( 0, 6, 1, 7, 7, "Intel Core 2 Quad-Core Q9000 (Yorkfield C1/M1)
FMSQ( 0, 6, 1, 7, 10, de, "Intel Core 2 Duo (Wolfdale E0), 45nm"); / Core 2 Extreme QX9000 (Yorkfield C1) / Xeon Processor 3300 (Yorkfield C1) [Pe
FMSQ( 0, 6, 1, 7, 10, dc, "Intel Core 2 Duo (Wolfdale R0), 45nm"); nryn], 45nm");
FMSQ( 0, 6, 1, 7, 10, dP, "Intel Pentium Dual-Core Processor E5000/E6000 FMSQ( 0, 6, 1, 7, 10, Me, "Intel Mobile Core 2 (Penryn E0) [Penryn], 45nm
(Wolfdale R0), 45nm"); ");
FMSQ( 0, 6, 1, 7, 10, dC, "Intel Celeron E3000 (Wolfdale R0), 45nm"); FMSQ( 0, 6, 1, 7, 10, Mc, "Intel Mobile Core 2 (Penryn R0) [Penryn], 45nm
FMSQ( 0, 6, 1, 7, 10, se, "Intel Xeon Processor 3300 (Yorkfield E0), 45nm ");
"); FMSQ( 0, 6, 1, 7, 10, Qe, "Intel Core 2 Quad-Core Q9000 (Yorkfield E0) [P
FMSQ( 0, 6, 1, 7, 10, sQ, "Intel Xeon Processor 3300 (Yorkfield R0), 45nm enryn], 45nm");
"); FMSQ( 0, 6, 1, 7, 10, Qc, "Intel Core 2 Quad-Core Q9000 (Yorkfield R0) [P
FMSQ( 0, 6, 1, 7, 10, sX, "Intel Xeon Processor 3100 (Wolfdale E0) / Xeon enryn], 45nm");
Processor 3300 (Yorkfield R0) / Xeon Processor 5200 (Wolfdale E0) / Xeon Proces FMSQ( 0, 6, 1, 7, 10, de, "Intel Core 2 Duo (Wolfdale E0) [Penryn], 45nm"
sor 5400 (Harpertown E0), 45nm"); );
FMS ( 0, 6, 1, 7, 10, "Intel Core 2 Duo (Wolfdale E0/R0) / Core 2 Qua FMSQ( 0, 6, 1, 7, 10, dc, "Intel Core 2 Duo (Wolfdale R0) [Penryn], 45nm"
d-Core Q9000 (Yorkfield E0/R0) / Mobile Core 2 (Penryn E0/R0) / Pentium Dual-Cor );
e Processor E5000/E600 (Wolfdale R0) / Celeron E3000 (Wolfdale R0) / Xeon Proces FMSQ( 0, 6, 1, 7, 10, dP, "Intel Pentium Dual-Core Processor E5000/E6000
sor 3100 (Wolfdale E0) / Xeon Processor 3300 (Yorkfield E0/R0) / Xeon Processor (Wolfdale R0) [Penryn], 45nm");
5200 (Wolfdale E0) / Xeon Processor 5400 (Harpertown E0), 45nm"); FMSQ( 0, 6, 1, 7, 10, dC, "Intel Celeron E3000 (Wolfdale R0) [Penryn], 45
FMQ ( 0, 6, 1, 7, se, "Intel Xeon (Wolfdale / Yorkfield / Harpertown) nm");
, 45nm"); FMSQ( 0, 6, 1, 7, 10, se, "Intel Xeon Processor 3300 (Yorkfield E0) [Penr
FMQ ( 0, 6, 1, 7, sQ, "Intel Xeon (Wolfdale / Yorkfield / Harpertown) yn], 45nm");
, 45nm"); FMSQ( 0, 6, 1, 7, 10, sQ, "Intel Xeon Processor 3300 (Yorkfield R0) [Penr
FMQ ( 0, 6, 1, 7, sX, "Intel Xeon (Wolfdale / Yorkfield / Harpertown) yn], 45nm");
, 45nm"); FMSQ( 0, 6, 1, 7, 10, sX, "Intel Xeon Processor 3100 (Wolfdale E0) / Xeon
FMQ ( 0, 6, 1, 7, Mc, "Intel Mobile Core 2 (Penryn), 45nm"); Processor 3300 (Yorkfield R0) / Xeon Processor 5200 (Wolfdale E0) / Xeon Proces
FMQ ( 0, 6, 1, 7, Xc, "Intel Core 2 Extreme (Yorkfield), 45nm"); sor 5400 (Harpertown E0) [Penryn], 45nm");
FMQ ( 0, 6, 1, 7, Qc, "Intel Core 2 Quad-Core (Yorkfield), 45nm"); FMS ( 0, 6, 1, 7, 10, "Intel Core 2 Duo (Wolfdale E0/R0) / Core 2 Qua
FMQ ( 0, 6, 1, 7, dc, "Intel Core 2 Duo (Wolfdale), 45nm"); d-Core Q9000 (Yorkfield E0/R0) / Mobile Core 2 (Penryn E0/R0) / Pentium Dual-Cor
FMQ ( 0, 6, 1, 7, dC, "Intel Celeron (Wolfdale), 45nm"); e Processor E5000/E600 (Wolfdale R0) / Celeron E3000 (Wolfdale R0) / Xeon Proces
FMQ ( 0, 6, 1, 7, dP, "Intel Pentium Dual-Core (Wolfdale), 45nm"); sor 3100 (Wolfdale E0) / Xeon Processor 3300 (Yorkfield E0/R0) / Xeon Processor
FM ( 0, 6, 1, 7, "Intel Core 2 Duo (Wolfdale) / Mobile Core 2 (P 5200 (Wolfdale E0) / Xeon Processor 5400 (Harpertown E0) [Penryn], 45nm");
enryn) / Core 2 Quad-Core (Yorkfield) / Core 2 Extreme (Yorkfield) / Celeron (Wo FMQ ( 0, 6, 1, 7, se, "Intel Xeon (Wolfdale / Yorkfield / Harpertown)
lfdale) / Pentium Dual-Core (Wolfdale) / Xeon (Wolfdale / Yorkfield / Harpertown [Penryn], 45nm");
), 45nm"); FMQ ( 0, 6, 1, 7, sQ, "Intel Xeon (Wolfdale / Yorkfield / Harpertown)
[Penryn], 45nm");
FMQ ( 0, 6, 1, 7, sX, "Intel Xeon (Wolfdale / Yorkfield / Harpertown)
[Penryn], 45nm");
FMQ ( 0, 6, 1, 7, Mc, "Intel Mobile Core 2 (Penryn) [Penryn], 45nm");
FMQ ( 0, 6, 1, 7, Xc, "Intel Core 2 Extreme (Yorkfield) [Penryn], 45n
m");
FMQ ( 0, 6, 1, 7, Qc, "Intel Core 2 Quad-Core (Yorkfield) [Penryn], 4
5nm");
FMQ ( 0, 6, 1, 7, dc, "Intel Core 2 Duo (Wolfdale) [Penryn], 45nm");
FMQ ( 0, 6, 1, 7, dC, "Intel Celeron (Wolfdale) [Penryn], 45nm");
FMQ ( 0, 6, 1, 7, dP, "Intel Pentium Dual-Core (Wolfdale) [Penryn], 4
5nm");
FM ( 0, 6, 1, 7, "Intel Core 2 Duo (Wolfdale) / Mobile Core 2 (P
enryn) / Core 2 Quad-Core (Yorkfield) / Core 2 Extreme (Yorkfield) / Celeron (Wo
lfdale) / Pentium Dual-Core (Wolfdale) / Xeon (Wolfdale / Yorkfield / Harpertown
) [Penryn], 45nm");
FMS ( 0, 6, 1,10, 4, "Intel Core i7-900 (Bloomfield C0), 45nm"); FMS ( 0, 6, 1,10, 4, "Intel Core i7-900 (Bloomfield C0), 45nm");
FMSQ( 0, 6, 1,10, 5, dc, "Intel Core i7-900 (Bloomfield D0), 45nm"); FMSQ( 0, 6, 1,10, 5, dc, "Intel Core i7-900 (Bloomfield D0), 45nm");
FMSQ( 0, 6, 1,10, 5, sX, "Intel Xeon Processor 3500 (Bloomfield D0) / Xe on Processor 5500 (Gainestown D0), 45nm"); FMSQ( 0, 6, 1,10, 5, sX, "Intel Xeon Processor 3500 (Bloomfield D0) / Xe on Processor 5500 (Gainestown D0), 45nm");
FMS ( 0, 6, 1,10, 5, "Intel Core i7-900 (Bloomfield D0) / Xeon Proce ssor 3500 (Bloomfield D0) / Xeon Processor 5500 (Gainestown D0), 45nm"); FMS ( 0, 6, 1,10, 5, "Intel Core i7-900 (Bloomfield D0) / Xeon Proce ssor 3500 (Bloomfield D0) / Xeon Processor 5500 (Gainestown D0), 45nm");
FMQ ( 0, 6, 1,10, dc, "Intel Core (Bloomfield), 45nm"); FMQ ( 0, 6, 1,10, dc, "Intel Core (Bloomfield), 45nm");
FMQ ( 0, 6, 1,10, sX, "Intel Xeon (Bloomfield / Gainestown), 45nm"); FMQ ( 0, 6, 1,10, sX, "Intel Xeon (Bloomfield / Gainestown), 45nm");
FM ( 0, 6, 1,10, "Intel Core (Bloomfield) / Xeon (Bloomfield / G ainestown), 45nm"); FM ( 0, 6, 1,10, "Intel Core (Bloomfield) / Xeon (Bloomfield / G ainestown), 45nm");
FMS ( 0, 6, 1,12, 1, "Intel Atom N270 (Diamondville B0), 45nm"); FMS ( 0, 6, 1,12, 1, "Intel Atom N270 (Diamondville B0) [Bonnell], 4
FMS ( 0, 6, 1,12, 2, "Intel Atom 200/N200/300 (Diamondville C0) / At 5nm");
om Z500 (Silverthorne C0), 45nm"); FMS ( 0, 6, 1,12, 2, "Intel Atom 200/N200/300 (Diamondville C0) / At
FMS ( 0, 6, 1,12, 10, "Intel Atom D400/N400 (Pineview A0) / Atom D500 om Z500 (Silverthorne C0) [Bonnell], 45nm");
/N500 (Pineview B0), 45nm"); FMS ( 0, 6, 1,12, 10, "Intel Atom D400/N400 (Pineview A0) / Atom D500
FM ( 0, 6, 1,12, "Intel Atom (Diamondville / Silverthorne / Pine /N500 (Pineview B0) [Bonnell], 45nm");
view), 45nm"); FM ( 0, 6, 1,12, "Intel Atom (Diamondville / Silverthorne / Pine
FMS ( 0, 6, 1,13, 1, "Intel Xeon Processor 7400 (Dunnington A1), 45n view) [Bonnell], 45nm");
m"); FMS ( 0, 6, 1,13, 1, "Intel Xeon Processor 7400 (Dunnington A1) [Pen
FM ( 0, 6, 1,13, "Intel Xeon (Dunnington), 45nm"); ryn], 45nm");
FMSQ( 0, 6, 1,14, 4, sX, "Intel Xeon Processor C3500/C5500 (Jasper Fores FM ( 0, 6, 1,13, "Intel Xeon (Dunnington) [Penryn], 45nm");
t B0), 45nm"); FMSQ( 0, 6, 1,14, 4, sX, "Intel Xeon Processor C3500/C5500 (Jasper Fores
FMSQ( 0, 6, 1,14, 4, dC, "Intel Celeron P1053 (Jasper Forest B0), 45nm") t B0) [Nehalem], 45nm");
; FMSQ( 0, 6, 1,14, 4, dC, "Intel Celeron P1053 (Jasper Forest B0) [Nehale
FMQ ( 0, 6, 1,14, sX, "Intel Xeon Processor C3500/C5500 (Jasper Fores m], 45nm");
t B0) / Celeron P1053 (Jasper Forest B0), 45nm"); FMQ ( 0, 6, 1,14, sX, "Intel Xeon Processor C3500/C5500 (Jasper Fores
FMSQ( 0, 6, 1,14, 5, sX, "Intel Xeon Processor 3400 (Lynnfield B1), 45nm t B0) / Celeron P1053 (Jasper Forest B0) [Nehalem], 45nm");
"); FMSQ( 0, 6, 1,14, 5, sX, "Intel Xeon Processor 3400 (Lynnfield B1) [Neha
FMSQ( 0, 6, 1,14, 5, Mc, "Intel Core i7-700/800/900 Mobile (Clarksfield lem], 45nm");
B1), 45nm"); FMSQ( 0, 6, 1,14, 5, Mc, "Intel Core i7-700/800/900 Mobile (Clarksfield
FMSQ( 0, 6, 1,14, 5, dc, "Intel Core i5-700 / i7-800 (Lynnfield B1), 45n B1) [Nehalem], 45nm");
m"); FMSQ( 0, 6, 1,14, 5, dc, "Intel Core i5-700 / i7-800 (Lynnfield B1) [Neh
FMS ( 0, 6, 1,14, 5, "Intel Intel Core i5-700 / i7-800 (Lynnfield B1 alem], 45nm");
) / Core i7-700/800/900 Mobile (Clarksfield B1) / Xeon Processor 3400 (Lynnfield FMS ( 0, 6, 1,14, 5, "Intel Intel Core i5-700 / i7-800 (Lynnfield B1
B1), 45nm"); ) / Core i7-700/800/900 Mobile (Clarksfield B1) / Xeon Processor 3400 (Lynnfield
FMQ ( 0, 6, 1,14, sX, "Intel Xeon (Lynnfield) / Xeon (Jasper Forest), B1) [Nehalem], 45nm");
45nm"); FMQ ( 0, 6, 1,14, sX, "Intel Xeon (Lynnfield) / Xeon (Jasper Forest)
FMQ ( 0, 6, 1,14, dC, "Intel Celeron (Jasper Forest), 45nm"); [Nehalem], 45nm");
FMQ ( 0, 6, 1,14, Mc, "Intel Core Mobile (Clarksfield), 45nm"); FMQ ( 0, 6, 1,14, dC, "Intel Celeron (Jasper Forest) [Nehalem], 45nm"
FMQ ( 0, 6, 1,14, dc, "Intel Core (Lynnfield), 45nm"); );
FM ( 0, 6, 1,14, "Intel Intel Core (Lynnfield) / Core Mobile (Cl FMQ ( 0, 6, 1,14, Mc, "Intel Core Mobile (Clarksfield) [Nehalem], 45n
arksfield) / Xeon (Lynnfield) / Xeon (Jasper Forest), 45nm"); m");
FMQ ( 0, 6, 1,14, dc, "Intel Core (Lynnfield) [Nehalem], 45nm");
FM ( 0, 6, 1,14, "Intel Intel Core (Lynnfield) / Core Mobile (Cl
arksfield) / Xeon (Lynnfield) / Xeon (Jasper Forest) [Nehalem], 45nm");
FMSQ( 0, 6, 2, 5, 2, sX, "Intel Xeon Processor L3406 (Clarkdale C2), 32n m"); FMSQ( 0, 6, 2, 5, 2, sX, "Intel Xeon Processor L3406 (Clarkdale C2), 32n m");
FMSQ( 0, 6, 2, 5, 2, MC, "Intel Celeron Mobile P4500 (Arrandale C2), 32n m"); FMSQ( 0, 6, 2, 5, 2, MC, "Intel Celeron Mobile P4500 (Arrandale C2), 32n m");
FMSQ( 0, 6, 2, 5, 2, MP, "Intel Pentium P6000 Mobile (Arrandale C2), 32n m"); FMSQ( 0, 6, 2, 5, 2, MP, "Intel Pentium P6000 Mobile (Arrandale C2), 32n m");
FMSQ( 0, 6, 2, 5, 2, dP, "Intel Pentium G6900 / P4505 (Clarkdale C2), 32 nm"); FMSQ( 0, 6, 2, 5, 2, dP, "Intel Pentium G6900 / P4505 (Clarkdale C2), 32 nm");
FMSQ( 0, 6, 2, 5, 2, Mc, "Intel Core i3-300 Mobile / Core i5-400 Mobile / Core i5-500 Mobile / Core i7-600 Mobile (Arrandale C2), 32nm"); FMSQ( 0, 6, 2, 5, 2, Mc, "Intel Core i3-300 Mobile / Core i5-400 Mobile / Core i5-500 Mobile / Core i7-600 Mobile (Arrandale C2), 32nm");
FMSQ( 0, 6, 2, 5, 2, dc, "Intel Core i3-300 / i3-500 / i5-500 / i5-600 / i7-600 (Clarkdale C2), 32nm"); FMSQ( 0, 6, 2, 5, 2, dc, "Intel Core i3-300 / i3-500 / i5-500 / i5-600 / i7-600 (Clarkdale C2), 32nm");
FMS ( 0, 6, 2, 5, 2, "Intel Core i3 / i5 / i7 (Clarkdale C2) / Core i3 Mobile / Core i5 Mobile / Core i7 Mobile (Arrandale C2) / Pentium P6000 Mobil e (Arrandale C2) / Celeron Mobile P4500 (Arrandale C2) / Xeon Processor L3406 (C larkdale C2), 32nm"); FMS ( 0, 6, 2, 5, 2, "Intel Core i3 / i5 / i7 (Clarkdale C2) / Core i3 Mobile / Core i5 Mobile / Core i7 Mobile (Arrandale C2) / Pentium P6000 Mobil e (Arrandale C2) / Celeron Mobile P4500 (Arrandale C2) / Xeon Processor L3406 (C larkdale C2), 32nm");
FMSQ( 0, 6, 2, 5, 5, MC, "Intel Celeron Celeron Mobile U3400 (Arrandale K0) / Celeron Mobile P4600 (Arrandale K0), 32nm"); FMSQ( 0, 6, 2, 5, 5, MC, "Intel Celeron Celeron Mobile U3400 (Arrandale K0) / Celeron Mobile P4600 (Arrandale K0), 32nm");
FMSQ( 0, 6, 2, 5, 5, MP, "Intel Pentium U5000 Mobile (Arrandale K0), 32n m"); FMSQ( 0, 6, 2, 5, 5, MP, "Intel Pentium U5000 Mobile (Arrandale K0), 32n m");
FMSQ( 0, 6, 2, 5, 5, dP, "Intel Pentium P4505 / U3405 (Clarkdale K0), 32 nm"); FMSQ( 0, 6, 2, 5, 5, dP, "Intel Pentium P4505 / U3405 (Clarkdale K0), 32 nm");
FMSQ( 0, 6, 2, 5, 5, dc, "Intel Core i3-300 / i3-500 / i5-400 / i5-500 / i5-600 / i7-600 (Clarkdale K0), 32nm"); FMSQ( 0, 6, 2, 5, 5, dc, "Intel Core i3-300 / i3-500 / i5-400 / i5-500 / i5-600 / i7-600 (Clarkdale K0), 32nm");
FMS ( 0, 6, 2, 5, 5, "Intel Core i3 / i5 / i7 (Clarkdale K0) / Pent ium U5000 Mobile / Pentium P4505 / U3405 / Celeron Mobile P4000 / U3000 (Arranda le K0), 32nm"); FMS ( 0, 6, 2, 5, 5, "Intel Core i3 / i5 / i7 (Clarkdale K0) / Pent ium U5000 Mobile / Pentium P4505 / U3405 / Celeron Mobile P4000 / U3000 (Arranda le K0), 32nm");
FMQ ( 0, 6, 2, 5, sX, "Intel Xeon Processor L3406 (Clarkdale), 32nm") ; FMQ ( 0, 6, 2, 5, sX, "Intel Xeon Processor L3406 (Clarkdale), 32nm") ;
FMQ ( 0, 6, 2, 5, MC, "Intel Celeron Mobile (Arrandale), 32nm"); FMQ ( 0, 6, 2, 5, MC, "Intel Celeron Mobile (Arrandale), 32nm");
FMQ ( 0, 6, 2, 5, MP, "Intel Pentium Mobile (Arrandale), 32nm"); FMQ ( 0, 6, 2, 5, MP, "Intel Pentium Mobile (Arrandale), 32nm");
FMQ ( 0, 6, 2, 5, dP, "Intel Pentium (Clarkdale), 32nm"); FMQ ( 0, 6, 2, 5, dP, "Intel Pentium (Clarkdale), 32nm");
FMQ ( 0, 6, 2, 5, Mc, "Intel Core Mobile (Arrandale), 32nm"); FMQ ( 0, 6, 2, 5, Mc, "Intel Core Mobile (Arrandale), 32nm");
FMQ ( 0, 6, 2, 5, dc, "Intel Core (Clarkdale), 32nm"); FMQ ( 0, 6, 2, 5, dc, "Intel Core (Clarkdale), 32nm");
FM ( 0, 6, 2, 5, "Intel Core (Clarkdale) / Core (Arrandale) / Pe ntium (Clarkdale) / Pentium Mobile (Arrandale) / Celeron Mobile (Arrandale) / Xe on (Clarkdale), 32nm"); FM ( 0, 6, 2, 5, "Intel Core (Clarkdale) / Core (Arrandale) / Pe ntium (Clarkdale) / Pentium Mobile (Arrandale) / Celeron Mobile (Arrandale) / Xe on (Clarkdale), 32nm");
FMS ( 0, 6, 2, 6, 1, "Intel Atom Z600 (Lincroft C0) / Atom E600 (Tun FMS ( 0, 6, 2, 6, 1, "Intel Atom Z600 (Lincroft C0) / Atom E600 (Tun
nel Creek B0/B1), 45nm"); nel Creek B0/B1) [Bonnell], 45nm");
FM ( 0, 6, 2, 6, "Intel Atom Z600 (Lincroft) / Atom E600 (Tunnel FM ( 0, 6, 2, 6, "Intel Atom Z600 (Lincroft) / Atom E600 (Tunnel
Creek B0/B1), 45nm"); Creek B0/B1) [Bonnell], 45nm");
FMSQ( 0, 6, 2,10, 7, Xc, "Intel Mobile Core i7 Extreme (Sandy Bridge D2/ J1/Q0), 32nm"); FMSQ( 0, 6, 2,10, 7, Xc, "Intel Mobile Core i7 Extreme (Sandy Bridge D2/ J1/Q0), 32nm");
FMSQ( 0, 6, 2,10, 7, Mc, "Intel Mobile Core i3-2000 / Mobile Core i5-200 0 / Mobile Core i7-2000 (Sandy Bridge D2/J1/Q0), 32nm"); FMSQ( 0, 6, 2,10, 7, Mc, "Intel Mobile Core i3-2000 / Mobile Core i5-200 0 / Mobile Core i7-2000 (Sandy Bridge D2/J1/Q0), 32nm");
FMSQ( 0, 6, 2,10, 7, dc, "Intel Core i3-2000 / Core i5-2000 / Core i7-20 00 (Sandy Bridge D2/J1/Q0), 32nm"); FMSQ( 0, 6, 2,10, 7, dc, "Intel Core i3-2000 / Core i5-2000 / Core i7-20 00 (Sandy Bridge D2/J1/Q0), 32nm");
FMSQ( 0, 6, 2,10, 7, MC, "Intel Celeron G400/G500/700/800/B800 (Sandy Br idge J1/Q0), 32nm"); FMSQ( 0, 6, 2,10, 7, MC, "Intel Celeron G400/G500/700/800/B800 (Sandy Br idge J1/Q0), 32nm");
FMSQ( 0, 6, 2,10, 7, sX, "Intel Xeon E3-1100 / E3-1200 v1 (Sandy Bridge D2/J1/Q0), 32nm"); FMSQ( 0, 6, 2,10, 7, sX, "Intel Xeon E3-1100 / E3-1200 v1 (Sandy Bridge D2/J1/Q0), 32nm");
FMSQ( 0, 6, 2,10, 7, dP, "Intel Pentium G500/G600/G800 / Pentium B915C ( Sandy Bridge Q0), 32nm"); FMSQ( 0, 6, 2,10, 7, dP, "Intel Pentium G500/G600/G800 / Pentium B915C ( Sandy Bridge Q0), 32nm");
FMS ( 0, 6, 2,10, 7, "Intel Core i3-2000 / Core i5-2000 / Core i7-20 00 / Mobile Core i7-2000 (Sandy Bridge D2/J1/Q0) / Pentium G500/G600/G800 / Pent ium B915C (Sandy Bridge Q0) / Celeron G400/G500/700/800/B800 (Sandy Bridge J1/Q0 ) / Xeon E1-1100 / E3-1200 (Sandy Bridge D2/J1/Q0), 32nm"); FMS ( 0, 6, 2,10, 7, "Intel Core i3-2000 / Core i5-2000 / Core i7-20 00 / Mobile Core i7-2000 (Sandy Bridge D2/J1/Q0) / Pentium G500/G600/G800 / Pent ium B915C (Sandy Bridge Q0) / Celeron G400/G500/700/800/B800 (Sandy Bridge J1/Q0 ) / Xeon E1-1100 / E3-1200 (Sandy Bridge D2/J1/Q0), 32nm");
FMQ ( 0, 6, 2,10, Xc, "Intel Mobile Core i7 Extreme (Sandy Bridge), 3 2nm"); FMQ ( 0, 6, 2,10, Xc, "Intel Mobile Core i7 Extreme (Sandy Bridge), 3 2nm");
FMQ ( 0, 6, 2,10, Mc, "Intel Mobile Core i3-2000 / Mobile Core i5-200 0 / Mobile Core i7-2000 (Sandy Bridge), 32nm"); FMQ ( 0, 6, 2,10, Mc, "Intel Mobile Core i3-2000 / Mobile Core i5-200 0 / Mobile Core i7-2000 (Sandy Bridge), 32nm");
FMQ ( 0, 6, 2,10, dc, "Intel Core i5-2000 / Core i7-2000 (Sandy Bridg e), 32nm"); FMQ ( 0, 6, 2,10, dc, "Intel Core i5-2000 / Core i7-2000 (Sandy Bridg e), 32nm");
FMQ ( 0, 6, 2,10, MC, "Intel Celeron G400/G500/700/800/B800 (Sandy Br idge), 32nm"); FMQ ( 0, 6, 2,10, MC, "Intel Celeron G400/G500/700/800/B800 (Sandy Br idge), 32nm");
FMQ ( 0, 6, 2,10, sX, "Intel Xeon E3-1100 / E3-1200 v1 (Sandy Bridge) , 32nm"); FMQ ( 0, 6, 2,10, sX, "Intel Xeon E3-1100 / E3-1200 v1 (Sandy Bridge) , 32nm");
FMQ ( 0, 6, 2,10, dP, "Intel Pentium G500/G600/G800 / Pentium B915C ( Sandy Bridge), 32nm"); FMQ ( 0, 6, 2,10, dP, "Intel Pentium G500/G600/G800 / Pentium B915C ( Sandy Bridge), 32nm");
FM ( 0, 6, 2,10, "Intel Core i5-2000 / Core i7-2000 / Mobile Cor e i3-2000 / Mobile Core i5-2000 / Mobile Core i7-2000 / Pentium G500/G600/G800 / Pentium B915C / Celeron G400/G500/700/800/B800 / Xeon E1-1100 / E3-1200 (Sandy Bridge), 32nm"); FM ( 0, 6, 2,10, "Intel Core i5-2000 / Core i7-2000 / Mobile Cor e i3-2000 / Mobile Core i5-2000 / Mobile Core i7-2000 / Pentium G500/G600/G800 / Pentium B915C / Celeron G400/G500/700/800/B800 / Xeon E1-1100 / E3-1200 (Sandy Bridge), 32nm");
FMSQ( 0, 6, 2,12, 2, dc, "Intel Core i7-900 / Core i7-980X (Gulftown B1) FMSQ( 0, 6, 2,12, 2, dc, "Intel Core i7-900 / Core i7-980X (Gulftown B1)
, 32nm"); [Westmere], 32nm");
FMSQ( 0, 6, 2,12, 2, sX, "Intel Xeon Processor 3600 (Westmere-EP B1) / X FMSQ( 0, 6, 2,12, 2, sX, "Intel Xeon Processor 3600 (Westmere-EP B1) / X
eon Processor 5600 (Westmere-EP B1), 32nm"); eon Processor 5600 (Westmere-EP B1) [Westmere], 32nm");
FMS ( 0, 6, 2,12, 2, "Intel Core i7-900 (Gulftown B1) / Core i7-980X FMS ( 0, 6, 2,12, 2, "Intel Core i7-900 (Gulftown B1) / Core i7-980X
(Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Wes (Gulftown B1) / Xeon Processor 3600 (Westmere-EP B1) / Xeon Processor 5600 (Wes
tmere-EP B1), 32nm"); tmere-EP B1) [Westmere], 32nm");
FM ( 0, 6, 2,12, "Intel Core (Gulftown) / Xeon (Westmere-EP), 32 FM ( 0, 6, 2,12, "Intel Core (Gulftown) / Xeon (Westmere-EP) [We
nm"); stmere], 32nm");
FMSQ( 0, 6, 2,13, 6, sX, "Intel Xeon E5-1600/2600 (Sandy Bridge-E C1), 3 2nm"); FMSQ( 0, 6, 2,13, 6, sX, "Intel Xeon E5-1600/2600 (Sandy Bridge-E C1), 3 2nm");
FMSQ( 0, 6, 2,13, 6, dP, "Intel Core i7-3800/3900 (Sandy Bridge-E C1), 3 2nm"); FMSQ( 0, 6, 2,13, 6, dP, "Intel Core i7-3800/3900 (Sandy Bridge-E C1), 3 2nm");
FMS ( 0, 6, 2,13, 6, "Intel Core i7-3800/3900 (Sandy Bridge-E C1) / Xeon E5-1600/2600 (Sandy Bridge-E C1), 32nm"); FMS ( 0, 6, 2,13, 6, "Intel Core i7-3800/3900 (Sandy Bridge-E C1) / Xeon E5-1600/2600 (Sandy Bridge-E C1), 32nm");
FMSQ( 0, 6, 2,13, 7, sX, "Intel Xeon E5-1600/2600/4600 (Sandy Bridge-E C 2/M1), 32nm"); FMSQ( 0, 6, 2,13, 7, sX, "Intel Xeon E5-1600/2600/4600 (Sandy Bridge-E C 2/M1), 32nm");
FMSQ( 0, 6, 2,13, 7, dP, "Intel Core i7-3800/3900 (Sandy Bridge-E C2), 3 2nm"); FMSQ( 0, 6, 2,13, 7, dP, "Intel Core i7-3800/3900 (Sandy Bridge-E C2), 3 2nm");
FMS ( 0, 6, 2,13, 7, "Intel Core i7-3800/3900 (Sandy Bridge-E C2) / Xeon E5-1600/2600/4600 (Sandy Bridge-E C2/M1), 32nm"); FMS ( 0, 6, 2,13, 7, "Intel Core i7-3800/3900 (Sandy Bridge-E C2) / Xeon E5-1600/2600/4600 (Sandy Bridge-E C2/M1), 32nm");
FMQ ( 0, 6, 2,13, sX, "Intel Xeon E5-1600/2600 (Sandy Bridge-E), 32nm "); FMQ ( 0, 6, 2,13, sX, "Intel Xeon E5-1600/2600 (Sandy Bridge-E), 32nm ");
FMQ ( 0, 6, 2,13, dP, "Intel Core i7-3800/3900 (Sandy Bridge-E), 32nm "); FMQ ( 0, 6, 2,13, dP, "Intel Core i7-3800/3900 (Sandy Bridge-E), 32nm ");
FM ( 0, 6, 2,13, "Intel Core i7-3800/3900 (Sandy Bridge-E) / Xeo n E5-1600/2600/4600 (Sandy Bridge-E), 32nm"); FM ( 0, 6, 2,13, "Intel Core i7-3800/3900 (Sandy Bridge-E) / Xeo n E5-1600/2600/4600 (Sandy Bridge-E), 32nm");
FMS ( 0, 6, 2,14, 6, "Intel Xeon Processor 7500 (Beckton D0), 45nm") ; FMS ( 0, 6, 2,14, 6, "Intel Xeon Processor 7500 (Beckton D0), 45nm") ;
FM ( 0, 6, 2,14, "Intel Xeon (Beckton), 45nm"); FM ( 0, 6, 2,14, "Intel Xeon (Beckton), 45nm");
FMS ( 0, 6, 2,15, 2, "Intel Xeon E7-8800 / Xeon E7-4800 / Xeon E7-28 FMS ( 0, 6, 2,15, 2, "Intel Xeon E7-8800 / Xeon E7-4800 / Xeon E7-28
00 (Westmere-EX A2), 32nm"); 00 (Westmere-EX A2) [Westmere], 32nm");
FM ( 0, 6, 2,15, "Intel Xeon E7-8800 / Xeon E7-4800 / Xeon E7-28 FM ( 0, 6, 2,15, "Intel Xeon E7-8800 / Xeon E7-4800 / Xeon E7-28
00 (Westmere-EX), 32nm"); 00 (Westmere-EX) [Westmere], 32nm");
FMS ( 0, 6, 3, 5, 1, "Intel Atom Z2760 (Clover Trail C0) / Z8000 (Ch FMS ( 0, 6, 3, 5, 1, "Intel Atom Z2760 (Clover Trail C0) / Z8000 (Ch
erry Trail C0), 14nm"); erry Trail C0) [Saltwell], 14nm");
FM ( 0, 6, 3, 5, "Intel Atom Z2760 (Clover Trail) / Z8000 (Cherr FM ( 0, 6, 3, 5, "Intel Atom Z2760 (Clover Trail) / Z8000 (Cherr
y Trail), 14nm"); y Trail) [Saltwell], 14nm");
// Intel docs (328198) do not provide any FMS for Centerton, but an example // Intel docs (328198) do not provide any FMS for Centerton, but an example
// from jhladky@redhat.com does. // from jhladky@redhat.com does.
FMS ( 0, 6, 3, 6, 1, "Intel Atom D2000/N2000 (Cedarview B1/B2/B3) / FMS ( 0, 6, 3, 6, 1, "Intel Atom D2000/N2000 (Cedarview B1/B2/B3) /
S1200 (Centerton B1), 32nm"); S1200 (Centerton B1) [Saltwell], 32nm");
FM ( 0, 6, 3, 6, "Intel Atom D2000/N2000 (Cedarview) / S1200 (Ce FM ( 0, 6, 3, 6, "Intel Atom D2000/N2000 (Cedarview) / S1200 (Ce
nterton B1), 32nm"); nterton B1) [Saltwell], 32nm");
FMS ( 0, 6, 3, 7, 1, "Intel Atom Z3000 (Bay Trail-T A0), 22nm"); FMS ( 0, 6, 3, 7, 1, "Intel Atom Z3000 (Bay Trail-T A0) [Silvermont]
FMS ( 0, 6, 3, 7, 2, "Intel Pentium / Celeron (Bay Trail-M B0/B1), 2 , 22nm");
2nm"); FMS ( 0, 6, 3, 7, 2, "Intel Pentium / Celeron (Bay Trail-M B0/B1) [S
FMS ( 0, 6, 3, 7, 3, "Intel Pentium N3500 / J2850 / Celeron N1700 / ilvermont], 22nm");
N1800 / N2800 / N2900 (Bay Trail-M B2/B3) / Atom E3800 (Bay Trail-I B3), 22nm"); FMS ( 0, 6, 3, 7, 3, "Intel Pentium N3500 / J2850 / Celeron N1700 /
FMSQ( 0, 6, 3, 7, 4, dC, "Intel Celeron N2800 / N2900 (Bay Trail-M C0), N1800 / N2800 / N2900 (Bay Trail-M B2/B3) / Atom E3800 (Bay Trail-I B3) [Silverm
22nm"); ont], 22nm");
FMSQ( 0, 6, 3, 7, 4, dP, "Intel Pentium N3500 (Bay Trail-M C0), 22nm"); FMSQ( 0, 6, 3, 7, 4, dC, "Intel Celeron N2800 / N2900 (Bay Trail-M C0) [
FMS ( 0, 6, 3, 7, 4, "Intel Pentium N3500 / Celeron N2800 / N2900 (B Silvermont], 22nm");
ay Trail-M C0) / Atom Z3000 (Bay Trail-T B2/B3), 22nm"); FMSQ( 0, 6, 3, 7, 4, dP, "Intel Pentium N3500 (Bay Trail-M C0) [Silvermo
FMS ( 0, 6, 3, 7, 9, "Intel Atom E3800 (Bay Trail-I D0), 22nm"); nt], 22nm");
FM ( 0, 6, 3, 7, "Intel Pentium N3500 / J2850 / Celeron N1700 / FMS ( 0, 6, 3, 7, 4, "Intel Pentium N3500 / Celeron N2800 / N2900 (B
N1800 / N2800 / N2900 (Bay Trail-M) / Atom Z3000 (Bay Trail-T) / Atom E3800 (Bay ay Trail-M C0) / Atom Z3000 (Bay Trail-T B2/B3) [Silvermont], 22nm");
Trail-I), 22nm"); FMS ( 0, 6, 3, 7, 9, "Intel Atom E3800 (Bay Trail-I D0) [Silvermont]
, 22nm");
FM ( 0, 6, 3, 7, "Intel Pentium N3500 / J2850 / Celeron N1700 /
N1800 / N2800 / N2900 (Bay Trail-M) / Atom Z3000 (Bay Trail-T) / Atom E3800 (Bay
Trail-I) [Silvermont], 22nm");
FMSQ( 0, 6, 3,10, 9, Mc, "Intel Mobile Core i3-3000 (Ivy Bridge L1) / i5 -3000 (Ivy Bridge L1) / i7-3000 (Ivy Bridge E1/L1) / Pentium 900/1000/2000/2100 (P0), 22nm"); FMSQ( 0, 6, 3,10, 9, Mc, "Intel Mobile Core i3-3000 (Ivy Bridge L1) / i5 -3000 (Ivy Bridge L1) / i7-3000 (Ivy Bridge E1/L1) / Pentium 900/1000/2000/2100 (P0), 22nm");
FMSQ( 0, 6, 3,10, 9, dc, "Intel Core i3-3000 (Ivy Bridge L1) / i5-3000 ( Ivy Bridge E1/N0/L1) / i7-3000 (Ivy Bridge E1), 22nm"); FMSQ( 0, 6, 3,10, 9, dc, "Intel Core i3-3000 (Ivy Bridge L1) / i5-3000 ( Ivy Bridge E1/N0/L1) / i7-3000 (Ivy Bridge E1), 22nm");
FMSQ( 0, 6, 3,10, 9, sX, "Intel Xeon E3-1100 v2 / E3-1200 v2 (Ivy Bridge E1/N0/L1), 22nm"); FMSQ( 0, 6, 3,10, 9, sX, "Intel Xeon E3-1100 v2 / E3-1200 v2 (Ivy Bridge E1/N0/L1), 22nm");
FMSQ( 0, 6, 3,10, 9, dP, "Intel Pentium G1600/G2000/G2100 / Pentium B925 C (Ivy Bridge P0), 22nm"); FMSQ( 0, 6, 3,10, 9, dP, "Intel Pentium G1600/G2000/G2100 / Pentium B925 C (Ivy Bridge P0), 22nm");
FMS ( 0, 6, 3,10, 9, "Intel Core i3-3000 (Ivy Bridge L1) / i5-3000 ( Ivy Bridge E1/N0/L1) / i7-3000 (Ivy Bridge E1) / Mobile Core i3-3000 (Ivy Bridge L1) / i5-3000 (Ivy Bridge L1) / Mobile Core i7-3000 (Ivy Bridge E1/L1) / Xeon E 3-1100 v2 / E3-1200 v2 (Ivy Bridge E1/N0/L1) / Pentium G1600/G2000/G2100 / Penti um B925C (Ivy Bridge P0) / Pentium 900/1000/2000/2100 (P0), 22nm"); FMS ( 0, 6, 3,10, 9, "Intel Core i3-3000 (Ivy Bridge L1) / i5-3000 ( Ivy Bridge E1/N0/L1) / i7-3000 (Ivy Bridge E1) / Mobile Core i3-3000 (Ivy Bridge L1) / i5-3000 (Ivy Bridge L1) / Mobile Core i7-3000 (Ivy Bridge E1/L1) / Xeon E 3-1100 v2 / E3-1200 v2 (Ivy Bridge E1/N0/L1) / Pentium G1600/G2000/G2100 / Penti um B925C (Ivy Bridge P0) / Pentium 900/1000/2000/2100 (P0), 22nm");
FMQ ( 0, 6, 3,10, Mc, "Intel Mobile Core i3-3000 (Ivy Bridge) / Mobil e Core i5-3000 (Ivy Bridge) / Mobile Core i7-3000 (Ivy Bridge) / Pentium 900/100 0/2000/2100, 22nm"); FMQ ( 0, 6, 3,10, Mc, "Intel Mobile Core i3-3000 (Ivy Bridge) / Mobil e Core i5-3000 (Ivy Bridge) / Mobile Core i7-3000 (Ivy Bridge) / Pentium 900/100 0/2000/2100, 22nm");
FMQ ( 0, 6, 3,10, dc, "Intel Core i3-3000 (Ivy Bridge) / i5-3000 (Ivy Bridge) / i7-3000 (Ivy Bridge), 22nm"); FMQ ( 0, 6, 3,10, dc, "Intel Core i3-3000 (Ivy Bridge) / i5-3000 (Ivy Bridge) / i7-3000 (Ivy Bridge), 22nm");
FMQ ( 0, 6, 3,10, sX, "Intel Xeon E3-1100 v2 / E3-1200 v2 (Ivy Bridge ), 22nm"); FMQ ( 0, 6, 3,10, sX, "Intel Xeon E3-1100 v2 / E3-1200 v2 (Ivy Bridge ), 22nm");
FMQ ( 0, 6, 3,10, dP, "Intel Pentium G1600/G2000/G2100 / Pentium B925 C (Ivy Bridge), 22nm"); FMQ ( 0, 6, 3,10, dP, "Intel Pentium G1600/G2000/G2100 / Pentium B925 C (Ivy Bridge), 22nm");
FM ( 0, 6, 3,10, "Intel Core i3-3000 (Ivy Bridge) / i5-3000 (Ivy Bridge) / i7-3000 (Ivy Bridge) / Mobile Core i3-3000 (Ivy Bridge) / Mobile Core i5-3000 (Ivy Bridge) / Mobile Core i7-3000 (Ivy Bridge) / Xeon E3-1100 v2 / E3- 1200 v2 (Ivy Bridge) / Pentium G1600/G2000/G2100 (Ivy Bridge) / Pentium 900/1000 /2000/2100 / Pentium B925C, 22nm"); FM ( 0, 6, 3,10, "Intel Core i3-3000 (Ivy Bridge) / i5-3000 (Ivy Bridge) / i7-3000 (Ivy Bridge) / Mobile Core i3-3000 (Ivy Bridge) / Mobile Core i5-3000 (Ivy Bridge) / Mobile Core i7-3000 (Ivy Bridge) / Xeon E3-1100 v2 / E3- 1200 v2 (Ivy Bridge) / Pentium G1600/G2000/G2100 (Ivy Bridge) / Pentium 900/1000 /2000/2100 / Pentium B925C, 22nm");
skipping to change at line 2210 skipping to change at line 2257
FMQ ( 0, 6, 4, 6, dC, "Intel Celeron G1800 (Desktop R) (Haswell), 22n m"); FMQ ( 0, 6, 4, 6, dC, "Intel Celeron G1800 (Desktop R) (Haswell), 22n m");
FMQ ( 0, 6, 4, 6, MC, "Intel Mobile Celeron 2900U (Mobile H) (Haswell ), 22nm"); FMQ ( 0, 6, 4, 6, MC, "Intel Mobile Celeron 2900U (Mobile H) (Haswell ), 22nm");
FMQ ( 0, 6, 4, 6, dP, "Intel Pentium G3000 (Desktop R) (Haswell), 22n m"); FMQ ( 0, 6, 4, 6, dP, "Intel Pentium G3000 (Desktop R) (Haswell), 22n m");
FM ( 0, 6, 4, 6, "Intel Core i5-4000 / i7-4000 / Mobile Core i3- 4000 / i5-4000 / i7-4000 / Mobile Core i5-4000 / Mobile Core i5-4000 / Mobile Co re i7-4000 / Pentium G3000 / Celeron G1800 / Mobile Pentium 3500U/3600U/3500Y / Mobile Celeron 2900U / Xeon E3-1200 v3 (Desktop R/Mobile H) (Haswell), 22nm"); FM ( 0, 6, 4, 6, "Intel Core i5-4000 / i7-4000 / Mobile Core i3- 4000 / i5-4000 / i7-4000 / Mobile Core i5-4000 / Mobile Core i5-4000 / Mobile Co re i7-4000 / Pentium G3000 / Celeron G1800 / Mobile Pentium 3500U/3600U/3500Y / Mobile Celeron 2900U / Xeon E3-1200 v3 (Desktop R/Mobile H) (Haswell), 22nm");
// So far, all these (0,6),(4,7) processors are stepping G0, but the // So far, all these (0,6),(4,7) processors are stepping G0, but the
// Intel docs (332381, 332382) omit the stepping number for G0. // Intel docs (332381, 332382) omit the stepping number for G0.
FMQ ( 0, 6, 4, 7, dc, "Intel Core i7-5000 (Broadwell), 14nm"); FMQ ( 0, 6, 4, 7, dc, "Intel Core i7-5000 (Broadwell), 14nm");
FMQ ( 0, 6, 4, 7, Mc, "Intel Mobile Core i7-5000 (Broadwell), 14nm"); FMQ ( 0, 6, 4, 7, Mc, "Intel Mobile Core i7-5000 (Broadwell), 14nm");
FMQ ( 0, 6, 4, 7, sX, "Intel Xeon E3-1200 v4 (Broadwell), 14nm"); FMQ ( 0, 6, 4, 7, sX, "Intel Xeon E3-1200 v4 (Broadwell), 14nm");
FM ( 0, 6, 4, 7, "Intel Core i7-5000 / Mobile Core i7-5000 / Xeo n E3-1200 v4 (Broadwell), 14nm"); FM ( 0, 6, 4, 7, "Intel Core i7-5000 / Mobile Core i7-5000 / Xeo n E3-1200 v4 (Broadwell), 14nm");
FM ( 0, 6, 4,10, "Intel Atom Z3400 (Merrifield), 22nm"); // no s pec update; only 325462 Volume 3 Table 35-1 so far FM ( 0, 6, 4,10, "Intel Atom Z3400 (Merrifield) [Silvermont], 22 nm"); // no spec update; only MSR_CPUID_table* so far
// The (0,6),(4,12) processors also have a D1 stepping, but the // The (0,6),(4,12) processors also have a D1 stepping, but the
// Intel docs (332095) omit the stepping number. // Intel docs (332095) omit the stepping number.
FMS ( 0, 6, 4,12, 0, "Intel Pentium N3000 / Celeron N3000 (Braswell FMS ( 0, 6, 4,12, 0, "Intel Pentium N3000 / Celeron N3000 (Braswell
C0), 14nm"); C0) [Airmont], 14nm");
FM ( 0, 6, 4,12, "Intel Pentium N3000 / Celeron N3000 (Braswell) FM ( 0, 6, 4,12, "Intel Pentium N3000 / Celeron N3000 (Braswell)
, 14nm"); [Airmont], 14nm");
FMS ( 0, 6, 4,13, 0, "Intel Atom C2000 (Avoton A0/A1), 22nm"); FMS ( 0, 6, 4,13, 0, "Intel Atom C2000 (Avoton A0/A1) [Silvermont],
FMS ( 0, 6, 4,13, 8, "Intel Atom C2000 (Avoton B0/C0), 22nm"); 22nm");
FM ( 0, 6, 4,13, "Intel Atom C2000 (Avoton), 22nm"); FMS ( 0, 6, 4,13, 8, "Intel Atom C2000 (Avoton B0/C0) [Silvermont],
22nm");
FM ( 0, 6, 4,13, "Intel Atom C2000 (Avoton) [Silvermont], 22nm")
;
// Intel docs (332689) omit the stepping numbers for (0,6),(4,14) D1 & K1. // Intel docs (332689) omit the stepping numbers for (0,6),(4,14) D1 & K1.
FMSQ( 0, 6, 4,14, 12, dc, "Intel Core i*-10000 / Pentium 6000U / Celeron 5000U (Comet Lake V1), 14nm");
FMQ ( 0, 6, 4,14, dc, "Intel Core i3-6000U / i5-6000U / i7-6000U / m3 -6Y00 / m5-6Y00 / m7-6Y00 (Skylake), 14nm"); FMQ ( 0, 6, 4,14, dc, "Intel Core i3-6000U / i5-6000U / i7-6000U / m3 -6Y00 / m5-6Y00 / m7-6Y00 (Skylake), 14nm");
FMQ ( 0, 6, 4,14, dP, "Intel Pentium 4405U / Pentium 4405Y (Skylake), 14nm"); FMQ ( 0, 6, 4,14, dP, "Intel Pentium 4405U / Pentium 4405Y (Skylake), 14nm");
FMQ ( 0, 6, 4,14, dC, "Intel Celeron 3800U / 39000U (Skylake), 14nm") ; FMQ ( 0, 6, 4,14, dC, "Intel Celeron 3800U / 39000U (Skylake), 14nm") ;
FMQ ( 0, 6, 4,14, sX, "Intel Xeon E3-1500m (Skylake), 14nm"); // no s pec update; only 325462 Volume 3 Table 35-1 so far FMQ ( 0, 6, 4,14, sX, "Intel Xeon E3-1500m (Skylake), 14nm"); // no s pec update; only MSR_CPUID_table* so far
FM ( 0, 6, 4,14, "Intel Core i3-6000U / i5-6000U / i7-6000U / m3 -6Y00 / m5-6Y00 / m7-6Y00 / Pentium 4405U / Pentium 4405Y / Celeron 3800U / 3900 0U / Xeon E3-1500m (Skylake), 14nm"); FM ( 0, 6, 4,14, "Intel Core i3-6000U / i5-6000U / i7-6000U / m3 -6Y00 / m5-6Y00 / m7-6Y00 / Pentium 4405U / Pentium 4405Y / Celeron 3800U / 3900 0U / Xeon E3-1500m (Skylake), 14nm");
// Intel docs (334208,333811) omit the stepping numbers for (0,6),(4,15) // Intel docs (334208,333811) omit the stepping numbers for (0,6),(4,15)
// B0, M0 & R0. // B0, M0 & R0.
FMQ ( 0, 6, 4,15, dc, "Intel Core i7-6800K / i7-6900K / i7-6900X (Bro adwell-E), 14nm"); FMQ ( 0, 6, 4,15, dc, "Intel Core i7-6800K / i7-6900K / i7-6900X (Bro adwell-E), 14nm");
FMSQ( 0, 6, 4,15, 1, sX, "Intel Xeon E5-1600 / E5-2600 / E5-4600 v4 (Bro adwell) / E7-4800 / E7-8800 v4 (Broadwell-EX B0), 14nm"); FMSQ( 0, 6, 4,15, 1, sX, "Intel Xeon E5-1600 / E5-2600 / E5-4600 v4 (Bro adwell) / E7-4800 / E7-8800 v4 (Broadwell-EX B0), 14nm");
FMQ ( 0, 6, 4,15, sX, "Intel Xeon E5-1600 / E5-2600 / E5-4600 v4 (Bro adwell) / E7-4800 / E7-8800 v4 (Broadwell-EX), 14nm"); FMQ ( 0, 6, 4,15, sX, "Intel Xeon E5-1600 / E5-2600 / E5-4600 v4 (Bro adwell) / E7-4800 / E7-8800 v4 (Broadwell-EX), 14nm");
FM ( 0, 6, 4,15, "Intel Core i7-6800K / i7-6900K / i7-6900X (Bro adwell-E) / Xeon E5-1600 / E5-2500 / E5-4600 (Broadwell) / E7-4800 / E7-8800 v4 (Broadwell-EX), 14nm"); FM ( 0, 6, 4,15, "Intel Core i7-6800K / i7-6900K / i7-6900X (Bro adwell-E) / Xeon E5-1600 / E5-2500 / E5-4600 (Broadwell) / E7-4800 / E7-8800 v4 (Broadwell-EX), 14nm");
FMSQ( 0, 6, 5, 5, 2, sX, "Intel Xeon W 2000 / Scalable Bronze 3000 / Sil ver 4000 / Gold 5000 / 6000 / Platinum 8000 (Skylake B0/L0), 14nm"); FMSQ( 0, 6, 5, 5, 2, sX, "Intel Xeon W 2000 / Scalable Bronze 3000 / Sil ver 4000 / Gold 5000 / 6000 / Platinum 8000 / D-2100 (Skylake B0/L0), 14nm");
FMSQ( 0, 6, 5, 5, 4, sX, "Intel Xeon W 2000 / Scalable Bronze 3000 / Sil ver 4000 / Gold 5000 / 6000 / Platinum 8000 (Skylake H0/M0/U0), 14nm"); FMSQ( 0, 6, 5, 5, 4, sX, "Intel Xeon W 2000 / Scalable Bronze 3000 / Sil ver 4000 / Gold 5000 / 6000 / Platinum 8000 (Skylake H0/M0/U0), 14nm");
FMSQ( 0, 6, 5, 5, 7, sX, "Intel Xeon W 2000 / Scalable (2nd Gen) Bronze 3000 / Silver 4000 / Gold 5000 / 6000 / Platinum 8000 (Cascade Lake B1/L1/R1), 1 4nm");
// Intel docs (335901) omit almost all details for the Core versions of // Intel docs (335901) omit almost all details for the Core versions of
// (0,6),(5,5). // (0,6),(5,5).
FMQ ( 0, 6, 5, 5, dc, "Intel Core i7-6000X / i7-7000X / i9-7000X (Sky lake-X), 14nm"); FMQ ( 0, 6, 5, 5, dc, "Intel Core i7-6000X / i7-7000X / i9-7000X (Sky lake-X), 14nm");
FMQ ( 0, 6, 5, 5, sX, "Intel Xeon W 2000 / Scalable Bronze 3000 / Sil FMQ ( 0, 6, 5, 5, sX, "Intel Xeon W 2000 / Scalable Bronze 3000 / Sil
ver 4000 / Gold 5000 / 6000 / Platinum 8000 (Skylake), 14nm"); ver 4000 / Gold 5000 / 6000 / Platinum 8000 / D-2100 (Skylake / Cascade Lake), 1
FM ( 0, 6, 5, 5, "Intel Core i7-6000X / i7-7000X / i9-7000X (Sky 4nm");
lake-X) / Xeon W 2000 / Scalable Bronze 3000 / Silver 4000 / Gold 5000 / 6000 / FM ( 0, 6, 5, 5, "Intel Core i7-6000X / i7-7000X / i9-7000X (Sky
Platinum 8000 (Skylake), 14nm"); lake-X) / Xeon W 2000 / Scalable Bronze 3000 / Silver 4000 / Gold 5000 / 6000 /
Platinum 8000 / D-2100 (Skylake / Cascade Lake), 14nm");
FMS ( 0, 6, 5, 6, 1, "Intel Xeon D-1500 (Broadwell-DE U0), 14nm"); FMS ( 0, 6, 5, 6, 1, "Intel Xeon D-1500 (Broadwell-DE U0), 14nm");
FMS ( 0, 6, 5, 6, 2, "Intel Xeon D-1500 (Broadwell-DE V1), 14nm"); FMS ( 0, 6, 5, 6, 2, "Intel Xeon D-1500 (Broadwell-DE V1), 14nm");
FMS ( 0, 6, 5, 6, 3, "Intel Xeon D-1500 (Broadwell-DE V2), 14nm"); FMS ( 0, 6, 5, 6, 3, "Intel Xeon D-1500 (Broadwell-DE V2), 14nm");
FMS ( 0, 6, 5, 6, 4, "Intel Xeon D-1500 (Broadwell-DE Y0), 14nm"); FMS ( 0, 6, 5, 6, 4, "Intel Xeon D-1500 (Broadwell-DE Y0), 14nm");
FMS ( 0, 6, 5, 6, 5, "Intel Xeon D-1500N (Broadwell-DE A1), 14nm"); FMS ( 0, 6, 5, 6, 5, "Intel Xeon D-1500N (Broadwell-DE A1), 14nm");
FM ( 0, 6, 5, 6, "Intel Xeon D-1500 / D-1500N (Broadwell-DE), 14 nm"); FM ( 0, 6, 5, 6, "Intel Xeon D-1500 / D-1500N (Broadwell-DE), 14 nm");
// Intel docs (334646) omit the stepping number for B0. But as of Jan 2017, // Intel docs (334646) omit the stepping number for B0. But as of Jan 2017,
// it is the only stepping, and all examples seen have stepping number 1. // it is the only stepping, and all examples seen have stepping number 1.
FMS ( 0, 6, 5, 7, 1, "Intel Xeon Phi x200 (Knights Landing B0), 14nm "); FMS ( 0, 6, 5, 7, 1, "Intel Xeon Phi x200 (Knights Landing B0), 14nm ");
FM ( 0, 6, 5, 7, "Intel Xeon Phi x200 (Knights Landing), 14nm"); FM ( 0, 6, 5, 7, "Intel Xeon Phi x200 (Knights Landing), 14nm");
FM ( 0, 6, 5,10, "Intel Atom Z3400 (Moorefield), 22nm"); // no s pec update; only 325462 Volume 3 Table 35-1 so far FM ( 0, 6, 5,10, "Intel Atom Z3400 (Moorefield) [Silvermont], 22 nm"); // no spec update; only MSR_CPUID_table* so far
// Intel docs (334820) omit the stepping numbers for B0 & B1. // Intel docs (334820) omit the stepping numbers for B0 & B1.
FMSQ( 0, 6, 5,12, 9, dP, "Intel Pentium N4000 / J4000 (Apollo Lake), 14n FMSQ( 0, 6, 5,12, 9, dP, "Intel Pentium N4000 / J4000 (Apollo Lake) [Gol
m"); dmont], 14nm");
FMSQ( 0, 6, 5,12, 9, dC, "Intel Celeron N3000 / J3000 (Apollo Lake), 14n FMSQ( 0, 6, 5,12, 9, dC, "Intel Celeron N3000 / J3000 (Apollo Lake) [Gol
m"); dmont], 14nm");
FMS ( 0, 6, 5,12, 9, "Intel Pentium N4000 / J4000 / Celeron N3000 / FMS ( 0, 6, 5,12, 9, "Intel Pentium N4000 / J4000 / Celeron N3000 /
J3000 (Apollo Lake), 14nm"); J3000 (Apollo Lake) [Goldmont], 14nm");
FM ( 0, 6, 5,12, "Intel Atom (Goldmont) / Pentium N4000 / J4000 FM ( 0, 6, 5,12, "Intel Atom (Apollo Lake) / Pentium N4000 / J40
/ Celeron N3000 / J3000 (Apollo Lake), 14nm"); // no spec update for Goldmont; o 00 / Celeron N3000 / J3000 (Apollo Lake) [Goldmont], 14nm"); // no spec update f
nly 325462 Volume 3 Table 35-1 so far or Atom; only MSR_CPUID_table* so far
FM ( 0, 6, 5,13, "Intel Atom X3-C3000 (SoFIA), 22nm"); // no spe FM ( 0, 6, 5,13, "Intel Atom X3-C3000 (SoFIA) [Silvermont], 22nm
c update; only 325462 Volume 3 Table 35-1 so far "); // no spec update; only MSR_CPUID_table* so far
// Intel docs (332689,333133) omit the stepping numbers for (0,6),(5,14) // Intel docs (332689,333133) omit the stepping numbers for (0,6),(5,14)
// R0 & S0. // R0 & S0.
FMQ ( 0, 6, 5,14, dc, "Intel Core i3-6000 / i5-6000 / i7-6000 (Skylak e), 14nm"); FMQ ( 0, 6, 5,14, dc, "Intel Core i3-6000 / i5-6000 / i7-6000 (Skylak e), 14nm");
FMQ ( 0, 6, 5,14, dP, "Intel Pentium G4000 (Skylake), 14nm"); FMQ ( 0, 6, 5,14, dP, "Intel Pentium G4000 (Skylake), 14nm");
FMQ ( 0, 6, 5,14, dC, "Intel Celeron G3900 (Skylake), 14nm"); FMQ ( 0, 6, 5,14, dC, "Intel Celeron G3900 (Skylake), 14nm");
FMQ ( 0, 6, 5,14, sX, "Intel Xeon E3-1200 v5 (Skylake), 14nm"); FMQ ( 0, 6, 5,14, sX, "Intel Xeon E3-1200 v5 (Skylake), 14nm");
FM ( 0, 6, 5,14, "Intel Core i3-6000 / i5-6000 / i7-6000 / Penti um G4000 / Celeron G3900 / Xeon E3-1200 (Skylake), 14nm"); FM ( 0, 6, 5,14, "Intel Core i3-6000 / i5-6000 / i7-6000 / Penti um G4000 / Celeron G3900 / Xeon E3-1200 (Skylake), 14nm");
FM ( 0, 6, 5,15, "Intel Atom (Goldmont), 14nm"); // no spec upda FMS ( 0, 6, 5,15, 0, "Intel Atom C3000 (Denverton A0/A1) [Goldmont],
te; only 325462 Volume 3 Table 35-1 so far 14nm");
FMS ( 0, 6, 7,10, 1, "Intel Pentium Silver N5000 / J5000 / Celeron N FMS ( 0, 6, 5,15, 1, "Intel Atom C3000 (Denverton B0/B1) [Goldmont],
4000 / J4000 (Gemini Lake B0), 14nm"); 14nm");
FM ( 0, 6, 7,10, "Intel Pentium Silver N5000 / J5000 / Celeron N FM ( 0, 6, 5,15, "Intel Atom C3000 (Denverton) [Goldmont], 14nm"
4000 / J4000 (Gemini Lake), 14nm"); );
FM ( 0, 6, 8, 5, "Intel Xeon Phi (Knights Mill), 14nm"); // no s FM ( 0, 6, 6, 6, "Intel Core (Cannon Lake), 10nm"); // no spec u
pec update; 325462 Volume 3 Table 35-1 is vague; Piotr Luc said it would be Knig pdate; only MSR_CPUID_table* so far
hts Mill FM ( 0, 6, 6,10, "Intel Core (Ice Lake), 10nm"); // no spec upda
te; only MSR_CPUID_table* so far
FM ( 0, 6, 6,12, "Intel Core (Ice Lake), 10nm"); // no spec upda
te; only MSR_CPUID_table* so far
FMS ( 0, 6, 7,10, 1, "Intel Pentium Silver N5000 / J5000 / Celeron N
4000 / J4000 (Gemini Lake B0/R0) [Goldmont Plus], 14nm");
FM ( 0, 6, 7,10, "Intel Pentium Silver N5000 / J5000 / Celeron N
4000 / J4000 (Gemini Lake) [Goldmont Plus], 14nm");
FM ( 0, 6, 7,13, "Intel Core i*-10000 (Ice Lake), 10nm"); // no
spec update; only MSR_CPUID_table* so far
// Currently there are no Ice Lake CPUs for Xeon/Pentium/Celeron
FMS ( 0, 6, 7,14, 4, "Intel Core i*-10000 (Ice Lake Y), 10nm");
FMS ( 0, 6, 7,14, 5, "Intel Core i*-10000 (Ice Lake U), 10nm");
FM ( 0, 6, 7,14, "Intel Core i*-10000 (Ice Lake), 10nm");
FM ( 0, 6, 8, 5, "Intel Xeon Phi (Knights Mill), 14nm"); // no s
pec update; only MSR_CPUID_table* so far
FM ( 0, 6, 8,12, "Intel Core (Tiger Lake), 10nm"); // found only
on en.wikichip.org
// Intel docs (334663) omit the stepping numbers for (0,6),(8,14) // Intel docs (334663) omit the stepping numbers for (0,6),(8,14)
// H0, J1 & Y0. // H0, J1 & Y0, but (338025) provides some.
FMQ ( 0, 6, 8,14, dc, "Intel m3-7Y00 / i5-7Y00 / i7-7Y00 / i3-7000U / FMSQ( 0, 6, 8,14, 11, dc, "Intel i*-8000U / i*-8000Y (Whiskey Lake / Ambe
i5-7000U / i7-7000U (Kaby Lake), 14nm"); r Lake W0), 14nm");
FMSQ( 0, 6, 8,14, 12, dc, "Intel i*-8000U / i*-8000Y (Whiskey Lake / Ambe
r Lake V0), 14nm");
FMQ ( 0, 6, 8,14, dc, "Intel i*-7000 / i*-8000U / i*-8000Y / m3-7Y00
(Kaby Lake / Whiskey Lake / Amber Lake), 14nm");
FMQ ( 0, 6, 8,14, dP, "Intel Pentium 4410Y / 4415U (Kaby Lake), 14nm" ); FMQ ( 0, 6, 8,14, dP, "Intel Pentium 4410Y / 4415U (Kaby Lake), 14nm" );
FMQ ( 0, 6, 8,14, dC, "Intel Celeron 3965Y / 3865U / 3965U (Kaby Lake ), 14nm"); FMQ ( 0, 6, 8,14, dC, "Intel Celeron 3965Y / 3865U / 3965U (Kaby Lake ), 14nm");
FM ( 0, 6, 8,14, "Intel m3-7Y00 / i5-7Y00 / i7-7Y00 / i3-7000U / FM ( 0, 6, 8,14, "Intel m3-7Y00 / i*-7000 / Pentium 4410Y / 4415
i5-7000U / i7-7000U / Pentium 4410Y / 4415U / Celeron 3965Y / 3865U / 3965U (Ka U / Celeron 3965Y / 3865U / 3965U (Kaby Lake / Whiskey Lake / Amber Lake), 14nm"
by Lake), 14nm"); );
// Intel docs (334663) omit the stepping numbers for (0,6),(9,14) B0. // Intel docs (334663) omit the stepping numbers for (0,6),(9,14) B0,
FMQ ( 0, 6, 9,14, dc, "Intel Core i5-7000 / i5-7000K / i5-7000T / i7- // but (337346) provides some.
7000 / i3-7100H / i5-7000HQ / i7-7000HQ / i7-7000X / i5-7000X / i7-8000 / i5-800 FMSQ( 0, 6, 9,14, 10, dc, "Intel Core i*-8000 S/H Line (Coffee Lake U0) /
0 / i3-8000 (Kaby Lake), 14nm"); Core i*-8000 U Line (Coffee Lake D0), 14nm");
FMQ ( 0, 6, 9,14, dC, "Intel Celeron G3930 (Kaby Lake), 14nm"); FMSQ( 0, 6, 9,14, 11, dc, "Intel Core i*-8000 S Line (Coffee Lake B0), 14
FMQ ( 0, 6, 9,14, sX, "Intel Xeon E3-1200v6 / E3-1285v5 / E3-15x5Mv6 nm");
(Kaby Lake), 14nm"); FMSQ( 0, 6, 9,14, 12, dc, "Intel Core i*-8000 S Line (Coffee Lake P0), 14
FM ( 0, 6, 9,14, "Intel Core i5-7000 / i5-7000K / i5-7000T / i7- nm");
7000 / i3-7100H / i5-7000HQ / i7-7000HQ / i7-7000X / i5-7000X / i7-8000 / i5-800 FMSQ( 0, 6, 9,14, 13, dc, "Intel Core i*-8000 H Line (Coffee Lake R0), 14
0 / i3-8000 / Xeon E3-1200v6 / E3-1285v5 / E3-15x5Mv6 / Celeron G3930 (Kaby Lake nm");
), 14nm"); FMQ ( 0, 6, 9,14, dc, "Intel Core i*-8000 S/H/U/X Line (Coffee Lake),
14nm");
FMQ ( 0, 6, 9,14, dC, "Intel Celeron G3930 (Coffee Lake), 14nm");
FMQ ( 0, 6, 9,14, sX, "Intel Xeon E3-1200v6 / E3-1285v5 / E3-15x5Mv6
/ E-2100 / E-2200 (Coffee Lake), 14nm");
FM ( 0, 6, 9,14, "Intel Core S/H/U/X / Xeon E3-1200v6 / E3-1285v
5 / E3-15x5Mv6 / E-2100 / E-2200 / Celeron G3930 (Coffee Lake), 14nm");
FQ ( 0, 6, sX, "Intel Xeon (unknown model)"); FQ ( 0, 6, sX, "Intel Xeon (unknown model)");
FQ ( 0, 6, se, "Intel Xeon (unknown model)"); FQ ( 0, 6, se, "Intel Xeon (unknown model)");
FQ ( 0, 6, MC, "Intel Mobile Celeron (unknown model)"); FQ ( 0, 6, MC, "Intel Mobile Celeron (unknown model)");
FQ ( 0, 6, dC, "Intel Celeron (unknown model)"); FQ ( 0, 6, dC, "Intel Celeron (unknown model)");
FQ ( 0, 6, Xc, "Intel Core Extreme (unknown model)"); FQ ( 0, 6, Xc, "Intel Core Extreme (unknown model)");
FQ ( 0, 6, Mc, "Intel Mobile Core (unknown model)"); FQ ( 0, 6, Mc, "Intel Mobile Core (unknown model)");
FQ ( 0, 6, dc, "Intel Core (unknown model)"); FQ ( 0, 6, dc, "Intel Core (unknown model)");
FQ ( 0, 6, MP, "Intel Mobile Pentium (unknown model)"); FQ ( 0, 6, MP, "Intel Mobile Pentium (unknown model)");
FQ ( 0, 6, dP, "Intel Pentium (unknown model)"); FQ ( 0, 6, dP, "Intel Pentium (unknown model)");
F ( 0, 6, "Intel Pentium II / Pentium III / Pentium M / C eleron / Celeron M / Core / Core 2 / Core i / Xeon / Atom (unknown model)"); F ( 0, 6, "Intel Pentium II / Pentium III / Pentium M / C eleron / Celeron M / Core / Core 2 / Core i / Xeon / Atom (unknown model)");
FMS ( 0, 7, 0, 6, 4, "Intel Itanium (Merced C0)"); FMS ( 0, 7, 0, 6, 4, "Intel Itanium (Merced C0)");
FMS ( 0, 7, 0, 7, 4, "Intel Itanium (Merced C1)"); FMS ( 0, 7, 0, 7, 4, "Intel Itanium (Merced C1)");
FMS ( 0, 7, 0, 8, 4, "Intel Itanium (Merced C2)"); FMS ( 0, 7, 0, 8, 4, "Intel Itanium (Merced C2)");
F ( 0, 7, "Intel Itanium (unknown model)"); F ( 0, 7, "Intel Itanium (unknown model)");
FM ( 0,11, 0, 0, "Intel Xeon Phi x100 Coprocessor (Knights Ferry ), 45nm"); // found only on en.wikichip.org
FMS ( 0,11, 0, 1, 1, "Intel Xeon Phi x100 Coprocessor (Knights Corne r B0), 22nm"); FMS ( 0,11, 0, 1, 1, "Intel Xeon Phi x100 Coprocessor (Knights Corne r B0), 22nm");
FMS ( 0,11, 0, 1, 3, "Intel Xeon Phi x100 Coprocessor (Knights Corne r B1), 22nm"); FMS ( 0,11, 0, 1, 3, "Intel Xeon Phi x100 Coprocessor (Knights Corne r B1), 22nm");
FMS ( 0,11, 0, 1, 4, "Intel Xeon Phi x100 Coprocessor (Knights Corne r C0), 22nm"); FMS ( 0,11, 0, 1, 4, "Intel Xeon Phi x100 Coprocessor (Knights Corne r C0), 22nm");
FM ( 0,11, 0, 1, "Intel Xeon Phi x100 Coprocessor (Knights Corne r), 22nm"); FM ( 0,11, 0, 1, "Intel Xeon Phi x100 Coprocessor (Knights Corne r), 22nm");
FMS ( 0,15, 0, 0, 7, "Intel Pentium 4 (Willamette B2), .18um"); FMS ( 0,15, 0, 0, 7, "Intel Pentium 4 (Willamette B2) [Willamette],
FMSQ( 0,15, 0, 0, 10, dP, "Intel Pentium 4 (Willamette C1), .18um"); .18um");
FMSQ( 0,15, 0, 0, 10, sX, "Intel Xeon (Foster C1), .18um"); FMSQ( 0,15, 0, 0, 10, dP, "Intel Pentium 4 (Willamette C1) [Willamette],
FMS ( 0,15, 0, 0, 10, "Intel Pentium 4 (Willamette C1) / Xeon (Foster .18um");
C1), .18um"); FMSQ( 0,15, 0, 0, 10, sX, "Intel Xeon (Foster C1) [Willamette], .18um");
FMQ ( 0,15, 0, 0, dP, "Intel Pentium 4 (Willamette), .18um"); FMS ( 0,15, 0, 0, 10, "Intel Pentium 4 (Willamette C1) / Xeon (Foster
FMQ ( 0,15, 0, 0, sX, "Intel Xeon (Foster), .18um"); C1) [Willamette], .18um");
FM ( 0,15, 0, 0, "Intel Pentium 4 (Willamette) / Xeon (Foster), FMQ ( 0,15, 0, 0, dP, "Intel Pentium 4 (Willamette) [Willamette], .18
.18um"); um");
FMS ( 0,15, 0, 1, 1, "Intel Xeon MP (Foster C0), .18um"); FMQ ( 0,15, 0, 0, sX, "Intel Xeon (Foster) [Willamette], .18um");
FMSQ( 0,15, 0, 1, 2, dP, "Intel Pentium 4 (Willamette D0), .18um"); FM ( 0,15, 0, 0, "Intel Pentium 4 (Willamette) / Xeon (Foster) [
FMSQ( 0,15, 0, 1, 2, sX, "Intel Xeon (Foster D0), .18um"); Willamette], .18um");
FMS ( 0,15, 0, 1, 2, "Intel Pentium 4 (Willamette D0) / Xeon (Foster FMS ( 0,15, 0, 1, 1, "Intel Xeon MP (Foster C0) [Willamette], .18um"
D0), .18um"); );
FMSQ( 0,15, 0, 1, 3, dP, "Intel Pentium 4(Willamette E0), .18um"); FMSQ( 0,15, 0, 1, 2, dP, "Intel Pentium 4 (Willamette D0) [Willamette],
FMSQ( 0,15, 0, 1, 3, dC, "Intel Celeron 478-pin (Willamette E0), .18um") .18um");
; FMSQ( 0,15, 0, 1, 2, sX, "Intel Xeon (Foster D0) [Willamette], .18um");
FMS ( 0,15, 0, 1, 3, "Intel Pentium 4 / Celeron (Willamette E0), .18 FMS ( 0,15, 0, 1, 2, "Intel Pentium 4 (Willamette D0) / Xeon (Foster
um"); D0) [Willamette], .18um");
FMQ ( 0,15, 0, 1, dP, "Intel Pentium 4 (Willamette), .18um"); FMSQ( 0,15, 0, 1, 3, dP, "Intel Pentium 4(Willamette E0) [Willamette], .
FMQ ( 0,15, 0, 1, sX, "Intel Xeon (Foster), .18um"); 18um");
FM ( 0,15, 0, 1, "Intel Pentium 4 (Willamette) / Xeon (Foster), FMSQ( 0,15, 0, 1, 3, dC, "Intel Celeron 478-pin (Willamette E0) [Willame
.18um"); tte], .18um");
FMS ( 0,15, 0, 2, 2, "Intel Xeon MP (Gallatin A0), .13um"); FMS ( 0,15, 0, 1, 3, "Intel Pentium 4 / Celeron (Willamette E0) [Wil
FMSQ( 0,15, 0, 2, 4, sX, "Intel Xeon (Prestonia B0), .13um"); lamette], .18um");
FMSQ( 0,15, 0, 2, 4, MM, "Intel Mobile Pentium 4 Processor-M (Northwood FMQ ( 0,15, 0, 1, dP, "Intel Pentium 4 (Willamette) [Willamette], .18
B0), .13um"); um");
FMSQ( 0,15, 0, 2, 4, MC, "Intel Mobile Celeron (Northwood B0), .13um"); FMQ ( 0,15, 0, 1, sX, "Intel Xeon (Foster) [Willamette], .18um");
FMSQ( 0,15, 0, 2, 4, dP, "Intel Pentium 4 (Northwood B0), .13um"); FM ( 0,15, 0, 1, "Intel Pentium 4 (Willamette) / Xeon (Foster) [
FMS ( 0,15, 0, 2, 4, "Intel Pentium 4 (Northwood B0) / Xeon (Preston Willamette], .18um");
ia B0) / Mobile Pentium 4 Processor-M (Northwood B0) / Mobile Celeron (Northwood FMS ( 0,15, 0, 2, 2, "Intel Xeon MP (Gallatin A0) [Northwood], .13um
B0), .13um"); ");
FMSQ( 0,15, 0, 2, 5, dP, "Intel Pentium 4 (Northwood B1/M0), .13um"); FMSQ( 0,15, 0, 2, 4, sX, "Intel Xeon (Prestonia B0) [Northwood], .13um")
FMSQ( 0,15, 0, 2, 5, sM, "Intel Xeon MP (Gallatin B1), .13um"); ;
FMSQ( 0,15, 0, 2, 5, sX, "Intel Xeon (Prestonia B1), .13um"); FMSQ( 0,15, 0, 2, 4, MM, "Intel Mobile Pentium 4 Processor-M (Northwood
FMS ( 0,15, 0, 2, 5, "Intel Pentium 4 (Northwood B1/M0) / Xeon (Pres B0) [Northwood], .13um");
tonia B1) / Xeon MP (Gallatin B1), .13um"); FMSQ( 0,15, 0, 2, 4, MC, "Intel Mobile Celeron (Northwood B0) [Northwood
FMS ( 0,15, 0, 2, 6, "Intel Xeon MP (Gallatin C0), .13um"); ], .13um");
FMSQ( 0,15, 0, 2, 7, sX, "Intel Xeon (Prestonia C1), .13um"); FMSQ( 0,15, 0, 2, 4, dP, "Intel Pentium 4 (Northwood B0) [Northwood], .1
FMSQ( 0,15, 0, 2, 7, dC, "Intel Celeron 478-pin (Northwood C1), .13um"); 3um");
FMSQ( 0,15, 0, 2, 7, MC, "Intel Mobile Celeron (Northwood C1), .13um"); FMS ( 0,15, 0, 2, 4, "Intel Pentium 4 (Northwood B0) / Xeon (Preston
FMSQ( 0,15, 0, 2, 7, MM, "Intel Mobile Pentium 4 Processor-M (Northwood ia B0) / Mobile Pentium 4 Processor-M (Northwood B0) / Mobile Celeron (Northwood
C1), .13um"); B0) [Northwood], .13um");
FMSQ( 0,15, 0, 2, 7, dP, "Intel Pentium 4 (Northwood C1), .13um"); FMSQ( 0,15, 0, 2, 5, dP, "Intel Pentium 4 (Northwood B1/M0) [Northwood],
FMS ( 0,15, 0, 2, 7, "Intel Pentium 4 (Northwood C1) / Xeon (Preston .13um");
ia C1) / Mobile Pentium 4 Processor-M (Northwood C1) / Celeron 478-Pin (Northwoo FMSQ( 0,15, 0, 2, 5, sM, "Intel Xeon MP (Gallatin B1) [Northwood], .13um
d C1) / Mobile Celeron (Northwood C1), .13um"); ");
FMSQ( 0,15, 0, 2, 9, sX, "Intel Xeon (Prestonia D1), .13um"); FMSQ( 0,15, 0, 2, 5, sX, "Intel Xeon (Prestonia B1) [Northwood], .13um")
FMSQ( 0,15, 0, 2, 9, dC, "Intel Celeron 478-pin (Northwood D1), .13um"); ;
FMSQ( 0,15, 0, 2, 9, MC, "Intel Mobile Celeron (Northwood D1), .13um"); FMS ( 0,15, 0, 2, 5, "Intel Pentium 4 (Northwood B1/M0) / Xeon (Pres
FMSQ( 0,15, 0, 2, 9, MM, "Intel Mobile Pentium 4 Processor-M (Northwood tonia B1) / Xeon MP (Gallatin B1) [Northwood], .13um");
D1), .13um"); FMS ( 0,15, 0, 2, 6, "Intel Xeon MP (Gallatin C0) [Northwood], .13um
FMSQ( 0,15, 0, 2, 9, MP, "Intel Mobile Pentium 4 (Northwood D1), .13um") ");
; FMSQ( 0,15, 0, 2, 7, sX, "Intel Xeon (Prestonia C1) [Northwood], .13um")
FMSQ( 0,15, 0, 2, 9, dP, "Intel Pentium 4 (Northwood D1), .13um"); ;
FMS ( 0,15, 0, 2, 9, "Intel Pentium 4 (Northwood D1) / Xeon (Preston FMSQ( 0,15, 0, 2, 7, dC, "Intel Celeron 478-pin (Northwood C1) [Northwoo
ia D1) / Mobile Pentium 4 (Northwood D1) / Mobile Pentium 4 Processor-M (Northwo d], .13um");
od D1) / Celeron 478-pin (Northwood D1), .13um"); FMSQ( 0,15, 0, 2, 7, MC, "Intel Mobile Celeron (Northwood C1) [Northwood
FMQ ( 0,15, 0, 2, dP, "Intel Pentium 4 (Northwood), .13um"); ], .13um");
FMQ ( 0,15, 0, 2, sM, "Intel Xeon MP (Gallatin), .13um"); FMSQ( 0,15, 0, 2, 7, MM, "Intel Mobile Pentium 4 Processor-M (Northwood
FMQ ( 0,15, 0, 2, sX, "Intel Xeon (Prestonia), .13um"); C1) [Northwood], .13um");
FM ( 0,15, 0, 2, "Intel Pentium 4 (Northwood) / Xeon (Prestonia) FMSQ( 0,15, 0, 2, 7, dP, "Intel Pentium 4 (Northwood C1) [Northwood], .1
/ Xeon MP (Gallatin) / Mobile Pentium 4 / Mobile Pentium 4 Processor-M (Northwo 3um");
od) / Celeron 478-pin (Northwood), .13um"); FMS ( 0,15, 0, 2, 7, "Intel Pentium 4 (Northwood C1) / Xeon (Preston
FMSQ( 0,15, 0, 3, 3, dP, "Intel Pentium 4 (Prescott C0), 90nm"); ia C1) / Mobile Pentium 4 Processor-M (Northwood C1) / Celeron 478-Pin (Northwoo
FMSQ( 0,15, 0, 3, 3, dC, "Intel Celeron D (Prescott C0), 90nm"); d C1) / Mobile Celeron (Northwood C1) [Northwood], .13um");
FMS ( 0,15, 0, 3, 3, "Intel Pentium 4 (Prescott C0) / Celeron D (Pre FMSQ( 0,15, 0, 2, 9, sX, "Intel Xeon (Prestonia D1) [Northwood], .13um")
scott C0), 90nm"); ;
FMSQ( 0,15, 0, 3, 4, sX, "Intel Xeon (Nocona D0), 90nm"); FMSQ( 0,15, 0, 2, 9, dC, "Intel Celeron 478-pin (Northwood D1) [Northwoo
FMSQ( 0,15, 0, 3, 4, dC, "Intel Celeron D (Prescott D0), 90nm"); d], .13um");
FMSQ( 0,15, 0, 3, 4, MP, "Intel Mobile Pentium 4 (Prescott D0), 90nm"); FMSQ( 0,15, 0, 2, 9, MC, "Intel Mobile Celeron (Northwood D1) [Northwood
FMSQ( 0,15, 0, 3, 4, dP, "Intel Pentium 4 (Prescott D0), 90nm"); ], .13um");
FMS ( 0,15, 0, 3, 4, "Intel Pentium 4 (Prescott D0) / Xeon (Nocona D FMSQ( 0,15, 0, 2, 9, MM, "Intel Mobile Pentium 4 Processor-M (Northwood
0) / Mobile Pentium 4 (Prescott D0), 90nm"); D1) [Northwood], .13um");
FMQ ( 0,15, 0, 3, sX, "Intel Xeon (Nocona), 90nm"); FMSQ( 0,15, 0, 2, 9, MP, "Intel Mobile Pentium 4 (Northwood D1) [Northwo
FMQ( 0,15, 0, 3, dC, "Intel Celeron D (Prescott), 90nm"); od], .13um");
FMQ ( 0,15, 0, 3, MP, "Intel Mobile Pentium 4 (Prescott), 90nm"); FMSQ( 0,15, 0, 2, 9, dP, "Intel Pentium 4 (Northwood D1) [Northwood], .1
FMQ ( 0,15, 0, 3, dP, "Intel Pentium 4 (Prescott), 90nm"); 3um");
FM ( 0,15, 0, 3, "Intel Pentium 4 (Prescott) / Xeon (Nocona) / M FMS ( 0,15, 0, 2, 9, "Intel Pentium 4 (Northwood D1) / Xeon (Preston
obile Pentium 4 (Prescott), 90nm"); ia D1) / Mobile Pentium 4 (Northwood D1) / Mobile Pentium 4 Processor-M (Northwo
FMSQ( 0,15, 0, 4, 1, sP, "Intel Xeon MP (Potomac C0), 90nm"); od D1) / Celeron 478-pin (Northwood D1) [Northwood], .13um");
FMSQ( 0,15, 0, 4, 1, sM, "Intel Xeon MP (Cranford A0), 90nm"); FMQ ( 0,15, 0, 2, dP, "Intel Pentium 4 (Northwood) [Northwood], .13um
FMSQ( 0,15, 0, 4, 1, sX, "Intel Xeon (Nocona E0), 90nm"); ");
FMSQ( 0,15, 0, 4, 1, dC, "Intel Celeron D (Prescott E0), 90nm"); FMQ ( 0,15, 0, 2, sM, "Intel Xeon MP (Gallatin) [Northwood], .13um");
FMSQ( 0,15, 0, 4, 1, MP, "Intel Mobile Pentium 4 (Prescott E0), 90nm"); FMQ ( 0,15, 0, 2, sX, "Intel Xeon (Prestonia) [Northwood], .13um");
FMSQ( 0,15, 0, 4, 1, dP, "Intel Pentium 4 (Prescott E0), 90nm"); FM ( 0,15, 0, 2, "Intel Pentium 4 (Northwood) / Xeon (Prestonia)
FMS ( 0,15, 0, 4, 1, "Intel Pentium 4 (Prescott E0) / Xeon (Nocona E / Xeon MP (Gallatin) / Mobile Pentium 4 / Mobile Pentium 4 Processor-M (Northwo
0) / Xeon MP (Cranford A0 / Potomac C0) / Celeron D (Prescott E0 ) / Mobile Pent od) / Celeron 478-pin (Northwood) [Northwood], .13um");
ium 4 (Prescott E0), 90nm"); FMSQ( 0,15, 0, 3, 3, dP, "Intel Pentium 4 (Prescott C0) [Prescott], 90nm
FMSQ( 0,15, 0, 4, 3, sI, "Intel Xeon (Irwindale N0), 90nm"); ");
FMSQ( 0,15, 0, 4, 3, sX, "Intel Xeon (Nocona N0), 90nm"); FMSQ( 0,15, 0, 3, 3, dC, "Intel Celeron D (Prescott C0) [Prescott], 90nm
FMSQ( 0,15, 0, 4, 3, dP, "Intel Pentium 4 (Prescott N0), 90nm"); ");
FMS ( 0,15, 0, 4, 3, "Intel Pentium 4 (Prescott N0) / Xeon (Nocona N FMS ( 0,15, 0, 3, 3, "Intel Pentium 4 (Prescott C0) / Celeron D (Pre
0 / Irwindale N0), 90nm"); scott C0) [Prescott], 90nm");
FMSQ( 0,15, 0, 4, 4, dc, "Intel Pentium Extreme Edition Processor 840 (S FMSQ( 0,15, 0, 3, 4, sX, "Intel Xeon (Nocona D0) [Prescott], 90nm");
mithfield A0), 90nm"); FMSQ( 0,15, 0, 3, 4, dC, "Intel Celeron D (Prescott D0) [Prescott], 90nm
FMSQ( 0,15, 0, 4, 4, dd, "Intel Pentium D Processor 8x0 (Smithfield A0), ");
90nm"); FMSQ( 0,15, 0, 3, 4, MP, "Intel Mobile Pentium 4 (Prescott D0) [Prescott
FMS ( 0,15, 0, 4, 4, "Intel Pentium D Processor 8x0 (Smithfield A0) ], 90nm");
/ Pentium Extreme Edition Processor 840 (Smithfield A0), 90nm"); FMSQ( 0,15, 0, 3, 4, dP, "Intel Pentium 4 (Prescott D0) [Prescott], 90nm
FMSQ( 0,15, 0, 4, 7, dc, "Pentium Extreme Edition Processor 840 (Smithfi ");
eld B0), 90nm"); FMS ( 0,15, 0, 3, 4, "Intel Pentium 4 (Prescott D0) / Xeon (Nocona D
FMSQ( 0,15, 0, 4, 7, dd, "Intel Pentium D Processor 8x0 (Smithfield B0), 0) / Mobile Pentium 4 (Prescott D0) [Prescott], 90nm");
90nm"); FMQ ( 0,15, 0, 3, sX, "Intel Xeon (Nocona) [Prescott], 90nm");
FMS ( 0,15, 0, 4, 7, "Intel Pentium D Processor 8x0 (Smithfield B0) FMQ( 0,15, 0, 3, dC, "Intel Celeron D (Prescott) [Prescott], 90nm");
/ Pentium Extreme Edition Processor 840 (Smithfield B0), 90nm"); FMQ ( 0,15, 0, 3, MP, "Intel Mobile Pentium 4 (Prescott) [Prescott],
FMSQ( 0,15, 0, 4, 8, s7, "Intel Dual-Core Xeon Processor 7000 (Paxville 90nm");
A0), 90nm"); FMQ ( 0,15, 0, 3, dP, "Intel Pentium 4 (Prescott) [Prescott], 90nm");
FMSQ( 0,15, 0, 4, 8, sX, "Intel Dual-Core Xeon (Paxville A0), 90nm"); FM ( 0,15, 0, 3, "Intel Pentium 4 (Prescott) / Xeon (Nocona) / M
FMS ( 0,15, 0, 4, 8, "Intel Dual-Core Xeon (Paxville A0) / Dual-Core obile Pentium 4 (Prescott) [Prescott], 90nm");
Xeon Processor 7000 (Paxville A0), 90nm"); FMSQ( 0,15, 0, 4, 1, sP, "Intel Xeon MP (Potomac C0) [Prescott], 90nm");
FMSQ( 0,15, 0, 4, 9, sM, "Intel Xeon MP (Cranford B0), 90nm"); FMSQ( 0,15, 0, 4, 1, sM, "Intel Xeon MP (Cranford A0) [Prescott], 90nm")
FMSQ( 0,15, 0, 4, 9, dC, "Intel Celeron D (Prescott G1), 90nm"); ;
FMSQ( 0,15, 0, 4, 9, dP, "Intel Pentium 4 (Prescott G1), 90nm"); FMSQ( 0,15, 0, 4, 1, sX, "Intel Xeon (Nocona E0) [Prescott], 90nm");
FMS ( 0,15, 0, 4, 9, "Intel Pentium 4 (Prescott G1) / Xeon MP (Cranf FMSQ( 0,15, 0, 4, 1, dC, "Intel Celeron D (Prescott E0) [Prescott], 90nm
ord B0) / Celeron D (Prescott G1), 90nm"); ");
FMSQ( 0,15, 0, 4, 10, sI, "Intel Xeon (Irwindale R0), 90nm"); FMSQ( 0,15, 0, 4, 1, MP, "Intel Mobile Pentium 4 (Prescott E0) [Prescott
FMSQ( 0,15, 0, 4, 10, sX, "Intel Xeon (Nocona R0), 90nm"); ], 90nm");
FMSQ( 0,15, 0, 4, 10, dP, "Intel Pentium 4 (Prescott R0), 90nm"); FMSQ( 0,15, 0, 4, 1, dP, "Intel Pentium 4 (Prescott E0) [Prescott], 90nm
FMS ( 0,15, 0, 4, 10, "Intel Pentium 4 (Prescott R0) / Xeon (Nocona R ");
0 / Irwindale R0), 90nm"); FMS ( 0,15, 0, 4, 1, "Intel Pentium 4 (Prescott E0) / Xeon (Nocona E
FMQ ( 0,15, 0, 4, sM, "Intel Xeon MP (Nocona/Potomac), 90nm"); 0) / Xeon MP (Cranford A0 / Potomac C0) / Celeron D (Prescott E0 ) / Mobile Pent
FMQ ( 0,15, 0, 4, sX, "Intel Xeon (Nocona/Irwindale), 90nm"); ium 4 (Prescott E0) [Prescott], 90nm");
FMQ ( 0,15, 0, 4, dC, "Intel Celeron D (Prescott), 90nm"); FMSQ( 0,15, 0, 4, 3, sI, "Intel Xeon (Irwindale N0) [Prescott], 90nm");
FMQ ( 0,15, 0, 4, MP, "Intel Mobile Pentium 4 (Prescott), 90nm"); FMSQ( 0,15, 0, 4, 3, sX, "Intel Xeon (Nocona N0) [Prescott], 90nm");
FMQ ( 0,15, 0, 4, dd, "Intel Pentium D (Smithfield A0), 90nm"); FMSQ( 0,15, 0, 4, 3, dP, "Intel Pentium 4 (Prescott N0) [Prescott], 90nm
FMQ ( 0,15, 0, 4, dP, "Intel Pentium 4 (Prescott) / Pentium Extreme E ");
dition (Smithfield A0), 90nm"); FMS ( 0,15, 0, 4, 3, "Intel Pentium 4 (Prescott N0) / Xeon (Nocona N
FM ( 0,15, 0, 4, "Intel Pentium 4 (Prescott) / Xeon (Nocona / Ir 0 / Irwindale N0) [Prescott], 90nm");
windale) / Pentium D (Smithfield A0) / Pentium Extreme Edition (Smithfield A0) / FMSQ( 0,15, 0, 4, 4, dc, "Intel Pentium Extreme Edition Processor 840 (S
Mobile Pentium 4 (Prescott) / Xeon MP (Nocona) / Xeon MP (Cranford / Potomac) / mithfield A0) [Prescott], 90nm");
Celeron D (Prescott) / Dual-Core Xeon (Paxville A0) / Dual-Core Xeon Processor FMSQ( 0,15, 0, 4, 4, dd, "Intel Pentium D Processor 8x0 (Smithfield A0)
7000 (Paxville A0), 90nm"); [Prescott], 90nm");
FMSQ( 0,15, 0, 6, 2, dd, "Intel Pentium D Processor 9xx (Presler B1), 65 FMS ( 0,15, 0, 4, 4, "Intel Pentium D Processor 8x0 (Smithfield A0)
nm"); / Pentium Extreme Edition Processor 840 (Smithfield A0) [Prescott], 90nm");
FMSQ( 0,15, 0, 4, 7, dc, "Pentium Extreme Edition Processor 840 (Smithfi
eld B0) [Prescott], 90nm");
FMSQ( 0,15, 0, 4, 7, dd, "Intel Pentium D Processor 8x0 (Smithfield B0)
[Prescott], 90nm");
FMS ( 0,15, 0, 4, 7, "Intel Pentium D Processor 8x0 (Smithfield B0)
/ Pentium Extreme Edition Processor 840 (Smithfield B0) [Prescott], 90nm");
FMSQ( 0,15, 0, 4, 8, s7, "Intel Dual-Core Xeon Processor 7000 (Paxville
A0) [Prescott], 90nm");
FMSQ( 0,15, 0, 4, 8, sX, "Intel Dual-Core Xeon (Paxville A0) [Prescott],
90nm");
FMS ( 0,15, 0, 4, 8, "Intel Dual-Core Xeon (Paxville A0) / Dual-Core
Xeon Processor 7000 (Paxville A0) [Prescott], 90nm");
FMSQ( 0,15, 0, 4, 9, sM, "Intel Xeon MP (Cranford B0) [Prescott], 90nm")
;
FMSQ( 0,15, 0, 4, 9, dC, "Intel Celeron D (Prescott G1) [Prescott], 90nm
");
FMSQ( 0,15, 0, 4, 9, dP, "Intel Pentium 4 (Prescott G1) [Prescott], 90nm
");
FMS ( 0,15, 0, 4, 9, "Intel Pentium 4 (Prescott G1) / Xeon MP (Cranf
ord B0) / Celeron D (Prescott G1) [Prescott], 90nm");
FMSQ( 0,15, 0, 4, 10, sI, "Intel Xeon (Irwindale R0) [Prescott], 90nm");
FMSQ( 0,15, 0, 4, 10, sX, "Intel Xeon (Nocona R0) [Prescott], 90nm");
FMSQ( 0,15, 0, 4, 10, dP, "Intel Pentium 4 (Prescott R0) [Prescott], 90nm
");
FMS ( 0,15, 0, 4, 10, "Intel Pentium 4 (Prescott R0) / Xeon (Nocona R
0 / Irwindale R0) [Prescott], 90nm");
FMQ ( 0,15, 0, 4, sM, "Intel Xeon MP (Nocona/Potomac) [Prescott], 90n
m");
FMQ ( 0,15, 0, 4, sX, "Intel Xeon (Nocona/Irwindale) [Prescott], 90nm
");
FMQ ( 0,15, 0, 4, dC, "Intel Celeron D (Prescott) [Prescott], 90nm");
FMQ ( 0,15, 0, 4, MP, "Intel Mobile Pentium 4 (Prescott) [Prescott],
90nm");
FMQ ( 0,15, 0, 4, dd, "Intel Pentium D (Smithfield A0) [Prescott], 90
nm");
FMQ ( 0,15, 0, 4, dP, "Intel Pentium 4 (Prescott) / Pentium Extreme E
dition (Smithfield A0) [Prescott], 90nm");
FM ( 0,15, 0, 4, "Intel Pentium 4 (Prescott) / Xeon (Nocona / Ir
windale) / Pentium D (Smithfield A0) / Pentium Extreme Edition (Smithfield A0) /
Mobile Pentium 4 (Prescott) / Xeon MP (Nocona) / Xeon MP (Cranford / Potomac) /
Celeron D (Prescott) / Dual-Core Xeon (Paxville A0) / Dual-Core Xeon Processor
7000 (Paxville A0) [Prescott], 90nm");
FMSQ( 0,15, 0, 6, 2, dd, "Intel Pentium D Processor 9xx (Presler B1) [Ce
dar Mill], 65nm");
FMSQ( 0,15, 0, 6, 2, dP, "Intel Pentium 4 Processor 6x1 (Cedar Mill B1) / Pentium Extreme Edition Processor 955 (Presler B1)"); FMSQ( 0,15, 0, 6, 2, dP, "Intel Pentium 4 Processor 6x1 (Cedar Mill B1) / Pentium Extreme Edition Processor 955 (Presler B1)");
FMS ( 0,15, 0, 6, 2, "Intel Pentium 4 Processor 6x1 (Cedar Mill B1) FMS ( 0,15, 0, 6, 2, "Intel Pentium 4 Processor 6x1 (Cedar Mill B1)
/ Pentium Extreme Edition Processor 955 (Presler B1) / Pentium D Processor 900 ( / Pentium Extreme Edition Processor 955 (Presler B1) / Pentium D Processor 900 (
Presler B1), 65nm"); Presler B1) [Cedar Mill], 65nm");
FMSQ( 0,15, 0, 6, 4, dd, "Intel Pentium D Processor 9xx (Presler C1), 65 FMSQ( 0,15, 0, 6, 4, dd, "Intel Pentium D Processor 9xx (Presler C1) [Ce
nm"); dar Mill], 65nm");
FMSQ( 0,15, 0, 6, 4, dP, "Intel Pentium 4 Processor 6x1 (Cedar Mill C1) / Pentium Extreme Edition Processor 955 (Presler C1)"); FMSQ( 0,15, 0, 6, 4, dP, "Intel Pentium 4 Processor 6x1 (Cedar Mill C1) / Pentium Extreme Edition Processor 955 (Presler C1)");
FMSQ( 0,15, 0, 6, 4, dC, "Intel Celeron D Processor 34x/35x (Cedar Mill FMSQ( 0,15, 0, 6, 4, dC, "Intel Celeron D Processor 34x/35x (Cedar Mill
C1), 65nm"); C1) [Cedar Mill], 65nm");
FMSQ( 0,15, 0, 6, 4, sX, "Intel Xeon Processor 5000 (Dempsey C1), 65nm") FMSQ( 0,15, 0, 6, 4, sX, "Intel Xeon Processor 5000 (Dempsey C1) [Cedar
; Mill], 65nm");
FMS ( 0,15, 0, 6, 4, "Intel Pentium 4 Processor 6x1 (Cedar Mill C1) FMS ( 0,15, 0, 6, 4, "Intel Pentium 4 Processor 6x1 (Cedar Mill C1)
/ Pentium Extreme Edition Processor 955 (Presler C1) / Pentium D Processor 9xx ( / Pentium Extreme Edition Processor 955 (Presler C1) / Pentium D Processor 9xx (
Presler C1) / Xeon Processor 5000 (Dempsey C1) / Celeron D Processor 3xx (Cedar Presler C1) / Xeon Processor 5000 (Dempsey C1) / Celeron D Processor 3xx (Cedar
Mill C1), 65nm"); Mill C1) [Cedar Mill], 65nm");
FMSQ( 0,15, 0, 6, 5, dC, "Intel Celeron D Processor 36x (Cedar Mill D0), FMSQ( 0,15, 0, 6, 5, dC, "Intel Celeron D Processor 36x (Cedar Mill D0)
65nm"); [Cedar Mill], 65nm");
FMSQ( 0,15, 0, 6, 5, dd, "Intel Pentium D Processor 9xx (Presler D0), 65 FMSQ( 0,15, 0, 6, 5, dd, "Intel Pentium D Processor 9xx (Presler D0) [Ce
nm"); dar Mill], 65nm");
FMSQ( 0,15, 0, 6, 5, dP, "Intel Pentium 4 Processor 6x1 (Cedar Mill D0) FMSQ( 0,15, 0, 6, 5, dP, "Intel Pentium 4 Processor 6x1 (Cedar Mill D0)
/ Pentium Extreme Edition Processor 955 (Presler D0), 65nm"); / Pentium Extreme Edition Processor 955 (Presler D0) [Cedar Mill], 65nm");
FMS ( 0,15, 0, 6, 5, "Intel Pentium 4 Processor 6x1 (Cedar Mill D0) FMS ( 0,15, 0, 6, 5, "Intel Pentium 4 Processor 6x1 (Cedar Mill D0)
/ Pentium D Processor 9xx (Presler D0) / Pentium Extreme Edition Processor 955 ( / Pentium D Processor 9xx (Presler D0) / Pentium Extreme Edition Processor 955 (
Presler D0) / Celeron D Processor 36x (Cedar Mill D0), 65nm"); Presler D0) / Celeron D Processor 36x (Cedar Mill D0) [Cedar Mill], 65nm");
FMS ( 0,15, 0, 6, 8, "Intel Xeon Processor 71x0 (Tulsa B0), 65nm"); FMS ( 0,15, 0, 6, 8, "Intel Xeon Processor 71x0 (Tulsa B0) [Cedar Mi
FMQ ( 0,15, 0, 6, dd, "Intel Pentium D (Presler), 65nm"); ll], 65nm");
FMQ ( 0,15, 0, 6, dd, "Intel Pentium D (Presler) [Cedar Mill], 65nm")
;
FMQ ( 0,15, 0, 6, dP, "Intel Pentium 4 (Cedar Mill) / Pentium Extreme Edition (Presler)"); FMQ ( 0,15, 0, 6, dP, "Intel Pentium 4 (Cedar Mill) / Pentium Extreme Edition (Presler)");
FMQ ( 0,15, 0, 6, dC, "Intel Celeron D (Cedar Mill), 65nm"); FMQ ( 0,15, 0, 6, dC, "Intel Celeron D (Cedar Mill) [Cedar Mill], 65n
FMQ ( 0,15, 0, 6, sX, "Intel Xeon (Dempsey / Tulsa), 65nm"); m");
FM ( 0,15, 0, 6, "Intel Pentium 4 (Cedar Mill) / Pentium Extreme FMQ ( 0,15, 0, 6, sX, "Intel Xeon (Dempsey / Tulsa) [Cedar Mill], 65n
Edition (Presler) / Pentium D (Presler) / Xeon (Dempsey) / Xeon (Tulsa) / Celer m");
on D (Cedar Mill), 65nm"); FM ( 0,15, 0, 6, "Intel Pentium 4 (Cedar Mill) / Pentium Extreme
Edition (Presler) / Pentium D (Presler) / Xeon (Dempsey) / Xeon (Tulsa) / Celer
on D (Cedar Mill) [Cedar Mill], 65nm");
FQ ( 0,15, sM, "Intel Xeon MP (unknown model)"); FQ ( 0,15, sM, "Intel Xeon MP (unknown model)");
FQ ( 0,15, sX, "Intel Xeon (unknown model)"); FQ ( 0,15, sX, "Intel Xeon (unknown model)");
FQ ( 0,15, MC, "Intel Mobile Celeron (unknown model)"); FQ ( 0,15, MC, "Intel Mobile Celeron (unknown model)");
FQ ( 0,15, MC, "Intel Mobile Pentium 4 (unknown model)"); FQ ( 0,15, MC, "Intel Mobile Pentium 4 (unknown model)");
FQ ( 0,15, MM, "Intel Mobile Pentium 4 Processor-M (unknown mo del)"); FQ ( 0,15, MM, "Intel Mobile Pentium 4 Processor-M (unknown mo del)");
FQ ( 0,15, dC, "Intel Celeron (unknown model)"); FQ ( 0,15, dC, "Intel Celeron (unknown model)");
FQ ( 0,15, dd, "Intel Pentium D (unknown model)"); FQ ( 0,15, dd, "Intel Pentium D (unknown model)");
FQ ( 0,15, dP, "Intel Pentium 4 (unknown model)"); FQ ( 0,15, dP, "Intel Pentium 4 (unknown model)");
FQ ( 0,15, dc, "Intel Pentium (unknown model)"); FQ ( 0,15, dc, "Intel Pentium (unknown model)");
F ( 0,15, "Intel Pentium 4 / Pentium D / Xeon / Xeon MP / Celeron / Celeron D (unknown model)"); F ( 0,15, "Intel Pentium 4 / Pentium D / Xeon / Xeon MP / Celeron / Celeron D (unknown model)");
skipping to change at line 2876 skipping to change at line 2944
FMS (1,15, 0, 2, 3, "AMD Quad-Core Opteron (Barcelona DR-B3) / Embedded Opteron (Barcelona DR-B2) / Phenom Triple-Core (Toliman DR-B3) / Phenom Quad-Co re (Agena DR-B3) / Athlon Dual-Core (Kuma DR-B3) [K10], 65nm"); FMS (1,15, 0, 2, 3, "AMD Quad-Core Opteron (Barcelona DR-B3) / Embedded Opteron (Barcelona DR-B2) / Phenom Triple-Core (Toliman DR-B3) / Phenom Quad-Co re (Agena DR-B3) / Athlon Dual-Core (Kuma DR-B3) [K10], 65nm");
FMS (1,15, 0, 2, 10, "AMD Quad-Core Opteron (Barcelona DR-BA) [K10], 65n m"); FMS (1,15, 0, 2, 10, "AMD Quad-Core Opteron (Barcelona DR-BA) [K10], 65n m");
FMQ (1,15, 0, 2, EO, "AMD Embedded Opteron (Barcelona) [K10], 65nm"); FMQ (1,15, 0, 2, EO, "AMD Embedded Opteron (Barcelona) [K10], 65nm");
FMQ (1,15, 0, 2, dO, "AMD Quad-Core Opteron (Barcelona) [K10], 65nm"); FMQ (1,15, 0, 2, dO, "AMD Quad-Core Opteron (Barcelona) [K10], 65nm");
FMQ (1,15, 0, 2, Tp, "AMD Phenom Triple-Core (Toliman) [K10], 65nm"); FMQ (1,15, 0, 2, Tp, "AMD Phenom Triple-Core (Toliman) [K10], 65nm");
FMQ (1,15, 0, 2, Qp, "AMD Phenom Quad-Core (Agena) [K10], 65nm"); FMQ (1,15, 0, 2, Qp, "AMD Phenom Quad-Core (Agena) [K10], 65nm");
FMQ (1,15, 0, 2, dA, "AMD Athlon Dual-Core (Kuma) [K10], 65nm"); FMQ (1,15, 0, 2, dA, "AMD Athlon Dual-Core (Kuma) [K10], 65nm");
FM (1,15, 0, 2, "AMD Quad-Core Opteron (Barcelona) / Phenom Triple- Core (Toliman) / Phenom Quad-Core (Agena) / Athlon Dual-Core (Kuma) [K10], 65nm" ); FM (1,15, 0, 2, "AMD Quad-Core Opteron (Barcelona) / Phenom Triple- Core (Toliman) / Phenom Quad-Core (Agena) / Athlon Dual-Core (Kuma) [K10], 65nm" );
FMSQ(1,15, 0, 4, 2, EO, "AMD Embedded Opteron (Shanghai RB-C2) [K10], 45nm" ); FMSQ(1,15, 0, 4, 2, EO, "AMD Embedded Opteron (Shanghai RB-C2) [K10], 45nm" );
FMSQ(1,15, 0, 4, 2, dO, "AMD Quad-Core Opteron (Shanghai RB-C2) [K10], 45nm "); FMSQ(1,15, 0, 4, 2, dO, "AMD Quad-Core Opteron (Shanghai RB-C2) [K10], 45nm ");
FMSQ(1,15, 0, 4, 2, dR, "AMD Athlon Dual-Core (Propus RB-C2) [K10], 45nm"); FMSQ(1,15, 0, 4, 2, dr, "AMD Athlon Dual-Core (Propus RB-C2) [K10], 45nm");
FMSQ(1,15, 0, 4, 2, dA, "AMD Athlon Dual-Core (Regor RB-C2) [K10], 45nm"); FMSQ(1,15, 0, 4, 2, dA, "AMD Athlon Dual-Core (Regor RB-C2) [K10], 45nm");
FMSQ(1,15, 0, 4, 2, Dp, "AMD Phenom II X2 (Callisto RB-C2) [K10], 45nm"); FMSQ(1,15, 0, 4, 2, Dp, "AMD Phenom II X2 (Callisto RB-C2) [K10], 45nm");
FMSQ(1,15, 0, 4, 2, Tp, "AMD Phenom II X3 (Heka RB-C2) [K10], 45nm"); FMSQ(1,15, 0, 4, 2, Tp, "AMD Phenom II X3 (Heka RB-C2) [K10], 45nm");
FMSQ(1,15, 0, 4, 2, Qp, "AMD Phenom II X4 (Deneb RB-C2) [K10], 45nm"); FMSQ(1,15, 0, 4, 2, Qp, "AMD Phenom II X4 (Deneb RB-C2) [K10], 45nm");
FMS (1,15, 0, 4, 2, "AMD Quad-Core Opteron (Shanghai RB-C2) / Embedded Opteron (Shanghai RB-C2) / Athlon Dual-Core (Regor / Propus RB-C2) / Phenom II ( Callisto / Heka / Deneb RB-C2) [K10], 45nm"); FMS (1,15, 0, 4, 2, "AMD Quad-Core Opteron (Shanghai RB-C2) / Embedded Opteron (Shanghai RB-C2) / Athlon Dual-Core (Regor / Propus RB-C2) / Phenom II ( Callisto / Heka / Deneb RB-C2) [K10], 45nm");
FMSQ(1,15, 0, 4, 3, Dp, "AMD Phenom II X2 (Callisto RB-C3) [K10], 45nm"); FMSQ(1,15, 0, 4, 3, Dp, "AMD Phenom II X2 (Callisto RB-C3) [K10], 45nm");
FMSQ(1,15, 0, 4, 3, Tp, "AMD Phenom II X3 (Heka RB-C3) [K10], 45nm"); FMSQ(1,15, 0, 4, 3, Tp, "AMD Phenom II X3 (Heka RB-C3) [K10], 45nm");
FMSQ(1,15, 0, 4, 3, Qp, "AMD Phenom II X4 (Deneb RB-C3) [K10], 45nm"); FMSQ(1,15, 0, 4, 3, Qp, "AMD Phenom II X4 (Deneb RB-C3) [K10], 45nm");
FMS (1,15, 0, 4, 3, "AMD Phenom II (Callisto / Heka / Deneb RB-C3) [K10 ], 45nm"); FMS (1,15, 0, 4, 3, "AMD Phenom II (Callisto / Heka / Deneb RB-C3) [K10 ], 45nm");
FMQ (1,15, 0, 4, EO, "AMD Embedded Opteron (Shanghai) [K10], 45nm"); FMQ (1,15, 0, 4, EO, "AMD Embedded Opteron (Shanghai) [K10], 45nm");
FMQ (1,15, 0, 4, dO, "AMD Quad-Core Opteron (Shanghai) [K10], 45nm"); FMQ (1,15, 0, 4, dO, "AMD Quad-Core Opteron (Shanghai) [K10], 45nm");
FMQ (1,15, 0, 4, dR, "AMD Athlon Dual-Core (Propus) [K10], 45nm"); FMQ (1,15, 0, 4, dr, "AMD Athlon Dual-Core (Propus) [K10], 45nm");
FMQ (1,15, 0, 4, dA, "AMD Athlon Dual-Core (Regor) [K10], 45nm"); FMQ (1,15, 0, 4, dA, "AMD Athlon Dual-Core (Regor) [K10], 45nm");
FMQ (1,15, 0, 4, Dp, "AMD Phenom II X2 (Callisto) [K10], 45nm"); FMQ (1,15, 0, 4, Dp, "AMD Phenom II X2 (Callisto) [K10], 45nm");
FMQ (1,15, 0, 4, Tp, "AMD Phenom II X3 (Heka) [K10], 45nm"); FMQ (1,15, 0, 4, Tp, "AMD Phenom II X3 (Heka) [K10], 45nm");
FMQ (1,15, 0, 4, Qp, "AMD Phenom II X4 (Deneb) [K10], 45nm"); FMQ (1,15, 0, 4, Qp, "AMD Phenom II X4 (Deneb) [K10], 45nm");
FM (1,15, 0, 4, "AMD Quad-Core Opteron (Shanghai) / Athlon Dual-Cor e (Regor / Propus) / Phenom II (Callisto / Heka / Deneb) [K10], 45nm"); FM (1,15, 0, 4, "AMD Quad-Core Opteron (Shanghai) / Athlon Dual-Cor e (Regor / Propus) / Phenom II (Callisto / Heka / Deneb) [K10], 45nm");
FMSQ(1,15, 0, 5, 2, DA, "AMD Athlon II X2 (Regor BL-C2) [K10], 45nm"); FMSQ(1,15, 0, 5, 2, DA, "AMD Athlon II X2 (Regor BL-C2) [K10], 45nm");
FMSQ(1,15, 0, 5, 2, TA, "AMD Athlon II X3 (Rana BL-C2) [K10], 45nm"); FMSQ(1,15, 0, 5, 2, TA, "AMD Athlon II X3 (Rana BL-C2) [K10], 45nm");
FMSQ(1,15, 0, 5, 2, QA, "AMD Athlon II X4 (Propus BL-C2) [K10], 45nm"); FMSQ(1,15, 0, 5, 2, QA, "AMD Athlon II X4 (Propus BL-C2) [K10], 45nm");
FMS (1,15, 0, 5, 2, "AMD Athlon II X2 / X3 / X4 (Regor / Rana / Propus BL-C2) [K10], 45nm"); FMS (1,15, 0, 5, 2, "AMD Athlon II X2 / X3 / X4 (Regor / Rana / Propus BL-C2) [K10], 45nm");
FMSQ(1,15, 0, 5, 3, TA, "AMD Athlon II X3 (Rana BL-C3) [K10], 45nm"); FMSQ(1,15, 0, 5, 3, TA, "AMD Athlon II X3 (Rana BL-C3) [K10], 45nm");
skipping to change at line 3000 skipping to change at line 3068
FM (6,15, 3, 0, "AMD Elite Performance A-Series / AMD Mobile R-Seri es / Opteron X1200 / X2200 (Kaveri) [Steamroller], 28nm"); FM (6,15, 3, 0, "AMD Elite Performance A-Series / AMD Mobile R-Seri es / Opteron X1200 / X2200 (Kaveri) [Steamroller], 28nm");
FMS (6,15, 7, 0, 0, "AMD A-Series / E-Series / G-Series (Stoney Ridge S T-A0) [Excavator], 28nm"); FMS (6,15, 7, 0, 0, "AMD A-Series / E-Series / G-Series (Stoney Ridge S T-A0) [Excavator], 28nm");
FM (6,15, 7, 0, "AMD A-Series / E-Series / G-Series (Stoney Ridge) [Excavator], 28nm"); FM (6,15, 7, 0, "AMD A-Series / E-Series / G-Series (Stoney Ridge) [Excavator], 28nm");
F (6,15, "AMD Opteron 6x00 / Opteron 4x00 / Opteron 3x00 / A MD FX-Series / A-Series / E-Series / G-Series / R-Series / Opteron X1200 / X2200 / Athlon Dual-Core / Athlon Quad-Core / Sempron Dual-Core / FirePro"); F (6,15, "AMD Opteron 6x00 / Opteron 4x00 / Opteron 3x00 / A MD FX-Series / A-Series / E-Series / G-Series / R-Series / Opteron X1200 / X2200 / Athlon Dual-Core / Athlon Quad-Core / Sempron Dual-Core / FirePro");
FMS (7,15, 0, 0, 1, "AMD A-Series / E-Series / G-Series / Opteron X1100 Series / Opteron X2100 Series (Kabini KB-A1) [Jaguar], 28nm"); FMS (7,15, 0, 0, 1, "AMD A-Series / E-Series / G-Series / Opteron X1100 Series / Opteron X2100 Series (Kabini KB-A1) [Jaguar], 28nm");
FM (7,15, 0, 0, "AMD A-Series / E-Series / G-Series / Opteron X1100 Series / Opteron X2100 Series [Jaguar], 28nm"); FM (7,15, 0, 0, "AMD A-Series / E-Series / G-Series / Opteron X1100 Series / Opteron X2100 Series [Jaguar], 28nm");
// The AMD docs (53072) omit the CPUID entirely. But if this sticks to the // The AMD docs (53072) omit the CPUID entirely. But if this sticks to the
// recent AMD pattern, these must be (7,15),(3,0). // recent AMD pattern, these must be (7,15),(3,0).
FMS (7,15, 3, 0, 1, "AMD A-Series / E-Series Series (Mullins ML-A1) [Pu ma 2014], 28nm"); FMS (7,15, 3, 0, 1, "AMD A-Series / E-Series Series (Mullins ML-A1) [Pu ma 2014], 28nm");
FM (7,15, 3, 0, "AMD A-Series / E-Series Series (Mullins) [Puma 201 4], 28nm"); FM (7,15, 3, 0, "AMD A-Series / E-Series Series (Mullins) [Puma 201 4], 28nm");
FMS (8,15, 0, 1, 1, "AMD Ryzen (Summit Ridge B1) [Zen], 14nm"); FMSQ(8,15, 0, 1, 0, dR, "AMD Ryzen (Summit Ridge ZP-B0) [Zen], 14nm");
FM (8,15, 0, 1, "AMD Ryzen (Summit Ridge) [Zen], 14nm"); FMSQ(8,15, 0, 1, 1, dR, "AMD Ryzen (Summit Ridge ZP-B1) [Zen], 14nm");
FMSQ(8,15, 0, 1, 2, dR, "AMD Ryzen (Summit Ridge ZP-B2) [Zen], 14nm");
FMQ (8,15, 0, 1, dR, "AMD Ryzen (Summit Ridge) [Zen], 14nm");
FMSQ(8,15, 0, 1, 0, sE, "AMD EPYC (Naples B0) [Zen], 14nm");
FMSQ(8,15, 0, 1, 1, sE, "AMD EPYC (Naples B1) [Zen], 14nm");
FMSQ(8,15, 0, 1, 2, sE, "AMD EPYC (Naples B2) [Zen], 14nm");
FMQ (8,15, 0, 1, sE, "AMD EPYC (Naples) [Zen], 14nm");
FMS (8,15, 0, 1, 0, "AMD Ryzen (Summit Ridge ZP-B0) / EPYC (Naples B0)
[Zen], 14nm");
FMS (8,15, 0, 1, 1, "AMD Ryzen (Summit Ridge ZP-B1) / EPYC (Naples B1)
[Zen], 14nm");
FMS (8,15, 0, 1, 2, "AMD Ryzen (Summit Ridge ZP-B2) / EPYC (Naples B2)
[Zen], 14nm");
FM (8,15, 0, 1, "AMD Ryzen (Summit Ridge) / EPYC (Naples) [Zen], 14
nm");
FM (8,15, 1, 1, "AMD Ryzen (Raven Ridge) [Zen], 14nm"); // found on
ly on en.wikichip.org
FMSQ(8,15, 0, 8, 2, dR, "AMD Ryzen (Pinnacle Ridge PiR-B2) [Zen+], 12nm");
FMQ (8,15, 0, 8, dR, "AMD Ryzen (Pinnacle Ridge) [Zen+], 12nm");
FMS (8,15, 0, 8, 2, "AMD Ryzen (Pinnacle Ridge PiR-B2) [Zen+], 12nm");
FM (8,15, 0, 8, "AMD Ryzen (Pinnacle Ridge) [Zen+], 12nm");
FM (8,15, 1, 8, "AMD Ryzen (Picasso) [Zen+], 12nm"); // found only
on en.wikichip.org
FM (8,15, 3, 1, "AMD Ryzen (Castle Peak) / EPYC (Rome) [Zen 2], 7nm
"); // found only on en.wikichip.org
FM (8,15, 7, 1, "AMD Ryzen (Matisse) [Zen 2], 7nm"); // found only
on en.wikichip.org
DEFAULT ("unknown");
const char* brand_pre;
const char* brand_post;
char proc[96];
decode_amd_model(stash, &brand_pre, &brand_post, proc);
if (proc[0] != '\0') {
printf(" %s", proc);
}
printf("\n");
}
static void
print_synth_hygon(const char* name,
unsigned int val,
const code_stash_t* stash)
{
printf("%s", name);
START;
FMS (9,15, 0, 0, 1, "Hygon Dhyana (A1) [Moksha], 14nm");
FMS (9,15, 0, 0, 2, "Hygon Dhyana (A2) [Moksha], 14nm");
DEFAULT ("unknown"); DEFAULT ("unknown");
const char* brand_pre; const char* brand_pre;
const char* brand_post; const char* brand_post;
char proc[96]; char proc[96];
decode_amd_model(stash, &brand_pre, &brand_post, proc); decode_amd_model(stash, &brand_pre, &brand_post, proc);
if (proc[0] != '\0') { if (proc[0] != '\0') {
printf(" %s", proc); printf(" %s", proc);
} }
skipping to change at line 3229 skipping to change at line 3338
FMS (0, 7, 0, 8, 1, "AMD Athlon XP / Athlon MP / Sempron / Duron / Duron MP (Thoroughbred B0)"); FMS (0, 7, 0, 8, 1, "AMD Athlon XP / Athlon MP / Sempron / Duron / Duron MP (Thoroughbred B0)");
FM (0, 7, 0, 8, "AMD Athlon XP / Athlon MP / Sempron / Duron / Duron MP (Thoroughbred)"); FM (0, 7, 0, 8, "AMD Athlon XP / Athlon MP / Sempron / Duron / Duron MP (Thoroughbred)");
FMS (0, 7, 0,10, 0, "AMD Athlon XP / Athlon MP / Sempron / mobile Athlon XP -M / mobile Athlon XP-M (LV) (Barton A2)"); FMS (0, 7, 0,10, 0, "AMD Athlon XP / Athlon MP / Sempron / mobile Athlon XP -M / mobile Athlon XP-M (LV) (Barton A2)");
FM (0, 7, 0,10, "AMD Athlon XP / Athlon MP / Sempron / mobile Athlon XP -M / mobile Athlon XP-M (LV) (Barton)"); FM (0, 7, 0,10, "AMD Athlon XP / Athlon MP / Sempron / mobile Athlon XP -M / mobile Athlon XP-M (LV) (Barton)");
F (0, 7, "AMD Athlon XP / Athlon MP / Sempron / Duron / Duron MP / mobile Athlon / mobile Athlon XP-M / mobile Athlon XP-M (LV) / mobile Duron ( unknown model)"); F (0, 7, "AMD Athlon XP / Athlon MP / Sempron / Duron / Duron MP / mobile Athlon / mobile Athlon XP-M / mobile Athlon XP-M (LV) / mobile Duron ( unknown model)");
FALLBACK({ print_synth_amd("", val, NULL); return; }) FALLBACK({ print_synth_amd("", val, NULL); return; })
printf("\n"); printf("\n");
} }
static void static void
print_x_synth_hygon(unsigned int val)
{
printf(" (simple synth) = ");
START;
FALLBACK({ print_synth_hygon("", val, NULL); return; })
printf("\n");
}
static void
print_x_synth_via(unsigned int val) print_x_synth_via(unsigned int val)
{ {
printf(" (simple synth) = "); printf(" (simple synth) = ");
START; START;
FM (0,6, 0,6, "VIA C3 (WinChip C5A)"); FM (0,6, 0,6, "VIA C3 (WinChip C5A)");
FM (0,6, 0,6, "VIA C3 (WinChip C5A)"); FM (0,6, 0,6, "VIA C3 (WinChip C5A)");
FMS(0,6, 0,7, 0, "VIA C3 (WinChip C5B)"); FMS(0,6, 0,7, 0, "VIA C3 (WinChip C5B)");
FMS(0,6, 0,7, 1, "VIA C3 (WinChip C5B)"); FMS(0,6, 0,7, 1, "VIA C3 (WinChip C5B)");
FMS(0,6, 0,7, 2, "VIA C3 (WinChip C5B)"); FMS(0,6, 0,7, 2, "VIA C3 (WinChip C5B)");
FMS(0,6, 0,7, 3, "VIA C3 (WinChip C5B)"); FMS(0,6, 0,7, 3, "VIA C3 (WinChip C5B)");
skipping to change at line 3292 skipping to change at line 3411
break; break;
case VENDOR_NSC: case VENDOR_NSC:
print_synth_nsc(" (simple synth) = ", val_eax); print_synth_nsc(" (simple synth) = ", val_eax);
break; break;
case VENDOR_VORTEX: case VENDOR_VORTEX:
print_synth_vortex(" (simple synth) = ", val_eax); print_synth_vortex(" (simple synth) = ", val_eax);
break; break;
case VENDOR_RDC: case VENDOR_RDC:
print_synth_rdc(" (simple synth) = ", val_eax); print_synth_rdc(" (simple synth) = ", val_eax);
break; break;
case VENDOR_HYGON:
print_synth_hygon(" (simple synth) = ", val_eax, NULL);
break;
case VENDOR_UNKNOWN: case VENDOR_UNKNOWN:
/* DO NOTHING */ /* DO NOTHING */
break; break;
} }
} }
static void static void
print_synth(const code_stash_t* stash) print_synth(const code_stash_t* stash)
{ {
switch (stash->vendor) { switch (stash->vendor) {
skipping to change at line 3338 skipping to change at line 3460
break; break;
case VENDOR_NSC: case VENDOR_NSC:
print_synth_nsc(" (synth) = ", stash->val_1_eax); print_synth_nsc(" (synth) = ", stash->val_1_eax);
break; break;
case VENDOR_VORTEX: case VENDOR_VORTEX:
print_synth_vortex(" (synth) = ", stash->val_1_eax); print_synth_vortex(" (synth) = ", stash->val_1_eax);
break; break;
case VENDOR_RDC: case VENDOR_RDC:
print_synth_rdc(" (synth) = ", stash->val_1_eax); print_synth_rdc(" (synth) = ", stash->val_1_eax);
break; break;
case VENDOR_HYGON:
print_synth_hygon(" (synth) = ", stash->val_1_eax, stash);
break;
case VENDOR_UNKNOWN: case VENDOR_UNKNOWN:
/* DO NOTHING */ /* DO NOTHING */
break; break;
} }
} }
#define GET_ApicIdCoreIdSize(val_80000008_ecx) \ #define GET_ApicIdCoreIdSize(val_80000008_ecx) \
(BIT_EXTRACT_LE((val_80000008_ecx), 0, 4)) (BIT_EXTRACT_LE((val_80000008_ecx), 0, 4))
#define GET_LogicalProcessorCount(val_1_ebx) \ #define GET_LogicalProcessorCount(val_1_ebx) \
(BIT_EXTRACT_LE((val_1_ebx), 16, 24)) (BIT_EXTRACT_LE((val_1_ebx), 16, 24))
#define IS_HTT(val_1_edx) \ #define IS_HTT(val_1_edx) \
(BIT_EXTRACT_LE((val_1_edx), 28, 29)) (BIT_EXTRACT_LE((val_1_edx), 28, 29))
#define IS_CmpLegacy(val_80000001_ecx) \ #define IS_CmpLegacy(val_80000001_ecx) \
(BIT_EXTRACT_LE((val_80000001_ecx), 1, 2)) (BIT_EXTRACT_LE((val_80000001_ecx), 1, 2))
#define GET_NC_INTEL(val_4_eax) \ #define GET_NC_INTEL(val_4_eax) \
(BIT_EXTRACT_LE((val_4_eax), 26, 32)) (BIT_EXTRACT_LE((val_4_eax), 26, 32))
#define GET_NC_AMD(val_80000008_ecx) \ #define GET_NC_AMD(val_80000008_ecx) \
(BIT_EXTRACT_LE((val_80000008_ecx), 0, 8)) (BIT_EXTRACT_LE((val_80000008_ecx), 0, 8))
#define GET_X2APIC_PROCESSORS(val_b_ebx) \ #define GET_X2APIC_PROCESSORS(val_b_ebx) \
(BIT_EXTRACT_LE((val_b_ebx), 0, 16)) (BIT_EXTRACT_LE((val_b_ebx), 0, 16))
#define GET_V2_TOPO_LEVEL(val_1f_ecx) \
(BIT_EXTRACT_LE((val_1f_ecx), 8, 16))
#define GET_V2_TOPO_PROCESSORS(val_1f_ebx) \
(BIT_EXTRACT_LE((val_1f_ebx), 0, 16))
#define GET_CoresPerComputeUnit_AMD(val_8000001e_ebx) \
(BIT_EXTRACT_LE((val_8000001e_ebx), 8, 16))
#define V2_TOPO_SMT 1
#define V2_TOPO_CORE 2
static void decode_mp_synth(code_stash_t* stash) static void decode_mp_synth(code_stash_t* stash)
{ {
switch (stash->vendor) { switch (stash->vendor) {
case VENDOR_INTEL: case VENDOR_INTEL:
/* /*
** Logic derived from information in: ** Logic derived from information in:
** Detecting Multi-Core Processor Topology in an IA-32 Platform ** Detecting Multi-Core Processor Topology in an IA-32 Platform
** by Khang Nguyen and Shihjong Kuo ** by Khang Nguyen and Shihjong Kuo
** and: ** and:
** Intel 64 Architecture Processor Topology Enumeration (Whitepaper) ** Intel 64 Architecture Processor Topology Enumeration (Whitepaper)
** by Shih Kuo ** by Shih Kuo
** Extension to the 0x1f leaf was obvious.
*/ */
if (stash->saw_b) { if (stash->saw_1f) {
stash->mp.method = "Intel leaf 0x1f";
unsigned int try;
for (try = 0; try < LENGTH(stash->val_1f_ecx); try++) {
if (GET_V2_TOPO_LEVEL(stash->val_1f_ecx[try]) == V2_TOPO_SMT) {
stash->mp.hyperthreads
= GET_V2_TOPO_PROCESSORS(stash->val_1f_ebx[try]);
} else if (GET_V2_TOPO_LEVEL(stash->val_1f_ecx[try]) == V2_TOPO_CORE
) {
stash->mp.cores = GET_V2_TOPO_PROCESSORS(stash->val_1f_ebx[try]);
}
}
} else if (stash->saw_b) {
unsigned int ht = GET_X2APIC_PROCESSORS(stash->val_b_ebx[0]); unsigned int ht = GET_X2APIC_PROCESSORS(stash->val_b_ebx[0]);
unsigned int tc = GET_X2APIC_PROCESSORS(stash->val_b_ebx[1]); unsigned int tc = GET_X2APIC_PROCESSORS(stash->val_b_ebx[1]);
stash->mp.method = "Intel leaf 0xb"; stash->mp.method = "Intel leaf 0xb";
if (ht == 0) { if (ht == 0) {
ht = 1; ht = 1;
} }
stash->mp.cores = tc / ht; stash->mp.cores = tc / ht;
stash->mp.hyperthreads = ht; stash->mp.hyperthreads = ht;
} else if (stash->saw_4) { } else if (stash->saw_4) {
unsigned int tc = GET_LogicalProcessorCount(stash->val_1_ebx); unsigned int tc = GET_LogicalProcessorCount(stash->val_1_ebx);
skipping to change at line 3405 skipping to change at line 3551
stash->mp.cores = 1; stash->mp.cores = 1;
if (IS_HTT(stash->val_1_edx)) { if (IS_HTT(stash->val_1_edx)) {
unsigned int tc = GET_LogicalProcessorCount(stash->val_1_ebx); unsigned int tc = GET_LogicalProcessorCount(stash->val_1_ebx);
stash->mp.hyperthreads = (tc >= 2 ? tc : 2); stash->mp.hyperthreads = (tc >= 2 ? tc : 2);
} else { } else {
stash->mp.hyperthreads = 1; stash->mp.hyperthreads = 1;
} }
} }
break; break;
case VENDOR_AMD: case VENDOR_AMD:
case VENDOR_HYGON:
/* /*
** Logic from: ** Logic from:
** AMD CPUID Specification (25481 Rev. 2.16), ** AMD CPUID Specification (25481 Rev. 2.16),
** 3. LogicalProcessorCount, CmpLegacy, HTT, and NC ** 3. LogicalProcessorCount, CmpLegacy, HTT, and NC
** AMD CPUID Specification (25481 Rev. 2.28), ** AMD CPUID Specification (25481 Rev. 2.28),
** 3. Multiple Core Calculation ** 3. Multiple Core Calculation
*/ */
if (IS_HTT(stash->val_1_edx)) { if (IS_HTT(stash->val_1_edx)) {
unsigned int tc = GET_LogicalProcessorCount(stash->val_1_ebx); unsigned int tc = GET_LogicalProcessorCount(stash->val_1_ebx);
unsigned int c; unsigned int c;
if (GET_ApicIdCoreIdSize(stash->val_80000008_ecx) != 0) { if (GET_ApicIdCoreIdSize(stash->val_80000008_ecx) != 0) {
unsigned int size = GET_ApicIdCoreIdSize(stash->val_80000008_ecx); unsigned int size = GET_ApicIdCoreIdSize(stash->val_80000008_ecx);
unsigned int mask = (1 << size) - 1; unsigned int mask = (1 << size) - 1;
c = (GET_NC_AMD(stash->val_80000008_ecx) & mask) + 1; c = (GET_NC_AMD(stash->val_80000008_ecx) & mask) + 1;
} else { } else {
c = GET_NC_AMD(stash->val_80000008_ecx) + 1; c = GET_NC_AMD(stash->val_80000008_ecx) + 1;
} }
if ((tc == c) == IS_CmpLegacy(stash->val_80000001_ecx)) { if ((tc == c) == IS_CmpLegacy(stash->val_80000001_ecx)) {
stash->mp.method = "AMD"; stash->mp.method = (stash->vendor == VENDOR_AMD ? "AMD"
: "Hygon");
if (c > 1) { if (c > 1) {
stash->mp.cores = c; stash->mp.cores = c;
stash->mp.hyperthreads = tc / c; stash->mp.hyperthreads = tc / c;
} else { } else {
stash->mp.cores = 1; stash->mp.cores = 1;
stash->mp.hyperthreads = (tc >= 2 ? tc : 2); stash->mp.hyperthreads = (tc >= 2 ? tc : 2);
} }
} else { } else {
/* /*
** Rev 2.28 leaves out mention that this case is nonsensical, but ** Rev 2.28 leaves out mention that this case is nonsensical, but
** I'm leaving it in here as an "unknown" case. ** I'm leaving it in here as an "unknown" case.
*/ */
} }
} else { } else {
stash->mp.method = "AMD"; stash->mp.method = (stash->vendor == VENDOR_AMD ? "AMD" : "Hygon");
stash->mp.cores = 1; stash->mp.cores = 1;
stash->mp.hyperthreads = 1; stash->mp.hyperthreads = 1;
} }
break; break;
default: default:
if (!IS_HTT(stash->val_1_edx)) { if (!IS_HTT(stash->val_1_edx)) {
stash->mp.method = "Generic leaf 1 no multi-threading"; stash->mp.method = "Generic leaf 1 no multi-threading";
stash->mp.cores = 1; stash->mp.cores = 1;
stash->mp.hyperthreads = 1; stash->mp.hyperthreads = 1;
} }
skipping to change at line 3510 skipping to change at line 3658
"1:" "1:"
: [result] "=rm" (result) : [result] "=rm" (result)
: [v] "irm" (v) : [v] "irm" (v)
: "eax", "ecx"); : "eax", "ecx");
#endif #endif
return result; return result;
} }
#define GET_X2APIC_WIDTH(val_b_eax) \ #define GET_X2APIC_WIDTH(val_b_eax) \
(BIT_EXTRACT_LE((val_b_eax), 0, 5)) (BIT_EXTRACT_LE((val_b_eax), 0, 5))
#define GET_V2_TOPO_WIDTH(val_1f_eax) \
(BIT_EXTRACT_LE((val_1f_eax), 0, 5))
static void print_apic_synth (code_stash_t* stash) static void print_apic_synth (code_stash_t* stash)
{ {
unsigned int smt_width; unsigned int smt_width = 0;
unsigned int core_width; unsigned int core_width = 0;
unsigned int cu_width = 0;
switch (stash->vendor) { switch (stash->vendor) {
case VENDOR_INTEL: case VENDOR_INTEL:
/* /*
** Logic derived from information in: ** Logic derived from information in:
** Detecting Multi-Core Processor Topology in an IA-32 Platform ** Detecting Multi-Core Processor Topology in an IA-32 Platform
** by Khang Nguyen and Shihjong Kuo ** by Khang Nguyen and Shihjong Kuo
** and: ** and:
** Intel 64 Architecture Processor Topology Enumeration (Whitepaper) ** Intel 64 Architecture Processor Topology Enumeration (Whitepaper)
** by Shih Kuo ** by Shih Kuo
** Extension to the 0x1f leaf was obvious.
*/ */
if (stash->saw_b) { if (stash->saw_1f) {
unsigned int try;
for (try = 0; try < LENGTH(stash->val_1f_ecx); try++) {
unsigned int level = GET_V2_TOPO_LEVEL(stash->val_1f_ecx[try]);
if (level == V2_TOPO_SMT) {
smt_width = GET_V2_TOPO_WIDTH(stash->val_1f_eax[try]);
} else if (level == V2_TOPO_CORE) {
core_width = GET_V2_TOPO_WIDTH(stash->val_1f_eax[try]);
}
}
} else if (stash->saw_b) {
smt_width = GET_X2APIC_WIDTH(stash->val_b_eax[0]); smt_width = GET_X2APIC_WIDTH(stash->val_b_eax[0]);
core_width = GET_X2APIC_WIDTH(stash->val_b_eax[1]); core_width = GET_X2APIC_WIDTH(stash->val_b_eax[1]);
} else if (stash->saw_4 && (stash->val_4_eax & 0x1f) != 0) { } else if (stash->saw_4 && (stash->val_4_eax & 0x1f) != 0) {
unsigned int core_count = GET_NC_INTEL(stash->val_4_eax) + 1; unsigned int core_count = GET_NC_INTEL(stash->val_4_eax) + 1;
unsigned int smt_count = (GET_LogicalProcessorCount(stash->val_1_ebx) unsigned int smt_count = (GET_LogicalProcessorCount(stash->val_1_ebx)
/ core_count); / core_count);
smt_width = bits_needed(smt_count); smt_width = bits_needed(smt_count);
core_width = bits_needed(core_count); core_width = bits_needed(core_count);
} else { } else {
return; return;
} }
break; break;
case VENDOR_AMD: case VENDOR_AMD:
/* /*
** Logic deduced by analogy: As Intel's decode_mp_synth code is to AMD's ** Logic deduced by analogy: As Intel's decode_mp_synth code is to AMD's
** decode_mp_synth code, so is Intel's APIC synth code to this. ** decode_mp_synth code, so is Intel's APIC synth code to this.
**
** The CU (CMT "compute unit") logic was a logical extension.
*/ */
if (IS_HTT(stash->val_1_edx) if (IS_HTT(stash->val_1_edx)
&& GET_ApicIdCoreIdSize(stash->val_80000008_ecx) != 0) { && GET_ApicIdCoreIdSize(stash->val_80000008_ecx) != 0) {
unsigned int size = GET_ApicIdCoreIdSize(stash->val_80000008_ecx); unsigned int size = GET_ApicIdCoreIdSize(stash->val_80000008_ecx);
unsigned int mask = (1 << size) - 1; unsigned int mask = (1 << size) - 1;
unsigned int core_count = ((GET_NC_AMD(stash->val_80000008_ecx) & mask ) unsigned int core_count = ((GET_NC_AMD(stash->val_80000008_ecx) & mask )
+ 1); + 1);
unsigned int smt_count = (GET_LogicalProcessorCount(stash->val_1_ebx) unsigned int smt_count = (GET_LogicalProcessorCount(stash->val_1_ebx)
/ core_count); / core_count);
smt_width = bits_needed(smt_count); unsigned int cu_count = 1;
core_width = bits_needed(core_count); if (GET_CoresPerComputeUnit_AMD(stash->val_8000001e_ebx) != 0) {
unsigned int cores_per_cu
= GET_CoresPerComputeUnit_AMD(stash->val_8000001e_ebx) + 1;
cu_count = (core_count / cores_per_cu);
core_count = cores_per_cu;
}
smt_width = bits_needed(smt_count);
core_width = bits_needed(core_count);
cu_width = bits_needed(cu_count);
} else { } else {
return; return;
} }
break; break;
default: default:
return; return;
} }
unsigned int smt_off = 24; // Possibly this should be expanded with Intel leaf 1f's module, tile, and
unsigned int core_off = smt_off + smt_width; // die levels. They could be made into hidden architectural levels unless
unsigned int pkg_off = core_off + core_width; // actually present, much like the CU level.
printf(" (APIC widths synth):");
if (cu_width != 0) {
printf(" CU_width=%u", cu_width);
}
printf(" CORE_width=%u", core_width);
printf(" SMT_width=%u", smt_width);
printf("\n");
unsigned int smt_off = 24;
unsigned int smt_tail = smt_off + smt_width;
unsigned int core_off = smt_tail;
unsigned int core_tail = core_off + core_width;
unsigned int cu_off = core_tail;
unsigned int cu_tail = cu_off + cu_width;
unsigned int pkg_off = cu_tail;
unsigned int pkg_tail = 32;
printf(" (APIC widths synth): CORE_width=%d SMT_width=%d\n",
core_width, smt_width);
printf(" (APIC synth):"); printf(" (APIC synth):");
printf(" PKG_ID=%d", (pkg_off < 32 printf(" PKG_ID=%d", (pkg_off < pkg_tail
? BIT_EXTRACT_LE(stash->val_1_ebx, pkg_off, 32) ? BIT_EXTRACT_LE(stash->val_1_ebx, pkg_off, pkg_tail)
: 0)); : 0));
printf(" CORE_ID=%d", BIT_EXTRACT_LE(stash->val_1_ebx, core_off, pkg_off)); if (cu_width != 0) {
printf(" SMT_ID=%d", BIT_EXTRACT_LE(stash->val_1_ebx, smt_off, core_off)); printf(" CU_ID=%d", BIT_EXTRACT_LE(stash->val_1_ebx, cu_off, cu_tail));
}
printf(" CORE_ID=%d", BIT_EXTRACT_LE(stash->val_1_ebx, core_off, core_tail));
printf(" SMT_ID=%d", BIT_EXTRACT_LE(stash->val_1_ebx, smt_off, smt_tail));
printf("\n"); printf("\n");
} }
static void print_instr_synth_amd (code_stash_t* stash) static void print_instr_synth_amd (code_stash_t* stash)
{ {
boolean cmpxchg8b = (BIT_EXTRACT_LE(stash->val_80000001_edx, 8, 9) boolean cmpxchg8b = (BIT_EXTRACT_LE(stash->val_80000001_edx, 8, 9)
|| BIT_EXTRACT_LE(stash->val_1_edx, 8, 9)); || BIT_EXTRACT_LE(stash->val_1_edx, 8, 9));
boolean cond = (BIT_EXTRACT_LE(stash->val_80000001_edx, 15, 16) boolean cond = (BIT_EXTRACT_LE(stash->val_80000001_edx, 15, 16)
|| BIT_EXTRACT_LE(stash->val_1_edx, 15, 16)); || BIT_EXTRACT_LE(stash->val_1_edx, 15, 16));
boolean prefetch = (BIT_EXTRACT_LE(stash->val_80000001_ecx, 8, 9) boolean prefetch = (BIT_EXTRACT_LE(stash->val_80000001_ecx, 8, 9)
skipping to change at line 3597 skipping to change at line 3787
printf(" (instruction supported synth):\n"); printf(" (instruction supported synth):\n");
printf(" CMPXCHG8B = %s\n", bools[cmpxchg8b]); printf(" CMPXCHG8B = %s\n", bools[cmpxchg8b]);
printf(" conditional move/compare = %s\n", bools[cond]); printf(" conditional move/compare = %s\n", bools[cond]);
printf(" PREFETCH/PREFETCHW = %s\n", bools[prefetch]); printf(" PREFETCH/PREFETCHW = %s\n", bools[prefetch]);
} }
static void print_instr_synth (code_stash_t* stash) static void print_instr_synth (code_stash_t* stash)
{ {
switch (stash->vendor) { switch (stash->vendor) {
case VENDOR_AMD: case VENDOR_AMD:
case VENDOR_HYGON:
print_instr_synth_amd(stash); print_instr_synth_amd(stash);
break; break;
default: default:
break; break;
} }
} }
static void do_final (boolean raw, static void do_final (boolean raw,
boolean debug, boolean debug,
code_stash_t* stash) code_stash_t* stash)
skipping to change at line 3669 skipping to change at line 3860
static named_item names[] static named_item names[]
= { { "processor type" , 12, 13, processor }, = { { "processor type" , 12, 13, processor },
{ "family" , 8, 11, family }, { "family" , 8, 11, family },
{ "model" , 4, 7, NIL_IMAGES }, { "model" , 4, 7, NIL_IMAGES },
{ "stepping id" , 0, 3, NIL_IMAGES }, { "stepping id" , 0, 3, NIL_IMAGES },
{ "extended family" , 20, 27, NIL_IMAGES }, { "extended family" , 20, 27, NIL_IMAGES },
{ "extended model" , 16, 19, NIL_IMAGES }, { "extended model" , 16, 19, NIL_IMAGES },
}; };
printf(" version information (1/eax):\n"); printf(" version information (1/eax):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
print_synth_simple(value, vendor); print_synth_simple(value, vendor);
} }
#define B(b,str) \ #define B(b,str) \
else if ( __B(val_ebx) == _B(b)) \ else if ( __B(val_ebx) == _B(b)) \
printf(str) printf(str)
#define FMB(xf,f,xm,m,b,str) \ #define FMB(xf,f,xm,m,b,str) \
else if ( __FM(val_eax) == _FM(xf,f,xm,m) \ else if ( __FM(val_eax) == _FM(xf,f,xm,m) \
skipping to change at line 3743 skipping to change at line 3934
print_1_ebx(unsigned int value) print_1_ebx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "process local APIC physical ID" , 24, 31, NIL_IMAGES }, = { { "process local APIC physical ID" , 24, 31, NIL_IMAGES },
{ "cpu count" , 16, 23, NIL_IMAGES }, { "cpu count" , 16, 23, NIL_IMAGES },
{ "CLFLUSH line size" , 8, 15, NIL_IMAGES }, { "CLFLUSH line size" , 8, 15, NIL_IMAGES },
{ "brand index" , 0, 7, NIL_IMAGES }, { "brand index" , 0, 7, NIL_IMAGES },
}; };
printf(" miscellaneous (1/ebx):\n"); printf(" miscellaneous (1/ebx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_1_ecx(unsigned int value) print_1_ecx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "PNI/SSE3: Prescott New Instructions" , 0, 0, bools }, = { { "PNI/SSE3: Prescott New Instructions" , 0, 0, bools },
{ "PCLMULDQ instruction" , 1, 1, bools }, { "PCLMULDQ instruction" , 1, 1, bools },
{ "DTES64: 64-bit debug store" , 2, 2, bools }, { "DTES64: 64-bit debug store" , 2, 2, bools },
skipping to change at line 3785 skipping to change at line 3976
{ "AES instruction" , 25, 25, bools }, { "AES instruction" , 25, 25, bools },
{ "XSAVE/XSTOR states" , 26, 26, bools }, { "XSAVE/XSTOR states" , 26, 26, bools },
{ "OS-enabled XSAVE/XSTOR" , 27, 27, bools }, { "OS-enabled XSAVE/XSTOR" , 27, 27, bools },
{ "AVX: advanced vector extensions" , 28, 28, bools }, { "AVX: advanced vector extensions" , 28, 28, bools },
{ "F16C half-precision convert instruction" , 29, 29, bools }, { "F16C half-precision convert instruction" , 29, 29, bools },
{ "RDRAND instruction" , 30, 30, bools }, { "RDRAND instruction" , 30, 30, bools },
{ "hypervisor guest status" , 31, 31, bools }, { "hypervisor guest status" , 31, 31, bools },
}; };
printf(" feature information (1/ecx):\n"); printf(" feature information (1/ecx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_1_edx(unsigned int value) print_1_edx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "x87 FPU on chip" , 0, 0, bools }, = { { "x87 FPU on chip" , 0, 0, bools },
{ "VME: virtual-8086 mode enhancement" , 1, 1, bools }, { "VME: virtual-8086 mode enhancement" , 1, 1, bools },
{ "DE: debugging extensions" , 2, 2, bools }, { "DE: debugging extensions" , 2, 2, bools },
skipping to change at line 3826 skipping to change at line 4017
{ "SSE extensions" , 25, 25, bools }, { "SSE extensions" , 25, 25, bools },
{ "SSE2 extensions" , 26, 26, bools }, { "SSE2 extensions" , 26, 26, bools },
{ "SS: self snoop" , 27, 27, bools }, { "SS: self snoop" , 27, 27, bools },
{ "hyper-threading / multi-core supported" , 28, 28, bools }, { "hyper-threading / multi-core supported" , 28, 28, bools },
{ "TM: therm. monitor" , 29, 29, bools }, { "TM: therm. monitor" , 29, 29, bools },
{ "IA64" , 30, 30, bools }, { "IA64" , 30, 30, bools },
{ "PBE: pending break event" , 31, 31, bools }, { "PBE: pending break event" , 31, 31, bools },
}; };
printf(" feature information (1/edx):\n"); printf(" feature information (1/edx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void print_2_byte(unsigned char value, static void print_2_byte(unsigned char value,
vendor_t vendor, vendor_t vendor,
unsigned int val_1_eax) unsigned int val_1_eax)
{ {
if (value == 0x00) return; if (value == 0x00) return;
printf(" 0x%02x: ", value); printf(" 0x%02x: ", value);
#define CONT "\n " #define CONT "\n "
if (vendor == VENDOR_CYRIX || vendor == VENDOR_VIA) { if (vendor == VENDOR_CYRIX || vendor == VENDOR_VIA) {
switch (value) { switch (value) {
case 0x70: printf("TLB: 4K pages, 4-way, 32 entries"); return; case 0x70: printf("TLB: 4K pages, 4-way, 32 entries\n"); return;
case 0x74: printf("Cyrix-specific: ?"); return; case 0x74: printf("Cyrix-specific: ?\n"); return;
case 0x77: printf("Cyrix-specific: ?"); return; case 0x77: printf("Cyrix-specific: ?\n"); return;
case 0x80: printf("L1 cache: 16K, 4-way, 16 byte lines"); return; case 0x80: printf("L1 cache: 16K, 4-way, 16 byte lines\n"); return;
case 0x82: printf("Cyrix-specific: ?"); return; case 0x82: printf("Cyrix-specific: ?\n"); return;
case 0x84: printf("L2 cache: 1M, 8-way, 32 byte lines"); return; case 0x84: printf("L2 cache: 1M, 8-way, 32 byte lines\n"); return;
} }
} }
switch (value) { switch (value) {
case 0x01: printf("instruction TLB: 4K pages, 4-way, 32 entries"); break; case 0x01: printf("instruction TLB: 4K pages, 4-way, 32 entries"); break;
case 0x02: printf("instruction TLB: 4M pages, 4-way, 2 entries"); break; case 0x02: printf("instruction TLB: 4M pages, 4-way, 2 entries"); break;
case 0x03: printf("data TLB: 4K pages, 4-way, 64 entries"); break; case 0x03: printf("data TLB: 4K pages, 4-way, 64 entries"); break;
case 0x04: printf("data TLB: 4M pages, 4-way, 8 entries"); break; case 0x04: printf("data TLB: 4M pages, 4-way, 8 entries"); break;
case 0x05: printf("data TLB: 4M pages, 4-way, 32 entries"); break; case 0x05: printf("data TLB: 4M pages, 4-way, 32 entries"); break;
case 0x06: printf("L1 instruction cache: 8K, 4-way, 32 byte lines"); break; case 0x06: printf("L1 instruction cache: 8K, 4-way, 32 byte lines"); break;
skipping to change at line 4023 skipping to change at line 4214
"unified cache (3)" }; "unified cache (3)" };
static named_item names[] static named_item names[]
= { { "cache type" , 0, 4, cache_type }, = { { "cache type" , 0, 4, cache_type },
{ "cache level" , 5, 7, NIL_IMAGES }, { "cache level" , 5, 7, NIL_IMAGES },
{ "self-initializing cache level" , 8, 8, bools }, { "self-initializing cache level" , 8, 8, bools },
{ "fully associative cache" , 9, 9, bools }, { "fully associative cache" , 9, 9, bools },
{ "extra threads sharing this cache" , 14, 25, NIL_IMAGES }, { "extra threads sharing this cache" , 14, 25, NIL_IMAGES },
{ "extra processor cores on this die" , 26, 31, NIL_IMAGES }, { "extra processor cores on this die" , 26, 31, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 36); /* max_len => */ 36);
} }
static void static void
print_4_ebx(unsigned int value) print_4_ebx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "system coherency line size" , 0, 11, NIL_IMAGES }, = { { "system coherency line size" , 0, 11, NIL_IMAGES },
{ "physical line partitions" , 12, 21, NIL_IMAGES }, { "physical line partitions" , 12, 21, NIL_IMAGES },
{ "ways of associativity" , 22, 31, NIL_IMAGES }, { "ways of associativity" , 22, 31, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 36); /* max_len => */ 36);
} }
static void static void
print_4_ecx(unsigned int value) print_4_ecx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "number of sets - 1" , 0, 31, NIL_IMAGES }, = { { "number of sets - 1" , 0, 31, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 36); /* max_len => */ 36);
} }
static void static void
print_4_edx(unsigned int value) print_4_edx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "WBINVD/INVD behavior on lower caches" , 0, 0, bools }, = { { "WBINVD/INVD acts on lower caches" , 0, 0, bools },
{ "inclusive to lower caches" , 1, 1, bools }, { "inclusive to lower caches" , 1, 1, bools },
{ "complex cache indexing" , 2, 2, bools }, { "complex cache indexing" , 2, 2, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 36); /* max_len => */ 36);
} }
static void static void
print_5_eax(unsigned int value) print_5_eax(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "smallest monitor-line size (bytes)" , 0, 15, NIL_IMAGES }, = { { "smallest monitor-line size (bytes)" , 0, 15, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 40); /* max_len => */ 40);
} }
static void static void
print_5_ebx(unsigned int value) print_5_ebx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "largest monitor-line size (bytes)" , 0, 15, NIL_IMAGES }, = { { "largest monitor-line size (bytes)" , 0, 15, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 40); /* max_len => */ 40);
} }
static void static void
print_5_ecx(unsigned int value) print_5_ecx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "enum of Monitor-MWAIT exts supported" , 0, 0, bools }, = { { "enum of Monitor-MWAIT exts supported" , 0, 0, bools },
{ "supports intrs as break-event for MWAIT" , 1, 1, bools }, { "supports intrs as break-event for MWAIT" , 1, 1, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 40); /* max_len => */ 40);
} }
static void static void
print_5_edx(unsigned int value) print_5_edx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "number of C0 sub C-states using MWAIT" , 0, 3, NIL_IMAGES }, = { { "number of C0 sub C-states using MWAIT" , 0, 3, NIL_IMAGES },
{ "number of C1 sub C-states using MWAIT" , 4, 7, NIL_IMAGES }, { "number of C1 sub C-states using MWAIT" , 4, 7, NIL_IMAGES },
{ "number of C2 sub C-states using MWAIT" , 8, 11, NIL_IMAGES }, { "number of C2 sub C-states using MWAIT" , 8, 11, NIL_IMAGES },
{ "number of C3 sub C-states using MWAIT" , 12, 15, NIL_IMAGES }, { "number of C3 sub C-states using MWAIT" , 12, 15, NIL_IMAGES },
{ "number of C4 sub C-states using MWAIT" , 16, 19, NIL_IMAGES }, { "number of C4 sub C-states using MWAIT" , 16, 19, NIL_IMAGES },
{ "number of C5 sub C-states using MWAIT" , 20, 23, NIL_IMAGES }, { "number of C5 sub C-states using MWAIT" , 20, 23, NIL_IMAGES },
{ "number of C6 sub C-states using MWAIT" , 24, 27, NIL_IMAGES }, { "number of C6 sub C-states using MWAIT" , 24, 27, NIL_IMAGES },
{ "number of C7 sub C-states using MWAIT" , 28, 31, NIL_IMAGES }, { "number of C7 sub C-states using MWAIT" , 28, 31, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 40); /* max_len => */ 40);
} }
static void static void
print_6_eax(unsigned int value) print_6_eax(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "digital thermometer" , 0, 0, bools }, = { { "digital thermometer" , 0, 0, bools },
{ "Intel Turbo Boost Technology" , 1, 1, bools }, { "Intel Turbo Boost Technology" , 1, 1, bools },
{ "ARAT always running APIC timer" , 2, 2, bools }, { "ARAT always running APIC timer" , 2, 2, bools },
skipping to change at line 4140 skipping to change at line 4331
{ "HWP package level request" , 11, 11, bools }, { "HWP package level request" , 11, 11, bools },
{ "HDC base registers" , 13, 13, bools }, { "HDC base registers" , 13, 13, bools },
{ "Intel Turbo Boost Max Technology 3.0" , 14, 14, bools }, { "Intel Turbo Boost Max Technology 3.0" , 14, 14, bools },
{ "HWP capabilities" , 15, 15, bools }, { "HWP capabilities" , 15, 15, bools },
{ "HWP PECI override" , 16, 16, bools }, { "HWP PECI override" , 16, 16, bools },
{ "flexible HWP" , 17, 17, bools }, { "flexible HWP" , 17, 17, bools },
{ "IA32_HWP_REQUEST MSR fast access mode" , 18, 18, bools }, { "IA32_HWP_REQUEST MSR fast access mode" , 18, 18, bools },
{ "ignoring idle logical processor HWP req" , 20, 20, bools }, { "ignoring idle logical processor HWP req" , 20, 20, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 39); /* max_len => */ 39);
} }
static void static void
print_6_ebx(unsigned int value) print_6_ebx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "digital thermometer thresholds" , 0, 3, NIL_IMAGES }, = { { "digital thermometer thresholds" , 0, 3, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 39); /* max_len => */ 39);
} }
static void static void
print_6_ecx(unsigned int value) print_6_ecx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "hardware coordination feedback" , 0, 0, bools }, = { { "hardware coordination feedback" , 0, 0, bools },
{ "ACNT2 available" , 1, 1, bools }, { "ACNT2 available" , 1, 1, bools },
{ "performance-energy bias capability" , 3, 3, bools }, { "performance-energy bias capability" , 3, 3, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 39); /* max_len => */ 39);
} }
static void static void
print_7_ebx(unsigned int value) print_7_ebx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "FSGSBASE instructions" , 0, 0, bools }, = { { "FSGSBASE instructions" , 0, 0, bools },
{ "IA32_TSC_ADJUST MSR supported" , 1, 1, bools }, { "IA32_TSC_ADJUST MSR supported" , 1, 1, bools },
{ "SGX: Software Guard Extensions supported", 2, 2, bools }, { "SGX: Software Guard Extensions supported", 2, 2, bools },
skipping to change at line 4206 skipping to change at line 4397
{ "CLWB instruction" , 24, 24, bools }, { "CLWB instruction" , 24, 24, bools },
{ "Intel processor trace" , 25, 25, bools }, { "Intel processor trace" , 25, 25, bools },
{ "AVX512PF: prefetch instructions" , 26, 26, bools }, { "AVX512PF: prefetch instructions" , 26, 26, bools },
{ "AVX512ER: exponent & reciprocal instrs" , 27, 27, bools }, { "AVX512ER: exponent & reciprocal instrs" , 27, 27, bools },
{ "AVX512CD: conflict detection instrs" , 28, 28, bools }, { "AVX512CD: conflict detection instrs" , 28, 28, bools },
{ "SHA instructions" , 29, 29, bools }, { "SHA instructions" , 29, 29, bools },
{ "AVX512BW: byte & word instructions" , 30, 30, bools }, { "AVX512BW: byte & word instructions" , 30, 30, bools },
{ "AVX512VL: vector length" , 31, 31, bools }, { "AVX512VL: vector length" , 31, 31, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 40); /* max_len => */ 40);
} }
static void static void
print_7_ecx(unsigned int value) print_7_ecx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "PREFETCHWT1" , 0, 0, bools }, = { { "PREFETCHWT1" , 0, 0, bools },
{ "AVX512VBMI: vector byte manipulation" , 1, 1, bools }, { "AVX512VBMI: vector byte manipulation" , 1, 1, bools },
{ "UMIP: user-mode instruction prevention" , 2, 2, bools }, { "UMIP: user-mode instruction prevention" , 2, 2, bools },
skipping to change at line 4233 skipping to change at line 4424
{ "VAES instructions" , 9, 9, bools }, { "VAES instructions" , 9, 9, bools },
{ "VPCLMULQDQ instruction" , 10, 10, bools }, { "VPCLMULQDQ instruction" , 10, 10, bools },
{ "AVX512_VNNI" , 11, 11, bools }, { "AVX512_VNNI" , 11, 11, bools },
{ "AVX512_BITALG: bit count/shiffle" , 12, 12, bools }, { "AVX512_BITALG: bit count/shiffle" , 12, 12, bools },
{ "AVX512: VPOPCNTDQ instruction" , 14, 14, bools }, { "AVX512: VPOPCNTDQ instruction" , 14, 14, bools },
{ "5-level paging" , 16, 16, bools }, { "5-level paging" , 16, 16, bools },
{ "BNDLDX/BNDSTX MAWAU value in 64-bit mode", 17, 21, NIL_IMAGES }, { "BNDLDX/BNDSTX MAWAU value in 64-bit mode", 17, 21, NIL_IMAGES },
{ "RDPID: read processor D supported" , 22, 22, bools }, { "RDPID: read processor D supported" , 22, 22, bools },
{ "CLDEMOTE supports cache line demote" , 25, 25, bools }, { "CLDEMOTE supports cache line demote" , 25, 25, bools },
{ "MOVDIRI instruction" , 27, 27, bools }, { "MOVDIRI instruction" , 27, 27, bools },
{ "MOVDIR64B intruction" , 28, 28, bools }, { "MOVDIR64B instruction" , 28, 28, bools },
{ "SGX_LC: SGX launch config supported" , 30, 30, bools }, { "SGX_LC: SGX launch config supported" , 30, 30, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 40); /* max_len => */ 40);
} }
static void static void
print_7_edx(unsigned int value) print_7_edx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "AVX512_4VNNIW: neural network instrs" , 2, 2, bools }, = { { "AVX512_4VNNIW: neural network instrs" , 2, 2, bools },
{ "AVX512_4FMAPS: multiply acc single prec" , 3, 3, bools }, { "AVX512_4FMAPS: multiply acc single prec" , 3, 3, bools },
{ "fast short REP MOV" , 4, 4, bools }, { "fast short REP MOV" , 4, 4, bools },
{ "hybrid part" , 15, 15, bools },
{ "PCONFIG" , 18, 18, bools }, { "PCONFIG" , 18, 18, bools },
{ "CET_IBT: CET indirect branch tracking" , 20, 20, bools }, { "CET_IBT: CET indirect branch tracking" , 20, 20, bools },
{ "IBRS/IBPB: indirect branch restrictions" , 26, 26, bools },
{ "STIBP: 1 thr indirect branch predictor" , 27, 27, bools },
{ "L1D_FLUSH: IA32_FLUSH_CMD MSR" , 28, 28, bools },
{ "IA32_ARCH_CAPABILITIES MSR" , 29, 29, bools },
{ "IA32_CORE_CAPABILITIES MSR" , 30, 30, bools },
{ "SSBD: speculative store bypass disable" , 31, 31, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 40); /* max_len => */ 40);
} }
static void static void
print_a_eax(unsigned int value) print_a_eax(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "version ID" , 0, 7, NIL_IMAGES }, = { { "version ID" , 0, 7, NIL_IMAGES },
{ "number of counters per logical processor", 8, 15, NIL_IMAGES }, { "number of counters per logical processor", 8, 15, NIL_IMAGES },
{ "bit width of counter" , 16, 23, NIL_IMAGES }, { "bit width of counter" , 16, 23, NIL_IMAGES },
{ "length of EBX bit vector" , 24, 31, NIL_IMAGES }, { "length of EBX bit vector" , 24, 31, NIL_IMAGES },
}; };
printf(" Architecture Performance Monitoring Features (0xa/eax):\n"); printf(" Architecture Performance Monitoring Features (0xa/eax):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_a_ebx(unsigned int value) print_a_ebx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "core cycle event not available" , 0, 0, bools }, = { { "core cycle event not available" , 0, 0, bools },
{ "instruction retired event not available" , 1, 1, bools }, { "instruction retired event not available" , 1, 1, bools },
{ "reference cycles event not available" , 2, 2, bools }, { "reference cycles event not available" , 2, 2, bools },
{ "last-level cache ref event not available", 3, 3, bools }, { "last-level cache ref event not available", 3, 3, bools },
{ "last-level cache miss event not avail" , 4, 4, bools }, { "last-level cache miss event not avail" , 4, 4, bools },
{ "branch inst retired event not available" , 5, 5, bools }, { "branch inst retired event not available" , 5, 5, bools },
{ "branch mispred retired event not avail" , 6, 6, bools }, { "branch mispred retired event not avail" , 6, 6, bools },
}; };
printf(" Architecture Performance Monitoring Features (0xa/ebx):\n"); printf(" Architecture Performance Monitoring Features (0xa/ebx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_a_edx(unsigned int value) print_a_edx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "number of fixed counters" , 0, 4, NIL_IMAGES }, = { { "number of fixed counters" , 0, 4, NIL_IMAGES },
{ "bit width of fixed counters" , 5, 12, NIL_IMAGES }, { "bit width of fixed counters" , 5, 12, NIL_IMAGES },
{ "anythread deprecation" , 15, 15, bools }, { "anythread deprecation" , 15, 15, bools },
}; };
printf(" Architecture Performance Monitoring Features (0xa/edx):\n"); printf(" Architecture Performance Monitoring Features (0xa/edx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_b_eax(unsigned int value) print_b_eax(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "bits to shift APIC ID to get next" , 0, 4, NIL_IMAGES }, = { { "bits to shift APIC ID to get next" , 0, 4, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 33); /* max_len => */ 33);
} }
static void static void
print_b_ebx(unsigned int value) print_b_ebx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "logical processors at this level" , 0, 15, NIL_IMAGES }, = { { "logical processors at this level" , 0, 15, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 33); /* max_len => */ 33);
} }
static void static void
print_b_ecx(unsigned int value) print_b_ecx(unsigned int value)
{ {
static ccstring level_type[] = { "invalid (0)", static ccstring level_type[1<<8] = { "invalid (0)",
"thread (1)", "thread (1)",
"core (2)" }; "core (2)" };
static named_item names[] static named_item names[]
= { { "level number" , 0, 7, NIL_IMAGES }, = { { "level number" , 0, 7, NIL_IMAGES },
{ "level type" , 8, 15, level_type }, { "level type" , 8, 15, level_type },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 33); /* max_len => */ 33);
} }
static void static void
print_d_0_eax(unsigned int value) print_d_0_eax(unsigned int value)
{ {
/* /*
** State component bitmaps in general are described in 325462: Intel 64 and ** State component bitmaps in general are described in 325462: Intel 64 and
** IA-32 Architectures Software Developer's Manual Combined Volumes: 1, 2A, ** IA-32 Architectures Software Developer's Manual Combined Volumes: 1, 2A,
** 2B, 2C, 3A, 3B, and 3C, Volume 1: Basic Architecture, section 13.1: ** 2B, 2C, 3A, 3B, and 3C, Volume 1: Basic Architecture, section 13.1:
skipping to change at line 4367 skipping to change at line 4565
{ " XCR0 supported: MPX BNDREGS" , 3, 3, bools }, { " XCR0 supported: MPX BNDREGS" , 3, 3, bools },
{ " XCR0 supported: MPX BNDCSR" , 4, 4, bools }, { " XCR0 supported: MPX BNDCSR" , 4, 4, bools },
{ " XCR0 supported: AVX-512 opmask" , 5, 5, bools }, { " XCR0 supported: AVX-512 opmask" , 5, 5, bools },
{ " XCR0 supported: AVX-512 ZMM_Hi256" , 6, 6, bools }, { " XCR0 supported: AVX-512 ZMM_Hi256" , 6, 6, bools },
{ " XCR0 supported: AVX-512 Hi16_ZMM" , 7, 7, bools }, { " XCR0 supported: AVX-512 Hi16_ZMM" , 7, 7, bools },
{ " IA32_XSS supported: PT state" , 8, 8, bools }, { " IA32_XSS supported: PT state" , 8, 8, bools },
{ " XCR0 supported: PKRU state" , 9, 9, bools }, { " XCR0 supported: PKRU state" , 9, 9, bools },
{ " IA32_XSS supported: HDC state" , 13, 13, bools }, { " IA32_XSS supported: HDC state" , 13, 13, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 39); /* max_len => */ 39);
} }
static void static void
print_d_1_eax(unsigned int value) print_d_1_eax(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "XSAVEOPT instruction" , 0, 0, bools }, = { { "XSAVEOPT instruction" , 0, 0, bools },
{ "XSAVEC instruction" , 1, 1, bools }, { "XSAVEC instruction" , 1, 1, bools },
{ "XGETBV instruction" , 2, 2, bools }, { "XGETBV instruction" , 2, 2, bools },
{ "XSAVES/XRSTORS instructions" , 3, 3, bools }, { "XSAVES/XRSTORS instructions" , 3, 3, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 43); /* max_len => */ 43);
} }
static void static void
print_d_n_ecx(unsigned int value) print_d_n_ecx(unsigned int value)
{ {
static ccstring which[] = { "XCR0 (user state)", static ccstring which[] = { "XCR0 (user state)",
"IA32_XSS (supervisor state)" }; "IA32_XSS (supervisor state)" };
static named_item names[] static named_item names[]
= { { "supported in IA32_XSS or XCR0" , 0, 0, which }, = { { "supported in IA32_XSS or XCR0" , 0, 0, which },
{ "64-byte alignment in compacted XSAVE" , 1, 1, bools }, { "64-byte alignment in compacted XSAVE" , 1, 1, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 40); /* max_len => */ 40);
} }
static void static void
print_d_n(const unsigned int words[WORD_NUM], print_d_n(const unsigned int words[WORD_NUM],
unsigned int try) unsigned int try)
{ {
/* /*
** The XSAVE areas are explained in 325462: Intel 64 and IA-32 Architectures ** The XSAVE areas are explained in 325462: Intel 64 and IA-32 Architectures
** Software Developer's Manual Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B, and ** Software Developer's Manual Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B, and
skipping to change at line 4499 skipping to change at line 4697
printf(" %s save state byte offset%*s = 0x%08x (%u)\n", printf(" %s save state byte offset%*s = 0x%08x (%u)\n",
feature, feature_pad, "", feature, feature_pad, "",
words[WORD_EBX], words[WORD_EBX]); words[WORD_EBX], words[WORD_EBX]);
print_d_n_ecx(words[WORD_ECX]); print_d_n_ecx(words[WORD_ECX]);
} }
static void static void
print_f_0_edx(unsigned int value) print_f_0_edx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "supports L3 cache QoS monitoring" , 0, 0, bools }, = { { "supports L3 cache QoS monitoring" , 1, 1, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_f_1_edx(unsigned int value) print_f_1_edx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "supports L3 occupancy monitoring" , 0, 0, bools }, = { { "supports L3 occupancy monitoring" , 0, 0, bools },
{ "supports L3 total bandwidth monitoring" , 1, 1, bools }, { "supports L3 total bandwidth monitoring" , 1, 1, bools },
{ "supports L3 local bandwidth monitoring" , 2, 2, bools }, { "supports L3 local bandwidth monitoring" , 2, 2, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_10_0_ebx(unsigned int value) print_10_0_ebx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "L3 cache allocation technology supported", 1, 1, bools }, = { { "L3 cache allocation technology supported", 1, 1, bools },
{ "L2 cache allocation technology supported", 2, 2, bools }, { "L2 cache allocation technology supported", 2, 2, bools },
{ "memory bandwidth allocation supported" , 3, 3, bools }, { "memory bandwidth allocation supported" , 3, 3, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_10_n_eax(unsigned int value) print_10_n_eax(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "length of capacity bit mask - 1" , 0, 4, NIL_IMAGES }, = { { "length of capacity bit mask - 1" , 0, 4, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 40);
} }
static void static void
print_10_n_ecx(unsigned int value) print_10_n_ecx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "infrequent updates of COS" , 1, 1, bools }, = { { "infrequent updates of COS" , 1, 1, bools },
{ "code and data prioritization supported" , 2, 2, bools }, { "code and data prioritization supported" , 2, 2, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 40);
} }
static void static void
print_10_n_edx(unsigned int value) print_10_n_edx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "highest COS number supported" , 0, 15, NIL_IMAGES }, = { { "highest COS number supported" , 0, 15, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 40);
}
static void
print_10_3_eax(unsigned int value)
{
static named_item names[]
= { { "maximum throttling value - 1" , 0, 11, NIL_IMAGES },
};
print_names(value, names, LENGTH(names),
/* max_len => */ 40);
}
static void
print_10_3_ecx(unsigned int value)
{
static named_item names[]
= { { "delay values are linear" , 2, 2, bools },
};
print_names(value, names, LENGTH(names),
/* max_len => */ 40);
} }
static void static void
print_12_0_eax(unsigned int value) print_12_0_eax(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "SGX1 supported" , 0, 0, bools }, = { { "SGX1 supported" , 0, 0, bools },
{ "SGX2 supported" , 1, 1, bools }, { "SGX2 supported" , 1, 1, bools },
{ "SGX ENCLV E*VIRTCHILD, ESETCONTEXT" , 5, 5, bools }, { "SGX ENCLV E*VIRTCHILD, ESETCONTEXT" , 5, 5, bools },
{ "SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC", 6, 6, bools }, { "SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC", 6, 6, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 38); /* max_len => */ 38);
} }
static void static void
print_12_0_ebx(unsigned int value) print_12_0_ebx(unsigned int value)
{ {
/* /*
** MISCSELECT is described in Table 38-4: Bit Vector Layout of MISCSELECT ** MISCSELECT is described in Table 38-4: Bit Vector Layout of MISCSELECT
** Field of Extended Information. ** Field of Extended Information.
*/ */
static named_item names[] static named_item names[]
= { { "MISCSELECT.EXINFO supported: #PF & #GP" , 0, 0, bools }, = { { "MISCSELECT.EXINFO supported: #PF & #GP" , 0, 0, bools },
{ "MISCSELECT.CPINFO supported: #CP" , 1, 1, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 38); /* max_len => */ 38);
} }
static void static void
print_12_0_edx(unsigned int value) print_12_0_edx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "MaxEnclaveSize_Not64 (log2)" , 0, 7, NIL_IMAGES }, = { { "MaxEnclaveSize_Not64 (log2)" , 0, 7, NIL_IMAGES },
{ "MaxEnclaveSize_64 (log2)" , 8, 15, NIL_IMAGES }, { "MaxEnclaveSize_64 (log2)" , 8, 15, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 38); /* max_len => */ 38);
} }
static void static void
print_12_n_1_ecx(unsigned int value) print_12_n_ecx(unsigned int value)
{ {
static ccstring props[16] = { /* 0 => */ "enumerated as 0", static ccstring props[1<<4] = { /* 0 => */ "enumerated as 0",
/* 1 => */ "confidentiality & integrity" /* 1 => */ "confidentiality & integrity"
" protection" }; " protection" };
static named_item names[] static named_item names[]
= { { "section property" , 0, 3, props }, = { { "section property" , 0, 3, props },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 23); /* max_len => */ 23);
} }
static void static void
print_14_0_ebx(unsigned int value) print_14_0_ebx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "IA32_RTIT_CR3_MATCH is accessible" , 0, 0, bools }, = { { "IA32_RTIT_CR3_MATCH is accessible" , 0, 0, bools },
{ "configurable PSB & cycle-accurate" , 1, 1, bools }, { "configurable PSB & cycle-accurate" , 1, 1, bools },
{ "IP & TraceStop filtering; PT preserve" , 2, 2, bools }, { "IP & TraceStop filtering; PT preserve" , 2, 2, bools },
{ "MTC timing packet; suppress COFI-based" , 3, 3, bools }, { "MTC timing packet; suppress COFI-based" , 3, 3, bools },
{ "PTWRITE support" , 4, 4, bools }, { "PTWRITE support" , 4, 4, bools },
{ "power event trace support" , 5, 5, bools }, { "power event trace support" , 5, 5, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_14_0_ecx(unsigned int value) print_14_0_ecx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "ToPA output scheme support" , 0, 0, bools }, = { { "ToPA output scheme support" , 0, 0, bools },
{ "ToPA can hold many output entries" , 1, 1, bools }, { "ToPA can hold many output entries" , 1, 1, bools },
{ "single-range output scheme support" , 2, 2, bools }, { "single-range output scheme support" , 2, 2, bools },
{ "output to trace transport" , 3, 3, bools }, { "output to trace transport" , 3, 3, bools },
{ "IP payloads have LIP values & CS" , 31, 31, bools }, { "IP payloads have LIP values & CS" , 31, 31, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_14_1_eax(unsigned int value) print_14_1_eax(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "configurable address ranges" , 0, 2, NIL_IMAGES }, = { { "configurable address ranges" , 0, 2, NIL_IMAGES },
{ "supported MTC periods bitmask" , 16, 31, NIL_IMAGES }, { "supported MTC periods bitmask" , 16, 31, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_14_1_ebx(unsigned int value) print_14_1_ebx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "supported cycle threshold bitmask" , 0, 15, NIL_IMAGES }, = { { "supported cycle threshold bitmask" , 0, 15, NIL_IMAGES },
{ "supported config PSB freq bitmask" , 16, 31, NIL_IMAGES }, { "supported config PSB freq bitmask" , 16, 31, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_16_eax(unsigned int value) print_16_eax(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "Core Base Frequency (MHz)" , 0, 15, NIL_IMAGES }, = { { "Core Base Frequency (MHz)" , 0, 15, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_16_ebx(unsigned int value) print_16_ebx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "Core Maximum Frequency (MHz)" , 0, 15, NIL_IMAGES }, = { { "Core Maximum Frequency (MHz)" , 0, 15, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_16_ecx(unsigned int value) print_16_ecx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "Bus (Reference) Frequency (MHz)" , 0, 15, NIL_IMAGES }, = { { "Bus (Reference) Frequency (MHz)" , 0, 15, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_17_0_ebx(unsigned int value) print_17_0_ebx(unsigned int value)
{ {
static ccstring schemes[] = { /* 0 => */ "assigned by intel", static ccstring schemes[] = { /* 0 => */ "assigned by intel",
/* 1 => */ "industry standard" }; /* 1 => */ "industry standard" };
static named_item names[] static named_item names[]
= { { "vendor id" , 0, 15, NIL_IMAGES }, = { { "vendor id" , 0, 15, NIL_IMAGES },
{ "vendor scheme" , 16, 16, schemes }, { "vendor scheme" , 16, 16, schemes },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_18_n_ebx(unsigned int value) print_18_n_ebx(unsigned int value)
{ {
static ccstring parts[] = { /* 0 => */ "soft between logical processors", static ccstring parts[] = { /* 0 => */ "soft between logical processors",
/* 1 => */ NULL, /* 1 => */ NULL,
/* 2 => */ NULL, /* 2 => */ NULL,
/* 3 => */ NULL, /* 3 => */ NULL,
skipping to change at line 4746 skipping to change at line 4967
static named_item names[] static named_item names[]
= { { "4KB page size entries supported" , 0, 0, bools }, = { { "4KB page size entries supported" , 0, 0, bools },
{ "2MB page size entries supported" , 1, 1, bools }, { "2MB page size entries supported" , 1, 1, bools },
{ "4MB page size entries supported" , 2, 2, bools }, { "4MB page size entries supported" , 2, 2, bools },
{ "1GB page size entries supported" , 3, 3, bools }, { "1GB page size entries supported" , 3, 3, bools },
{ "partitioning" , 8, 10, parts }, { "partitioning" , 8, 10, parts },
{ "ways of associativity" , 16, 31, NIL_IMAGES }, { "ways of associativity" , 16, 31, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_18_n_edx(unsigned int value) print_18_n_edx(unsigned int value)
{ {
static ccstring tlbs[16] = { /* 0000b => */ "invalid (0)", static ccstring tlbs[1<<5] = { /* 00000b => */ "invalid (0)",
/* 0001b => */ "data TLB", /* 00001b => */ "data TLB",
/* 0010b => */ "instruction TLB", /* 00010b => */ "instruction TLB",
/* 0011b => */ "unified TLB", }; /* 00011b => */ "unified TLB", };
static named_item names[] static named_item names[]
= { { "translation cache type" , 0, 4, tlbs }, = { { "translation cache type" , 0, 4, tlbs },
{ "translation cache level - 1" , 5, 7, NIL_IMAGES }, { "translation cache level - 1" , 5, 7, NIL_IMAGES },
{ "fully associative" , 8, 8, bools }, { "fully associative" , 8, 8, bools },
{ "maximum number of addressible IDs" , 14, 25, NIL_IMAGES }, { "maximum number of addressible IDs" , 14, 25, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0);
}
static void
print_1a_0_eax(unsigned int value)
{
static ccstring coretypes[1<<8] = { /* 00h-0fh => */ NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
/* 10h-1fh => */ NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
/* 20h => */ "Intel Atom",
/* 21h-2fh => */ NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
/* 30h-3fh => */ NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
/* 40h => */ "Intel Core" };
static named_item names[]
= { { "native model ID of core" , 0, 23, NIL_IMAGES },
{ "core type" , 24, 31, coretypes },
};
print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_1b_n_eax(unsigned int value) print_1b_n_eax(unsigned int value)
{ {
static ccstring types[1<<12] = { /* 0 => */ "invalid (0)", static ccstring types[1<<12] = { /* 0 => */ "invalid (0)",
/* 1 => */ "target identifier (1)" }; /* 1 => */ "target identifier (1)" };
static named_item names[] static named_item names[]
= { { "sub-leaf type" , 0, 11, types }, = { { "sub-leaf type" , 0, 11, types },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_1f_ecx(unsigned int value)
{
static ccstring levels[1<<8] = { /* 0 => */ "invalid (0)",
/* 1 => */ "SMT (1)",
/* 2 => */ "core (2)",
/* 3 => */ "module (3)",
/* 4 => */ "tile (4)",
/* 5 => */ "die (5)" };
static named_item names[]
= { { "level number" , 0, 7, NIL_IMAGES },
{ "level type" , 8, 15, levels },
};
print_names(value, names, LENGTH(names),
/* max_len => */ 37);
}
static void
print_1f_eax(unsigned int value)
{
static named_item names[]
= { { "bit width of level" , 0, 4, NIL_IMAGES },
};
print_names(value, names, LENGTH(names),
/* max_len => */ 37);
}
static void
print_1f_ebx(unsigned int value)
{
static named_item names[]
= { { "number of logical processors at level" , 0, 4, NIL_IMAGES },
};
print_names(value, names, LENGTH(names),
/* max_len => */ 37);
}
static void
print_40000001_eax_kvm(unsigned int value) print_40000001_eax_kvm(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "kvmclock available at MSR 0x11" , 0, 0, bools }, = { { "kvmclock available at MSR 0x11" , 0, 0, bools },
{ "delays unnecessary for PIO ops" , 1, 1, bools }, { "delays unnecessary for PIO ops" , 1, 1, bools },
{ "mmu_op" , 2, 2, bools }, { "mmu_op" , 2, 2, bools },
{ "kvmclock available a MSR 0x4b564d00" , 3, 3, bools }, { "kvmclock available a MSR 0x4b564d00" , 3, 3, bools },
{ "async pf enable available by MSR" , 4, 4, bools }, { "async pf enable available by MSR" , 4, 4, bools },
{ "steal clock supported" , 5, 5, bools }, { "steal clock supported" , 5, 5, bools },
{ "guest EOI optimization enabled" , 6, 6, bools }, { "guest EOI optimization enabled" , 6, 6, bools },
{ "guest spinlock optimization enabled" , 7, 7, bools },
{ "guest TLB flush optimization enabled" , 9, 9, bools },
{ "async PF VM exit enable available by MSR", 10, 10, bools },
{ "guest send IPI optimization enabled" , 11, 11, bools },
{ "stable: no guest per-cpu warps expected" , 24, 24, bools }, { "stable: no guest per-cpu warps expected" , 24, 24, bools },
}; };
printf(" hypervisor features (0x40000001/eax):\n"); printf(" hypervisor features (0x40000001/eax):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0);
}
static void
print_40000001_edx_kvm(unsigned int value)
{
static named_item names[]
= { { "realtime hint: no unbound preemption" , 0, 0, bools },
};
printf(" hypervisor features (0x40000001/edx):\n");
print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_40000002_ecx_xen(unsigned int value) print_40000002_ecx_xen(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "MMU_PT_UPDATE_PRESERVE_AD supported" , 0, 0, bools }, = { { "MMU_PT_UPDATE_PRESERVE_AD supported" , 0, 0, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_40000003_eax_xen(unsigned int value) print_40000003_eax_xen(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "vtsc" , 0, 0, bools }, = { { "vtsc" , 0, 0, bools },
{ "host tsc is safe" , 1, 1, bools }, { "host tsc is safe" , 1, 1, bools },
{ "boot cpu has RDTSCP" , 2, 2, bools }, { "boot cpu has RDTSCP" , 2, 2, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_40000003_eax_microsoft(unsigned int value) print_40000003_eax_microsoft(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "VP run time" , 0, 0, bools }, = { { "VP run time" , 0, 0, bools },
{ "partition reference counter" , 1, 1, bools }, { "partition reference counter" , 1, 1, bools },
{ "basic synIC MSRs" , 2, 2, bools }, { "basic synIC MSRs" , 2, 2, bools },
skipping to change at line 4846 skipping to change at line 5155
{ "access virtual process index MSR" , 6, 6, bools }, { "access virtual process index MSR" , 6, 6, bools },
{ "virtual system reset MSR" , 7, 7, bools }, { "virtual system reset MSR" , 7, 7, bools },
{ "map/unmap statistics pages MSR" , 8, 8, bools }, { "map/unmap statistics pages MSR" , 8, 8, bools },
{ "reference TSC access" , 9, 9, bools }, { "reference TSC access" , 9, 9, bools },
{ "guest idle state MSR" , 10, 10, bools }, { "guest idle state MSR" , 10, 10, bools },
{ "TSC/APIC frequency MSRs" , 11, 11, bools }, { "TSC/APIC frequency MSRs" , 11, 11, bools },
{ "guest debugging MSRs" , 12, 12, bools }, { "guest debugging MSRs" , 12, 12, bools },
}; };
printf(" hypervisor feature identification (0x40000003/eax):\n"); printf(" hypervisor feature identification (0x40000003/eax):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_40000003_ebx_microsoft(unsigned int value) print_40000003_ebx_microsoft(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "CreatePartitions" , 0, 0, bools }, = { { "CreatePartitions" , 0, 0, bools },
{ "AccessPartitionId" , 1, 1, bools }, { "AccessPartitionId" , 1, 1, bools },
{ "AccessMemoryPool" , 2, 2, bools }, { "AccessMemoryPool" , 2, 2, bools },
skipping to change at line 4873 skipping to change at line 5182
{ "Debugging" , 11, 11, bools }, { "Debugging" , 11, 11, bools },
{ "CPUManagement" , 12, 12, bools }, { "CPUManagement" , 12, 12, bools },
{ "ConfigureProfiler" , 13, 13, bools }, { "ConfigureProfiler" , 13, 13, bools },
{ "AccessVSM" , 16, 16, bools }, { "AccessVSM" , 16, 16, bools },
{ "AccessVpRegisters" , 17, 17, bools }, { "AccessVpRegisters" , 17, 17, bools },
{ "EnableExtendedHypercalls" , 20, 20, bools }, { "EnableExtendedHypercalls" , 20, 20, bools },
{ "StartVirtualProcessor" , 21, 21, bools }, { "StartVirtualProcessor" , 21, 21, bools },
}; };
printf(" hypervisor partition creation flags (0x40000003/ebx):\n"); printf(" hypervisor partition creation flags (0x40000003/ebx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_40000003_ecx_microsoft(unsigned int value) print_40000003_ecx_microsoft(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "maximum process power state" , 0, 3, NIL_IMAGES }, = { { "maximum process power state" , 0, 3, NIL_IMAGES },
}; };
printf(" hypervisor power management features (0x40000003/ecx):\n"); printf(" hypervisor power management features (0x40000003/ecx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_40000003_edx_microsoft(unsigned int value) print_40000003_edx_microsoft(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "MWAIT available" , 0, 0, bools }, = { { "MWAIT available" , 0, 0, bools },
{ "guest debugging support available" , 1, 1, bools }, { "guest debugging support available" , 1, 1, bools },
{ "performance monitor support available" , 2, 2, bools }, { "performance monitor support available" , 2, 2, bools },
skipping to change at line 4915 skipping to change at line 5224
{ "NPIEP available" , 12, 12, bools }, { "NPIEP available" , 12, 12, bools },
{ "disable hypervisor available" , 13, 13, bools }, { "disable hypervisor available" , 13, 13, bools },
{ "extended gva ranges for flush virt addrs", 14, 14, bools }, { "extended gva ranges for flush virt addrs", 14, 14, bools },
{ "hypercall XMM register return available" , 15, 15, bools }, { "hypercall XMM register return available" , 15, 15, bools },
{ "sint polling mode available" , 17, 17, bools }, { "sint polling mode available" , 17, 17, bools },
{ "hypercall MSR lock available" , 18, 18, bools }, { "hypercall MSR lock available" , 18, 18, bools },
{ "use direct synthetic timers" , 19, 19, bools }, { "use direct synthetic timers" , 19, 19, bools },
}; };
printf(" hypervisor feature identification (0x40000003/edx):\n"); printf(" hypervisor feature identification (0x40000003/edx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_40000004_eax_xen(unsigned int value)
{
static named_item names[]
= { { "virtualized APIC registers" , 0, 0, bools },
{ "virtualized x2APIC accesses" , 1, 1, bools },
{ "IOMMU mappings for other domain memory" , 2, 2, bools },
{ "vcpu id is valid" , 3, 3, bools },
{ "domain id is valid" , 4, 4, bools },
};
printf(" HVM-specific parameters (0x40000004):\n");
print_names(value, names, LENGTH(names),
/* max_len => */ 38);
}
static void
print_40000004_eax_microsoft(unsigned int value) print_40000004_eax_microsoft(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "use hypercalls for AS switches" , 0, 0, bools }, = { { "use hypercalls for AS switches" , 0, 0, bools },
{ "use hypercalls for local TLB flushes" , 1, 1, bools }, { "use hypercalls for local TLB flushes" , 1, 1, bools },
{ "use hypercalls for remote TLB flushes" , 2, 2, bools }, { "use hypercalls for remote TLB flushes" , 2, 2, bools },
{ "use MSRs to access EOI, ICR, TPR" , 3, 3, bools }, { "use MSRs to access EOI, ICR, TPR" , 3, 3, bools },
{ "use MSRs to initiate system RESET" , 4, 4, bools }, { "use MSRs to initiate system RESET" , 4, 4, bools },
{ "use relaxed timing" , 5, 5, bools }, { "use relaxed timing" , 5, 5, bools },
{ "use DMA remapping" , 6, 6, bools }, { "use DMA remapping" , 6, 6, bools },
skipping to change at line 4941 skipping to change at line 5266
{ "use x2APIC MSRs" , 8, 8, bools }, { "use x2APIC MSRs" , 8, 8, bools },
{ "deprecate AutoEOI" , 9, 9, bools }, { "deprecate AutoEOI" , 9, 9, bools },
{ "use SyntheticClusterIpi hypercall" , 10, 10, bools }, { "use SyntheticClusterIpi hypercall" , 10, 10, bools },
{ "use ExProcessorMasks" , 11, 11, bools }, { "use ExProcessorMasks" , 11, 11, bools },
{ "hypervisor is nested with Hyper-V" , 12, 12, bools }, { "hypervisor is nested with Hyper-V" , 12, 12, bools },
{ "use INT for MBEC system calls" , 13, 13, bools }, { "use INT for MBEC system calls" , 13, 13, bools },
{ "use enlightened VMCS interface" , 14, 14, bools }, { "use enlightened VMCS interface" , 14, 14, bools },
}; };
printf(" hypervisor recommendations (0x40000004/eax):\n"); printf(" hypervisor recommendations (0x40000004/eax):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0);
}
static void
print_40000005_0_ebx_xen(unsigned int value)
{
static named_item names[]
= { { "maximum machine address width" , 0, 7, NIL_IMAGES },
};
printf(" PV-specific parameters (0x40000005):\n");
print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_40000006_eax_microsoft(unsigned int value) print_40000006_eax_microsoft(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "APIC overlay assist" , 0, 0, bools }, = { { "APIC overlay assist" , 0, 0, bools },
{ "MSR bitmaps" , 1, 1, bools }, { "MSR bitmaps" , 1, 1, bools },
{ "performance counters" , 2, 2, bools }, { "performance counters" , 2, 2, bools },
{ "second-level address translation" , 3, 3, bools }, { "second-level address translation" , 3, 3, bools },
{ "DMA remapping" , 4, 4, bools }, { "DMA remapping" , 4, 4, bools },
{ "interrupt remapping" , 5, 5, bools }, { "interrupt remapping" , 5, 5, bools },
{ "memory patrol scrubber" , 6, 6, bools }, { "memory patrol scrubber" , 6, 6, bools },
{ "DMA protection" , 7, 7, bools }, { "DMA protection" , 7, 7, bools },
{ "HPET requested" , 8, 8, bools }, { "HPET requested" , 8, 8, bools },
{ "synthetic timers are volatile" , 9, 9, bools }, { "synthetic timers are volatile" , 9, 9, bools },
}; };
printf(" hypervisor hardware features used (0x40000006/eax):\n"); printf(" hypervisor hardware features used (0x40000006/eax):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_40000007_eax_microsoft(unsigned int value) print_40000007_eax_microsoft(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "StartLogicalProcessor" , 0, 0, bools }, = { { "StartLogicalProcessor" , 0, 0, bools },
{ "CreateRootvirtualProcessor" , 1, 1, bools }, { "CreateRootvirtualProcessor" , 1, 1, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_40000007_ebx_microsoft(unsigned int value) print_40000007_ebx_microsoft(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "ProcessorPowerManagement" , 0, 0, bools }, = { { "ProcessorPowerManagement" , 0, 0, bools },
{ "MwaitIdleStates" , 1, 1, bools }, { "MwaitIdleStates" , 1, 1, bools },
{ "LogicalProcessorIdling" , 2, 2, bools }, { "LogicalProcessorIdling" , 2, 2, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_40000008_eax_microsoft(unsigned int value) print_40000008_eax_microsoft(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "SvmSupported" , 0, 0, bools }, = { { "SvmSupported" , 0, 0, bools },
{ "MaxPasidSpacePasidCount" , 11, 31, NIL_IMAGES }, { "MaxPasidSpacePasidCount" , 11, 31, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_40000009_eax_microsoft(unsigned int value) print_40000009_eax_microsoft(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "AccessSynicRegs" , 2, 2, bools }, = { { "AccessSynicRegs" , 2, 2, bools },
{ "AccessIntrCtrlRegs" , 4, 4, bools }, { "AccessIntrCtrlRegs" , 4, 4, bools },
{ "AccessHypercallMsrs" , 5, 5, bools }, { "AccessHypercallMsrs" , 5, 5, bools },
{ "AccessVpIndex" , 6, 6, bools }, { "AccessVpIndex" , 6, 6, bools },
{ "AccessReenlightenmentControls" , 12, 12, bools }, { "AccessReenlightenmentControls" , 12, 12, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_40000009_edx_microsoft(unsigned int value) print_40000009_edx_microsoft(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "XmmRegistersForFastHypercallAvailable" , 4, 4, bools }, = { { "XmmRegistersForFastHypercallAvailable" , 4, 4, bools },
{ "FastHypercallOutputAvailable" , 15, 15, bools }, { "FastHypercallOutputAvailable" , 15, 15, bools },
{ "SintPoillingModeAvailable" , 17, 17, bools }, { "SintPoillingModeAvailable" , 17, 17, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_4000000a_eax_microsoft(unsigned int value) print_4000000a_eax_microsoft(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "enlightened VMCS version (low)" , 0, 7, NIL_IMAGES }, = { { "enlightened VMCS version (low)" , 0, 7, NIL_IMAGES },
{ "enlightened VMCS version (high)" , 8, 15, NIL_IMAGES }, { "enlightened VMCS version (high)" , 8, 15, NIL_IMAGES },
{ "direct virtual flush hypercalls support" , 17, 17, bools }, { "direct virtual flush hypercalls support" , 17, 17, bools },
{ "HvFlushGuestPhysicalAddress* hypercalls" , 18, 18, bools }, { "HvFlushGuestPhysicalAddress* hypercalls" , 18, 18, bools },
{ "enlightened MSR bitmap support" , 19, 19, bools }, { "enlightened MSR bitmap support" , 19, 19, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000001_eax_amd(unsigned int value) print_80000001_eax_amd(unsigned int value)
{ {
static ccstring family[] = { NULL, static ccstring family[] = { NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
skipping to change at line 5074 skipping to change at line 5411
"AMD Athlon 64/Opteron/Sempron/Turion (15)" } ; "AMD Athlon 64/Opteron/Sempron/Turion (15)" } ;
static named_item names[] static named_item names[]
= { { "family/generation" , 8, 11, family }, = { { "family/generation" , 8, 11, family },
{ "model" , 4, 7, NIL_IMAGES }, { "model" , 4, 7, NIL_IMAGES },
{ "stepping id" , 0, 3, NIL_IMAGES }, { "stepping id" , 0, 3, NIL_IMAGES },
{ "extended family" , 20, 27, NIL_IMAGES }, { "extended family" , 20, 27, NIL_IMAGES },
{ "extended model" , 16, 19, NIL_IMAGES }, { "extended model" , 16, 19, NIL_IMAGES },
}; };
printf(" extended processor signature (0x80000001/eax):\n"); printf(" extended processor signature (0x80000001/eax):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
print_x_synth_amd(value); print_x_synth_amd(value);
} }
static void static void
print_80000001_eax_via(unsigned int value) print_80000001_eax_hygon(unsigned int value)
{ {
static ccstring family[16] = { NULL, static ccstring family[] = { NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
"VIA C3" }; NULL,
NULL,
NULL,
"Hygon Family (15)" };
static named_item names[]
= { { "family/generation" , 8, 11, family },
{ "model" , 4, 7, NIL_IMAGES },
{ "stepping id" , 0, 3, NIL_IMAGES },
{ "extended family" , 20, 27, NIL_IMAGES },
{ "extended model" , 16, 19, NIL_IMAGES },
};
printf(" extended processor signature (0x80000001/eax):\n");
print_names(value, names, LENGTH(names),
/* max_len => */ 0);
print_x_synth_hygon(value);
}
static void
print_80000001_eax_via(unsigned int value)
{
static ccstring family[1<<4] = { NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
"VIA C3" };
static named_item names[] static named_item names[]
= { { "generation" , 8, 11, family }, = { { "generation" , 8, 11, family },
{ "model" , 4, 7, NIL_IMAGES }, { "model" , 4, 7, NIL_IMAGES },
{ "stepping" , 0, 3, NIL_IMAGES }, { "stepping" , 0, 3, NIL_IMAGES },
}; };
printf(" extended processor signature (0x80000001/eax):\n"); printf(" extended processor signature (0x80000001/eax):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
print_x_synth_via(value); print_x_synth_via(value);
} }
static void static void
print_80000001_eax_transmeta(unsigned int value) print_80000001_eax_transmeta(unsigned int value)
{ {
static ccstring family[16] = { NULL, static ccstring family[1<<4] = { NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
"Transmeta Crusoe" }; "Transmeta Crusoe" };
static named_item names[] static named_item names[]
= { { "generation" , 8, 11, family }, = { { "generation" , 8, 11, family },
{ "model" , 4, 7, NIL_IMAGES }, { "model" , 4, 7, NIL_IMAGES },
{ "stepping" , 0, 3, NIL_IMAGES }, { "stepping" , 0, 3, NIL_IMAGES },
}; };
printf(" extended processor signature (0x80000001/eax):\n"); printf(" extended processor signature (0x80000001/eax):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
print_synth_transmeta(" (simple synth)", value, NULL); print_synth_transmeta(" (simple synth)", value, NULL);
} }
static void static void
print_80000001_eax(unsigned int value, print_80000001_eax(unsigned int value,
vendor_t vendor) vendor_t vendor)
{ {
switch (vendor) { switch (vendor) {
case VENDOR_AMD: case VENDOR_AMD:
print_80000001_eax_amd(value); print_80000001_eax_amd(value);
break; break;
case VENDOR_VIA: case VENDOR_VIA:
print_80000001_eax_via(value); print_80000001_eax_via(value);
break; break;
case VENDOR_TRANSMETA: case VENDOR_TRANSMETA:
print_80000001_eax_transmeta(value); print_80000001_eax_transmeta(value);
break; break;
case VENDOR_HYGON:
print_80000001_eax_hygon(value);
break;
case VENDOR_INTEL: case VENDOR_INTEL:
case VENDOR_CYRIX: case VENDOR_CYRIX:
case VENDOR_UMC: case VENDOR_UMC:
case VENDOR_NEXGEN: case VENDOR_NEXGEN:
case VENDOR_RISE: case VENDOR_RISE:
case VENDOR_SIS: case VENDOR_SIS:
case VENDOR_NSC: case VENDOR_NSC:
case VENDOR_VORTEX: case VENDOR_VORTEX:
case VENDOR_RDC: case VENDOR_RDC:
case VENDOR_UNKNOWN: case VENDOR_UNKNOWN:
skipping to change at line 5166 skipping to change at line 5540
{ {
static named_item names[] static named_item names[]
= { { "SYSCALL and SYSRET instructions" , 11, 11, bools }, = { { "SYSCALL and SYSRET instructions" , 11, 11, bools },
{ "execution disable" , 20, 20, bools }, { "execution disable" , 20, 20, bools },
{ "1-GB large page support" , 26, 26, bools }, { "1-GB large page support" , 26, 26, bools },
{ "RDTSCP" , 27, 27, bools }, { "RDTSCP" , 27, 27, bools },
{ "64-bit extensions technology available" , 29, 29, bools }, { "64-bit extensions technology available" , 29, 29, bools },
}; };
printf(" extended feature flags (0x80000001/edx):\n"); printf(" extended feature flags (0x80000001/edx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000001_edx_amd(unsigned int value) print_80000001_edx_amd(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "x87 FPU on chip" , 0, 0, bools }, = { { "x87 FPU on chip" , 0, 0, bools },
{ "virtual-8086 mode enhancement" , 1, 1, bools }, { "virtual-8086 mode enhancement" , 1, 1, bools },
{ "debugging extensions" , 2, 2, bools }, { "debugging extensions" , 2, 2, bools },
skipping to change at line 5205 skipping to change at line 5579
{ "FXSAVE/FXRSTOR" , 24, 24, bools }, { "FXSAVE/FXRSTOR" , 24, 24, bools },
{ "SSE extensions" , 25, 25, bools }, { "SSE extensions" , 25, 25, bools },
{ "1-GB large page support" , 26, 26, bools }, { "1-GB large page support" , 26, 26, bools },
{ "RDTSCP" , 27, 27, bools }, { "RDTSCP" , 27, 27, bools },
{ "long mode (AA-64)" , 29, 29, bools }, { "long mode (AA-64)" , 29, 29, bools },
{ "3DNow! instruction extensions" , 30, 30, bools }, { "3DNow! instruction extensions" , 30, 30, bools },
{ "3DNow! instructions" , 31, 31, bools }, { "3DNow! instructions" , 31, 31, bools },
}; };
printf(" extended feature flags (0x80000001/edx):\n"); printf(" extended feature flags (0x80000001/edx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000001_edx_cyrix_via(unsigned int value) print_80000001_edx_cyrix_via(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "x87 FPU on chip" , 0, 0, bools }, = { { "x87 FPU on chip" , 0, 0, bools },
{ "virtual-8086 mode enhancement" , 1, 1, bools }, { "virtual-8086 mode enhancement" , 1, 1, bools },
{ "debugging extensions" , 2, 2, bools }, { "debugging extensions" , 2, 2, bools },
skipping to change at line 5241 skipping to change at line 5615
{ "AMD multimedia instruction extensions" , 22, 22, bools }, { "AMD multimedia instruction extensions" , 22, 22, bools },
{ "MMX Technology" , 23, 23, bools }, { "MMX Technology" , 23, 23, bools },
{ "extended MMX" , 24, 24, bools }, { "extended MMX" , 24, 24, bools },
{ "SSE extensions" , 25, 25, bools }, { "SSE extensions" , 25, 25, bools },
{ "AA-64" , 29, 29, bools }, { "AA-64" , 29, 29, bools },
{ "3DNow! instruction extensions" , 30, 30, bools }, { "3DNow! instruction extensions" , 30, 30, bools },
{ "3DNow! instructions" , 31, 31, bools }, { "3DNow! instructions" , 31, 31, bools },
}; };
printf(" extended feature flags (0x80000001/edx):\n"); printf(" extended feature flags (0x80000001/edx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000001_edx_transmeta(unsigned int value) print_80000001_edx_transmeta(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "x87 FPU on chip" , 0, 0, bools }, = { { "x87 FPU on chip" , 0, 0, bools },
{ "virtual-8086 mode enhancement" , 1, 1, bools }, { "virtual-8086 mode enhancement" , 1, 1, bools },
{ "debugging extensions" , 2, 2, bools }, { "debugging extensions" , 2, 2, bools },
skipping to change at line 5269 skipping to change at line 5643
{ "machine check architecture" , 14, 14, bools }, { "machine check architecture" , 14, 14, bools },
{ "conditional move/compare instruction" , 15, 15, bools }, { "conditional move/compare instruction" , 15, 15, bools },
{ "FP conditional move instructions" , 16, 16, bools }, { "FP conditional move instructions" , 16, 16, bools },
{ "page size extension" , 17, 17, bools }, { "page size extension" , 17, 17, bools },
{ "AMD multimedia instruction extensions" , 22, 22, bools }, { "AMD multimedia instruction extensions" , 22, 22, bools },
{ "MMX Technology" , 23, 23, bools }, { "MMX Technology" , 23, 23, bools },
{ "FXSAVE/FXRSTOR" , 24, 24, bools }, { "FXSAVE/FXRSTOR" , 24, 24, bools },
}; };
printf(" extended feature flags (0x80000001/edx):\n"); printf(" extended feature flags (0x80000001/edx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000001_edx_nsc(unsigned int value) print_80000001_edx_nsc(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "x87 FPU on chip" , 0, 0, bools }, = { { "x87 FPU on chip" , 0, 0, bools },
{ "virtual-8086 mode enhancement" , 1, 1, bools }, { "virtual-8086 mode enhancement" , 1, 1, bools },
{ "debugging extensions" , 2, 2, bools }, { "debugging extensions" , 2, 2, bools },
skipping to change at line 5294 skipping to change at line 5668
{ "CMPXCHG8B inst." , 8, 8, bools }, { "CMPXCHG8B inst." , 8, 8, bools },
{ "SYSCALL and SYSRET instructions" , 11, 11, bools }, { "SYSCALL and SYSRET instructions" , 11, 11, bools },
{ "global paging extension" , 13, 13, bools }, { "global paging extension" , 13, 13, bools },
{ "conditional move/compare instruction" , 15, 15, bools }, { "conditional move/compare instruction" , 15, 15, bools },
{ "FPU conditional move instruction" , 16, 16, bools }, { "FPU conditional move instruction" , 16, 16, bools },
{ "MMX Technology" , 23, 23, bools }, { "MMX Technology" , 23, 23, bools },
{ "6x86MX multimedia extensions" , 24, 24, bools }, { "6x86MX multimedia extensions" , 24, 24, bools },
}; };
printf(" extended feature flags (0x80000001/edx):\n"); printf(" extended feature flags (0x80000001/edx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000001_edx(unsigned int value, print_80000001_edx(unsigned int value,
vendor_t vendor) vendor_t vendor)
{ {
switch (vendor) { switch (vendor) {
case VENDOR_INTEL: case VENDOR_INTEL:
print_80000001_edx_intel(value); print_80000001_edx_intel(value);
break; break;
case VENDOR_AMD: case VENDOR_AMD:
case VENDOR_HYGON:
print_80000001_edx_amd(value); print_80000001_edx_amd(value);
break; break;
case VENDOR_CYRIX: case VENDOR_CYRIX:
case VENDOR_VIA: case VENDOR_VIA:
print_80000001_edx_cyrix_via(value); print_80000001_edx_cyrix_via(value);
break; break;
case VENDOR_TRANSMETA: case VENDOR_TRANSMETA:
print_80000001_edx_transmeta(value); print_80000001_edx_transmeta(value);
break; break;
case VENDOR_NSC: case VENDOR_NSC:
skipping to change at line 5356 skipping to change at line 5731
{ "XOP support" , 11, 11, bools }, { "XOP support" , 11, 11, bools },
{ "SKINIT/STGI support" , 12, 12, bools }, { "SKINIT/STGI support" , 12, 12, bools },
{ "watchdog timer support" , 13, 13, bools }, { "watchdog timer support" , 13, 13, bools },
{ "lightweight profiling support" , 15, 15, bools }, { "lightweight profiling support" , 15, 15, bools },
{ "4-operand FMA instruction" , 16, 16, bools }, { "4-operand FMA instruction" , 16, 16, bools },
{ "TCE: translation cache extension" , 17, 17, bools }, { "TCE: translation cache extension" , 17, 17, bools },
{ "NodeId MSR C001100C" , 19, 19, bools }, { "NodeId MSR C001100C" , 19, 19, bools },
{ "TBM support" , 21, 21, bools }, { "TBM support" , 21, 21, bools },
{ "topology extensions" , 22, 22, bools }, { "topology extensions" , 22, 22, bools },
{ "core performance counter extensions" , 23, 23, bools }, { "core performance counter extensions" , 23, 23, bools },
{ "NB performance counter extensions" , 24, 24, bools },
{ "data breakpoint extension" , 26, 26, bools }, { "data breakpoint extension" , 26, 26, bools },
{ "performance time-stamp counter support" , 27, 27, bools }, { "performance time-stamp counter support" , 27, 27, bools },
{ "performance counter extensions" , 28, 28, bools }, { "performance counter extensions" , 28, 28, bools },
{ "MWAITX/MONITORX supported" , 29, 29, bools }, { "MWAITX/MONITORX supported" , 29, 29, bools },
}; };
printf(" AMD feature flags (0x80000001/ecx):\n"); print_names(value, names, LENGTH(names),
print_names(value, names, LENGTH(names, named_item),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000001_ecx_intel(unsigned int value) print_80000001_ecx_intel(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "LAHF/SAHF supported in 64-bit mode" , 0, 0, bools }, = { { "LAHF/SAHF supported in 64-bit mode" , 0, 0, bools },
{ "LZCNT advanced bit manipulation" , 5, 5, bools }, { "LZCNT advanced bit manipulation" , 5, 5, bools },
{ "3DNow! PREFETCH/PREFETCHW instructions" , 8, 8, bools }, { "3DNow! PREFETCH/PREFETCHW instructions" , 8, 8, bools },
}; };
printf(" Intel feature flags (0x80000001/ecx):\n"); print_names(value, names, LENGTH(names),
print_names(value, names, LENGTH(names, named_item),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000001_ecx(unsigned int value, print_80000001_ecx(unsigned int value,
vendor_t vendor) vendor_t vendor)
{ {
switch (vendor) { switch (vendor) {
case VENDOR_AMD: case VENDOR_AMD:
printf(" AMD feature flags (0x80000001/ecx):\n");
print_80000001_ecx_amd(value); print_80000001_ecx_amd(value);
break; break;
case VENDOR_INTEL: case VENDOR_INTEL:
printf(" Intel feature flags (0x80000001/ecx):\n");
print_80000001_ecx_intel(value); print_80000001_ecx_intel(value);
break; break;
case VENDOR_HYGON:
printf(" Hygon feature flags (0x80000001/ecx):\n");
print_80000001_ecx_amd(value);
break;
case VENDOR_CYRIX: case VENDOR_CYRIX:
case VENDOR_VIA: case VENDOR_VIA:
case VENDOR_TRANSMETA: case VENDOR_TRANSMETA:
case VENDOR_UMC: case VENDOR_UMC:
case VENDOR_NEXGEN: case VENDOR_NEXGEN:
case VENDOR_RISE: case VENDOR_RISE:
case VENDOR_SIS: case VENDOR_SIS:
case VENDOR_NSC: case VENDOR_NSC:
case VENDOR_VORTEX: case VENDOR_VORTEX:
case VENDOR_RDC: case VENDOR_RDC:
case VENDOR_UNKNOWN: case VENDOR_UNKNOWN:
/* DO NOTHING */ /* DO NOTHING */
break; break;
} }
} }
static void static void
print_80000001_ebx_amd(unsigned int value, print_80000001_ebx_amd(unsigned int value,
unsigned int val_1_eax) unsigned int val_1_eax)
{ {
unsigned int max_len = 0;
if (__F(val_1_eax) == _XF(0) + _F(15) if (__F(val_1_eax) == _XF(0) + _F(15)
&& __M(val_1_eax) < _XM(4) + _M(0)) { && __M(val_1_eax) < _XM(4) + _M(0)) {
static named_item names[] static named_item names[]
= { { "raw" , 0, 31, NIL_IMAGES }, = { { "raw" , 0, 31, NIL_IMAGES },
{ "BrandId" , 0, 16, NIL_IMAGES }, { "BrandId" , 0, 16, NIL_IMAGES },
{ "BrandTableIndex" , 6, 12, NIL_IMAGES }, { "BrandTableIndex" , 6, 12, NIL_IMAGES },
{ "NN" , 0, 6, NIL_IMAGES }, { "NN" , 0, 6, NIL_IMAGES },
}; };
printf(" extended brand id (0x80000001/ebx):\n"); printf(" extended brand id (0x80000001/ebx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} else if (__F(val_1_eax) == _XF(0) + _F(15) } else if (__F(val_1_eax) == _XF(0) + _F(15)
&& __M(val_1_eax) >= _XM(4) + _M(0)) { && __M(val_1_eax) >= _XM(4) + _M(0)) {
static named_item names[] static named_item names[]
= { { "raw" , 0, 31, NIL_IMAGES }, = { { "raw" , 0, 31, NIL_IMAGES },
{ "BrandId" , 0, 16, NIL_IMAGES }, { "BrandId" , 0, 16, NIL_IMAGES },
{ "PwrLmt:high" , 6, 8, NIL_IMAGES }, { "PwrLmt:high" , 6, 8, NIL_IMAGES },
{ "PwrLmt:low" , 14, 14, NIL_IMAGES }, { "PwrLmt:low" , 14, 14, NIL_IMAGES },
{ "BrandTableIndex" , 9, 13, NIL_IMAGES }, { "BrandTableIndex" , 9, 13, NIL_IMAGES },
{ "NN:high" , 15, 15, NIL_IMAGES }, { "NN:high" , 15, 15, NIL_IMAGES },
{ "NN:low" , 0, 5, NIL_IMAGES }, { "NN:low" , 0, 5, NIL_IMAGES },
}; };
printf(" extended brand id (0x80000001/ebx):\n"); printf(" extended brand id (0x80000001/ebx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} else if (__F(val_1_eax) == _XF(1) + _F(15) } else if (__F(val_1_eax) == _XF(1) + _F(15)
|| __F(val_1_eax) == _XF(2) + _F(15)) { || __F(val_1_eax) == _XF(2) + _F(15)) {
static named_item names[] static named_item names[]
= { { "raw" , 0, 31, NIL_IMAGES }, = { { "raw" , 0, 31, NIL_IMAGES },
{ "BrandId" , 0, 15, NIL_IMAGES }, { "BrandId" , 0, 15, NIL_IMAGES },
{ "str1" , 11, 14, NIL_IMAGES }, { "str1" , 11, 14, NIL_IMAGES },
{ "str2" , 0, 3, NIL_IMAGES }, { "str2" , 0, 3, NIL_IMAGES },
{ "PartialModel" , 4, 10, NIL_IMAGES }, { "PartialModel" , 4, 10, NIL_IMAGES },
{ "PG" , 15, 15, NIL_IMAGES }, { "PG" , 15, 15, NIL_IMAGES },
{ "PkgType" , 28, 31, NIL_IMAGES },
}; };
printf(" extended brand id (0x80000001/ebx):\n"); printf(" extended brand id (0x80000001/ebx):\n");
print_names(value, names, LENGTH(names, named_item), max_len = 12;
/* max_len => */ 0); print_names(value, names, LENGTH(names),
/* max_len => */ max_len);
} else { } else {
static named_item names[] static named_item names[]
= { { "raw" , 0, 31, NIL_IMAGES }, = { { "raw" , 0, 31, NIL_IMAGES },
{ "BrandId" , 0, 15, NIL_IMAGES }, { "BrandId" , 0, 15, NIL_IMAGES },
}; };
printf(" extended brand id (0x80000001/ebx):\n"); printf(" extended brand id (0x80000001/ebx):\n");
print_names(value, names, LENGTH(names, named_item), max_len = 7;
/* max_len => */ 0); print_names(value, names, LENGTH(names),
/* max_len => */ max_len);
}
// PkgType values come from these two guides (depending on family):
// AMD BIOS and Kernel Developer's Guide (BKDG) for ...
// Processor Programming Reference (PPR) for ...
//
// NOTE: AMD Family = XF + F, e.g. 0x17 (17h) = 0xf + 0x8
// AMD Model = (XM << 4) + M, e.g. 0x18 (18h) = (0x1 << 4) + 0x8
if (__F(val_1_eax) >= _XF(1) + _F(15)) {
ccstring* use_pkg_type = NIL_IMAGES;
if (__F(val_1_eax) == _XF(1) + _F(15)) {
// Family 10h
static ccstring pkg_type[1<<4] = { "Fr2/Fr5/Fr6 (0)",
"AM2r2/AM3 (1)",
"S1g3/S1g4 (2)",
"G34 (3)",
"ASB2 (4)",
"C32 (5)" };
use_pkg_type = pkg_type;
} else if (__F(val_1_eax) == _XF(6) + _F(15)) {
// Family 15h
if (__M(val_1_eax) >= _XM(0) + _M(0)
&& __M(val_1_eax) <= _XM(0) + _M(15)) {
static ccstring pkg_type[1<<4] = { NULL,
"AM3r2 (1)",
NULL,
"G34r1 (3)",
NULL,
"C32r1 (5)" };
use_pkg_type = pkg_type;
} else if (__M(val_1_eax) >= _XM(1) + _M(0)
&& __M(val_1_eax) <= _XM(1) + _M(15)) {
static ccstring pkg_type[1<<4] = { "FP2 (BGA) (0)",
"FS1r2 (uPGA) (1)",
"FM2 (PGA) (2)" };
use_pkg_type = pkg_type;
} else if (__M(val_1_eax) >= _XM(3) + _M(0)
&& __M(val_1_eax) <= _XM(3) + _M(15)) {
static ccstring pkg_type[1<<4] = { "FP3 (BGA) (0)",
"FM2r2 (uPGA) (1)" };
use_pkg_type = pkg_type;
} else if (__M(val_1_eax) >= _XM(6) + _M(0)
&& __M(val_1_eax) <= _XM(6) + _M(15)) {
static ccstring pkg_type[1<<4] = { "FP4 (BGA) (0)",
NULL,
"AM4 (uPGA) (2)",
"FM2r2 (uPGA) (3)" };
use_pkg_type = pkg_type;
} else if (__M(val_1_eax) >= _XM(7) + _M(0)
&& __M(val_1_eax) <= _XM(7) + _M(15)) {
static ccstring pkg_type[1<<4] = { "FP4 (BGA) (0)",
NULL,
"AM4 (uPGA) (2)",
NULL,
"FT4 (BGA) (4)" };
use_pkg_type = pkg_type;
}
} else if (__F(val_1_eax) == _XF(7) + _F(15)) {
// Family 16h
if (__M(val_1_eax) >= _XM(0) + _M(0)
&& __M(val_1_eax) <= _XM(0) + _M(15)) {
static ccstring pkg_type[1<<4] = { "FT3 (BGA) (0)",
"FS1b (1)" };
use_pkg_type = pkg_type;
} else if (__M(val_1_eax) >= _XM(3) + _M(0)
&& __M(val_1_eax) <= _XM(3) + _M(15)) {
static ccstring pkg_type[1<<4] = { "FT3b (BGA) (0)",
NULL,
NULL,
"FP4 (3)" };
use_pkg_type = pkg_type;
}
} else if (__F(val_1_eax) == _XF(8) + _F(15)) {
// Family 17h
if (__M(val_1_eax) == _XM(0) + _M(1)
|| __M(val_1_eax) == _XM(0) + _M(8)) {
static ccstring pkg_type[1<<4] = { NULL,
NULL,
"AM4 (2)" };
use_pkg_type = pkg_type;
} else if (__M(val_1_eax) == _XM(1) + _M(8)) {
static ccstring pkg_type[1<<4] = { "FP5 (0)",
NULL,
"AM4 (2)" };
use_pkg_type = pkg_type;
} else if (__M(val_1_eax) == _XM(7) + _M(1)) {
static ccstring pkg_type[1<<4] = { NULL,
NULL,
"AM4 (2)" };
use_pkg_type = pkg_type;
}
}
named_item names[] = { { "PkgType", 28, 31, use_pkg_type } };
print_names(value, names, LENGTH(names),
/* max_len => */ max_len);
} }
} }
static void static void
print_80000001_ebx(unsigned int value, print_80000001_ebx(unsigned int value,
vendor_t vendor, vendor_t vendor,
unsigned int val_1_eax) unsigned int val_1_eax)
{ {
switch (vendor) { switch (vendor) {
case VENDOR_AMD: case VENDOR_AMD:
case VENDOR_HYGON:
print_80000001_ebx_amd(value, val_1_eax); print_80000001_ebx_amd(value, val_1_eax);
break; break;
case VENDOR_INTEL: case VENDOR_INTEL:
case VENDOR_CYRIX: case VENDOR_CYRIX:
case VENDOR_VIA: case VENDOR_VIA:
case VENDOR_TRANSMETA: case VENDOR_TRANSMETA:
case VENDOR_UMC: case VENDOR_UMC:
case VENDOR_NEXGEN: case VENDOR_NEXGEN:
case VENDOR_RISE: case VENDOR_RISE:
case VENDOR_SIS: case VENDOR_SIS:
skipping to change at line 5504 skipping to change at line 5988
{ {
static named_item names[] static named_item names[]
= { { "instruction # entries" , 0, 7, NIL_IMAGES }, = { { "instruction # entries" , 0, 7, NIL_IMAGES },
{ "instruction associativity" , 8, 15, NIL_IMAGES }, { "instruction associativity" , 8, 15, NIL_IMAGES },
{ "data # entries" , 16, 23, NIL_IMAGES }, { "data # entries" , 16, 23, NIL_IMAGES },
{ "data associativity" , 24, 31, NIL_IMAGES }, { "data associativity" , 24, 31, NIL_IMAGES },
}; };
printf(" L1 TLB/cache information: 2M/4M pages & L1 TLB" printf(" L1 TLB/cache information: 2M/4M pages & L1 TLB"
" (0x80000005/eax):\n"); " (0x80000005/eax):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000005_ebx(unsigned int value) print_80000005_ebx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "instruction # entries" , 0, 7, NIL_IMAGES }, = { { "instruction # entries" , 0, 7, NIL_IMAGES },
{ "instruction associativity" , 8, 15, NIL_IMAGES }, { "instruction associativity" , 8, 15, NIL_IMAGES },
{ "data # entries" , 16, 23, NIL_IMAGES }, { "data # entries" , 16, 23, NIL_IMAGES },
{ "data associativity" , 24, 31, NIL_IMAGES }, { "data associativity" , 24, 31, NIL_IMAGES },
}; };
printf(" L1 TLB/cache information: 4K pages & L1 TLB" printf(" L1 TLB/cache information: 4K pages & L1 TLB"
" (0x80000005/ebx):\n"); " (0x80000005/ebx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000005_ecx(unsigned int value) print_80000005_ecx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "line size (bytes)" , 0, 7, NIL_IMAGES }, = { { "line size (bytes)" , 0, 7, NIL_IMAGES },
{ "lines per tag" , 8, 15, NIL_IMAGES }, { "lines per tag" , 8, 15, NIL_IMAGES },
{ "associativity" , 16, 23, NIL_IMAGES }, { "associativity" , 16, 23, NIL_IMAGES },
{ "size (KB)" , 24, 31, NIL_IMAGES }, { "size (KB)" , 24, 31, NIL_IMAGES },
}; };
printf(" L1 data cache information (0x80000005/ecx):\n"); printf(" L1 data cache information (0x80000005/ecx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000005_edx(unsigned int value) print_80000005_edx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "line size (bytes)" , 0, 7, NIL_IMAGES }, = { { "line size (bytes)" , 0, 7, NIL_IMAGES },
{ "lines per tag" , 8, 15, NIL_IMAGES }, { "lines per tag" , 8, 15, NIL_IMAGES },
{ "associativity" , 16, 23, NIL_IMAGES }, { "associativity" , 16, 23, NIL_IMAGES },
{ "size (KB)" , 24, 31, NIL_IMAGES }, { "size (KB)" , 24, 31, NIL_IMAGES },
}; };
printf(" L1 instruction cache information (0x80000005/edx):\n"); printf(" L1 instruction cache information (0x80000005/edx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static ccstring l2_assoc[] = { "L2 off (0)", static ccstring l2_assoc[1<<4] = { "L2 off (0)",
"direct mapped (1)", "direct mapped (1)",
"2-way (2)", "2-way (2)",
NULL, "3-way (3)",
"4-way (4)", "4-way (4)",
NULL, "6-way (5)",
"8-way (6)", "8-way (6)",
NULL, NULL,
"16-way (8)", "16-way (8)",
NULL, NULL,
"32-way (10)", "32-way (10)",
"48-way (11)", "48-way (11)",
"64-way (12)", "64-way (12)",
"96-way (13)", "96-way (13)",
"128-way (14)", "128-way (14)",
"full (15)" }; "full (15)" };
static void static void
print_80000006_eax(unsigned int value) print_80000006_eax(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "instruction # entries" , 0, 11, NIL_IMAGES }, = { { "instruction # entries" , 0, 11, NIL_IMAGES },
{ "instruction associativity" , 12, 15, l2_assoc }, { "instruction associativity" , 12, 15, l2_assoc },
{ "data # entries" , 16, 27, NIL_IMAGES }, { "data # entries" , 16, 27, NIL_IMAGES },
{ "data associativity" , 28, 31, l2_assoc }, { "data associativity" , 28, 31, l2_assoc },
}; };
printf(" L2 TLB/cache information: 2M/4M pages & L2 TLB" printf(" L2 TLB/cache information: 2M/4M pages & L2 TLB"
" (0x80000006/eax):\n"); " (0x80000006/eax):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000006_ebx(unsigned int value) print_80000006_ebx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "instruction # entries" , 0, 11, NIL_IMAGES }, = { { "instruction # entries" , 0, 11, NIL_IMAGES },
{ "instruction associativity" , 12, 15, l2_assoc }, { "instruction associativity" , 12, 15, l2_assoc },
{ "data # entries" , 16, 27, NIL_IMAGES }, { "data # entries" , 16, 27, NIL_IMAGES },
{ "data associativity" , 28, 31, l2_assoc }, { "data associativity" , 28, 31, l2_assoc },
}; };
printf(" L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):\n"); printf(" L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000006_ecx(unsigned int value, print_80000006_ecx(unsigned int value,
code_stash_t* stash) code_stash_t* stash)
{ {
static named_item names[] static named_item names[]
= { { "line size (bytes)" , 0, 7, NIL_IMAGES }, = { { "line size (bytes)" , 0, 7, NIL_IMAGES },
{ "lines per tag" , 8, 11, NIL_IMAGES }, { "lines per tag" , 8, 11, NIL_IMAGES },
{ "associativity" , 12, 15, l2_assoc }, { "associativity" , 12, 15, l2_assoc },
{ "size (KB)" , 16, 31, NIL_IMAGES }, { "size (KB)" , 16, 31, NIL_IMAGES },
}; };
printf(" L2 unified cache information (0x80000006/ecx):\n"); printf(" L2 unified cache information (0x80000006/ecx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
if (((value >> 12) & 0xf) == 4 && (value >> 16) == 256) { if (((value >> 12) & 0xf) == 4 && (value >> 16) == 256) {
stash->L2_4w_256K = TRUE; stash->L2_4w_256K = TRUE;
} else if (((value >> 12) & 0xf) == 4 && (value >> 16) == 512) { } else if (((value >> 12) & 0xf) == 4 && (value >> 16) == 512) {
stash->L2_4w_512K = TRUE; stash->L2_4w_512K = TRUE;
} }
} }
static void static void
print_80000006_edx(unsigned int value) print_80000006_edx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "line size (bytes)" , 0, 7, NIL_IMAGES }, = { { "line size (bytes)" , 0, 7, NIL_IMAGES },
{ "lines per tag" , 8, 11, NIL_IMAGES }, { "lines per tag" , 8, 11, NIL_IMAGES },
{ "associativity" , 12, 15, l2_assoc }, { "associativity" , 12, 15, l2_assoc },
{ "size (in 512KB units)" , 18, 31, NIL_IMAGES }, { "size (in 512KB units)" , 18, 31, NIL_IMAGES },
}; };
printf(" L3 cache information (0x80000006/edx):\n"); printf(" L3 cache information (0x80000006/edx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000007_ebx(unsigned int value) print_80000007_ebx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "MCA overflow recovery support" , 0, 0, bools }, = { { "MCA overflow recovery support" , 0, 0, bools },
{ "SUCCOR support" , 1, 1, bools }, { "SUCCOR support" , 1, 1, bools },
{ "HWA: hardware assert support" , 2, 2, bools }, { "HWA: hardware assert support" , 2, 2, bools },
{ "scalable MCA support" , 3, 3, bools }, { "scalable MCA support" , 3, 3, bools },
}; };
printf(" RAS Capability (0x80000007/ebx):\n"); printf(" RAS Capability (0x80000007/ebx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000007_ecx(unsigned int value) print_80000007_ecx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "CmpUnitPwrSampleTimeRatio" , 0, 31, NIL_IMAGES }, = { { "CmpUnitPwrSampleTimeRatio" , 0, 31, NIL_IMAGES },
}; };
printf(" Advanced Power Management Features (0x80000007/ecx):\n"); printf(" Advanced Power Management Features (0x80000007/ecx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000007_edx(unsigned int value) print_80000007_edx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "TS: temperature sensing diode" , 0, 0, bools }, = { { "TS: temperature sensing diode" , 0, 0, bools },
{ "FID: frequency ID control" , 1, 1, bools }, { "FID: frequency ID control" , 1, 1, bools },
{ "VID: voltage ID control" , 2, 2, bools }, { "VID: voltage ID control" , 2, 2, bools },
skipping to change at line 5688 skipping to change at line 6172
{ "TscInvariant" , 8, 8, bools }, { "TscInvariant" , 8, 8, bools },
{ "CPB: core performance boost" , 9, 9, bools }, { "CPB: core performance boost" , 9, 9, bools },
{ "read-only effective frequency interface" , 10, 10, bools }, { "read-only effective frequency interface" , 10, 10, bools },
{ "processor feedback interface" , 11, 11, bools }, { "processor feedback interface" , 11, 11, bools },
{ "APM power reporting" , 12, 12, bools }, { "APM power reporting" , 12, 12, bools },
{ "connected standby" , 13, 13, bools }, { "connected standby" , 13, 13, bools },
{ "RAPL: running average power limit" , 14, 14, bools }, { "RAPL: running average power limit" , 14, 14, bools },
}; };
printf(" Advanced Power Management Features (0x80000007/edx):\n"); printf(" Advanced Power Management Features (0x80000007/edx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000008_eax(unsigned int value) print_80000008_eax(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "maximum physical address bits" , 0, 7, NIL_IMAGES }, = { { "maximum physical address bits" , 0, 7, NIL_IMAGES },
{ "maximum linear (virtual) address bits" , 8, 15, NIL_IMAGES }, { "maximum linear (virtual) address bits" , 8, 15, NIL_IMAGES },
{ "maximum guest physical address bits" , 16, 23, NIL_IMAGES }, { "maximum guest physical address bits" , 16, 23, NIL_IMAGES },
}; };
printf(" Physical Address and Linear Address Size (0x80000008/eax):\n"); printf(" Physical Address and Linear Address Size (0x80000008/eax):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000008_ebx(unsigned int value) print_80000008_ebx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "CLZERO instruction" , 0, 0, bools }, = { { "CLZERO instruction" , 0, 0, bools },
{ "instructions retired count support" , 1, 1, bools }, { "instructions retired count support" , 1, 1, bools },
{ "always save/restore error pointers" , 2, 2, bools }, { "always save/restore error pointers" , 2, 2, bools },
{ "IBPB: indirect branch prediction barrier", 12, 12, bools },
{ "IBRS: indirect branch restr speculation" , 14, 14, bools },
{ "STIBP: 1 thr indirect branch predictor" , 15, 15, bools },
}; };
printf(" Extended Feature Extensions ID (0x80000008/ebx):\n"); printf(" Extended Feature Extensions ID (0x80000008/ebx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000008_ecx(unsigned int value) print_80000008_ecx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "number of CPU cores - 1" , 0, 7, NIL_IMAGES }, = { { "number of CPU cores - 1" , 0, 7, NIL_IMAGES },
{ "ApicIdCoreIdSize" , 12, 15, NIL_IMAGES }, { "ApicIdCoreIdSize" , 12, 15, NIL_IMAGES },
}; };
printf(" Logical CPU cores (0x80000008/ecx):\n"); printf(" Logical CPU cores (0x80000008/ecx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_8000000a_eax(unsigned int value) print_8000000a_eax(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "SvmRev: SVM revision" , 0, 7, NIL_IMAGES }, = { { "SvmRev: SVM revision" , 0, 7, NIL_IMAGES },
}; };
printf(" SVM Secure Virtual Machine (0x8000000a/eax):\n"); printf(" SVM Secure Virtual Machine (0x8000000a/eax):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_8000000a_edx(unsigned int value) print_8000000a_edx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "nested paging" , 0, 0, bools }, = { { "nested paging" , 0, 0, bools },
{ "LBR virtualization" , 1, 1, bools }, { "LBR virtualization" , 1, 1, bools },
{ "SVM lock" , 2, 2, bools }, { "SVM lock" , 2, 2, bools },
{ "NRIP save" , 3, 3, bools }, { "NRIP save" , 3, 3, bools },
{ "MSR based TSC rate control" , 4, 4, bools }, { "MSR based TSC rate control" , 4, 4, bools },
{ "VMCB clean bits support" , 5, 5, bools }, { "VMCB clean bits support" , 5, 5, bools },
{ "flush by ASID" , 6, 6, bools }, { "flush by ASID" , 6, 6, bools },
{ "decode assists" , 7, 7, bools }, { "decode assists" , 7, 7, bools },
{ "SSSE3/SSE5 opcode set disable" , 9, 9, bools }, { "SSSE3/SSE5 opcode set disable" , 9, 9, bools },
{ "pause intercept filter" , 10, 10, bools }, { "pause intercept filter" , 10, 10, bools },
{ "pause filter threshold" , 12, 12, bools }, { "pause filter threshold" , 12, 12, bools },
{ "AVIC: AMD virtual interrupt controller" , 13, 13, bools }, { "AVIC: AMD virtual interrupt controller" , 13, 13, bools },
{ "virtualized VMLOAD/VMSAVE" , 15, 15, bools }, { "virtualized VMLOAD/VMSAVE" , 15, 15, bools },
{ "virtualized GIF" , 16, 16, bools }, { "virtualized global interrupt flag (GIF)" , 16, 16, bools },
}; };
printf(" SVM Secure Virtual Machine (0x8000000a/edx):\n"); printf(" SVM Secure Virtual Machine (0x8000000a/edx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_8000000a_ebx(unsigned int value) print_8000000a_ebx(unsigned int value)
{ {
printf(" NASID: number of address space identifiers = 0x%x (%u):\n", printf(" NASID: number of address space identifiers = 0x%x (%u):\n",
value, value); value, value);
} }
skipping to change at line 5788 skipping to change at line 6275
print_80000019_eax(unsigned int value) print_80000019_eax(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "instruction # entries" , 0, 11, NIL_IMAGES }, = { { "instruction # entries" , 0, 11, NIL_IMAGES },
{ "instruction associativity" , 12, 15, l2_assoc }, { "instruction associativity" , 12, 15, l2_assoc },
{ "data # entries" , 16, 27, NIL_IMAGES }, { "data # entries" , 16, 27, NIL_IMAGES },
{ "data associativity" , 28, 31, l2_assoc }, { "data associativity" , 28, 31, l2_assoc },
}; };
printf(" L1 TLB information: 1G pages (0x80000019/eax):\n"); printf(" L1 TLB information: 1G pages (0x80000019/eax):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80000019_ebx(unsigned int value) print_80000019_ebx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "instruction # entries" , 0, 11, NIL_IMAGES }, = { { "instruction # entries" , 0, 11, NIL_IMAGES },
{ "instruction associativity" , 12, 15, l2_assoc }, { "instruction associativity" , 12, 15, l2_assoc },
{ "data # entries" , 16, 27, NIL_IMAGES }, { "data # entries" , 16, 27, NIL_IMAGES },
{ "data associativity" , 28, 31, l2_assoc }, { "data associativity" , 28, 31, l2_assoc },
}; };
printf(" L2 TLB information: 1G pages (0x80000019/ebx):\n"); printf(" L2 TLB information: 1G pages (0x80000019/ebx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_8000001a_eax(unsigned int value) print_8000001a_eax(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "128-bit SSE executed full-width" , 0, 0, bools }, = { { "128-bit SSE executed full-width" , 0, 0, bools },
{ "MOVU* better than MOVL*/MOVH*" , 1, 1, bools }, { "MOVU* better than MOVL*/MOVH*" , 1, 1, bools },
{ "256-bit SSE executed full-width" , 2, 2, bools }, { "256-bit SSE executed full-width" , 2, 2, bools },
}; };
printf(" SVM Secure Virtual Machine (0x8000001a/eax):\n"); printf(" SVM Secure Virtual Machine (0x8000001a/eax):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_8000001b_eax(unsigned int value) print_8000001b_eax(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "IBS feature flags valid" , 0, 0, bools }, = { { "IBS feature flags valid" , 0, 0, bools },
{ "IBS fetch sampling" , 1, 1, bools }, { "IBS fetch sampling" , 1, 1, bools },
{ "IBS execution sampling" , 2, 2, bools }, { "IBS execution sampling" , 2, 2, bools },
skipping to change at line 5839 skipping to change at line 6326
{ "op counting mode" , 4, 4, bools }, { "op counting mode" , 4, 4, bools },
{ "branch target address reporting" , 5, 5, bools }, { "branch target address reporting" , 5, 5, bools },
{ "IbsOpCurCnt and IbsOpMaxCnt extend 7" , 6, 6, bools }, { "IbsOpCurCnt and IbsOpMaxCnt extend 7" , 6, 6, bools },
{ "invalid RIP indication support" , 7, 7, bools }, { "invalid RIP indication support" , 7, 7, bools },
{ "fused branch micro-op indication support", 8, 8, bools }, { "fused branch micro-op indication support", 8, 8, bools },
{ "IBS fetch control extended MSR support" , 9, 9, bools }, { "IBS fetch control extended MSR support" , 9, 9, bools },
{ "IBS op data 4 MSR support" , 10, 10, bools }, { "IBS op data 4 MSR support" , 10, 10, bools },
}; };
printf(" Instruction Based Sampling Identifiers (0x8000001b/eax):\n"); printf(" Instruction Based Sampling Identifiers (0x8000001b/eax):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_8000001c_eax(unsigned int value) print_8000001c_eax(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "lightweight profiling" , 0, 0, bools }, = { { "lightweight profiling" , 0, 0, bools },
{ "LWPVAL instruction" , 1, 1, bools }, { "LWPVAL instruction" , 1, 1, bools },
{ "instruction retired event" , 2, 2, bools }, { "instruction retired event" , 2, 2, bools },
{ "branch retired event" , 3, 3, bools }, { "branch retired event" , 3, 3, bools },
{ "DC miss event" , 4, 4, bools }, { "DC miss event" , 4, 4, bools },
{ "core clocks not halted event" , 5, 5, bools }, { "core clocks not halted event" , 5, 5, bools },
{ "core reference clocks not halted event" , 6, 6, bools }, { "core reference clocks not halted event" , 6, 6, bools },
{ "interrupt on threshold overflow" , 31, 31, bools }, { "interrupt on threshold overflow" , 31, 31, bools },
}; };
printf(" Lightweight Profiling Capabilities: Availability" printf(" Lightweight Profiling Capabilities: Availability"
" (0x8000001c/eax):\n"); " (0x8000001c/eax):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_8000001c_ebx(unsigned int value) print_8000001c_ebx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "LWPCB byte size" , 0, 7, NIL_IMAGES }, = { { "LWPCB byte size" , 0, 7, NIL_IMAGES },
{ "event record byte size" , 8, 15, NIL_IMAGES }, { "event record byte size" , 8, 15, NIL_IMAGES },
{ "maximum EventId" , 16, 23, NIL_IMAGES }, { "maximum EventId" , 16, 23, NIL_IMAGES },
{ "EventInterval1 field offset" , 24, 31, NIL_IMAGES }, { "EventInterval1 field offset" , 24, 31, NIL_IMAGES },
}; };
printf(" Lightweight Profiling Capabilities (0x8000001c/ebx):\n"); printf(" Lightweight Profiling Capabilities (0x8000001c/ebx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_8000001c_ecx(unsigned int value) print_8000001c_ecx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "latency counter bit size" , 0, 4, NIL_IMAGES }, = { { "latency counter bit size" , 0, 4, NIL_IMAGES },
{ "data cache miss address valid" , 5, 5, bools }, { "data cache miss address valid" , 5, 5, bools },
{ "amount cache latency is rounded" , 6, 8, NIL_IMAGES }, { "amount cache latency is rounded" , 6, 8, NIL_IMAGES },
{ "LWP implementation version" , 9, 15, NIL_IMAGES }, { "LWP implementation version" , 9, 15, NIL_IMAGES },
{ "event ring buffer size in records" , 16, 23, NIL_IMAGES }, { "event ring buffer size in records" , 16, 23, NIL_IMAGES },
{ "branch prediction filtering" , 28, 28, bools }, { "branch prediction filtering" , 28, 28, bools },
{ "IP filtering" , 29, 29, bools }, { "IP filtering" , 29, 29, bools },
{ "cache level filtering" , 30, 30, bools }, { "cache level filtering" , 30, 30, bools },
{ "cache latency filteing" , 31, 31, bools }, { "cache latency filteing" , 31, 31, bools },
}; };
printf(" Lightweight Profiling Capabilities (0x8000001c/ecx):\n"); printf(" Lightweight Profiling Capabilities (0x8000001c/ecx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_8000001c_edx(unsigned int value) print_8000001c_edx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "lightweight profiling" , 0, 0, bools }, = { { "lightweight profiling" , 0, 0, bools },
{ "LWPVAL instruction" , 1, 1, bools }, { "LWPVAL instruction" , 1, 1, bools },
{ "instruction retired event" , 2, 2, bools }, { "instruction retired event" , 2, 2, bools },
{ "branch retired event" , 3, 3, bools }, { "branch retired event" , 3, 3, bools },
{ "DC miss event" , 4, 4, bools }, { "DC miss event" , 4, 4, bools },
{ "core clocks not halted event" , 5, 5, bools }, { "core clocks not halted event" , 5, 5, bools },
{ "core reference clocks not halted event" , 6, 6, bools }, { "core reference clocks not halted event" , 6, 6, bools },
{ "interrupt on threshold overflow" , 31, 31, bools }, { "interrupt on threshold overflow" , 31, 31, bools },
}; };
printf(" Lightweight Profiling Capabilities: Supported" printf(" Lightweight Profiling Capabilities: Supported"
" (0x8000001c/edx):\n"); " (0x8000001c/edx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_8000001d_eax(unsigned int value) print_8000001d_eax(unsigned int value)
{ {
static ccstring cache_type[] = { "no more caches (0)", static ccstring cache_type[1<<5] = { "no more caches (0)",
"data (1)", "data (1)",
"instruction (2)", "instruction (2)",
"unified (3)", "unified (3)" };
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL };
static named_item names[] static named_item names[]
= { { "type" , 0, 4, cache_type }, = { { "type" , 0, 4, cache_type },
{ "level" , 5, 7, NIL_IMAGES }, { "level" , 5, 7, NIL_IMAGES },
{ "self-initializing" , 8, 8, bools }, { "self-initializing" , 8, 8, bools },
{ "fully associative" , 9, 9, bools }, { "fully associative" , 9, 9, bools },
{ "extra cores sharing this cache" , 14, 25, NIL_IMAGES }, { "extra cores sharing this cache" , 14, 25, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 31); /* max_len => */ 31);
} }
static void static void
print_8000001d_ebx(unsigned int value) print_8000001d_ebx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "line size in bytes" , 0, 11, NIL_IMAGES }, = { { "line size in bytes" , 0, 11, NIL_IMAGES },
{ "physical line partitions" , 12, 21, NIL_IMAGES }, { "physical line partitions" , 12, 21, NIL_IMAGES },
{ "number of ways" , 22, 31, NIL_IMAGES }, { "number of ways" , 22, 31, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 31); /* max_len => */ 31);
} }
static void static void
print_8000001d_edx(unsigned int value) print_8000001d_edx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "write-back invalidate" , 0, 0, bools }, = { { "write-back invalidate" , 0, 0, bools },
{ "cache inclusive of lower levels" , 1, 1, bools }, { "cache inclusive of lower levels" , 1, 1, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 31); /* max_len => */ 31);
} }
static void static void
print_8000001e_ebx(unsigned int value) print_8000001e_ebx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "compute unit ID" , 0, 7, NIL_IMAGES }, = { { "compute unit ID" , 0, 7, NIL_IMAGES },
{ "cores per compute unit - 1" , 8, 9, NIL_IMAGES }, { "cores per compute unit - 1" , 8, 9, NIL_IMAGES },
}; };
printf(" Extended APIC ID (0x8000001e/ebx):\n"); printf(" Extended APIC ID (0x8000001e/ebx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_8000001e_ecx(unsigned int value) print_8000001e_ecx(unsigned int value)
{ {
static ccstring npp[] = { "1 node (0)", static ccstring npp[1<<2] = { "1 node (0)",
"2 nodes (1)", "2 nodes (1)" };
NULL, NULL, NULL,
NULL, NULL, NULL };
static named_item names[] static named_item names[]
= { { "node ID" , 0, 7, NIL_IMAGES }, = { { "node ID" , 0, 7, NIL_IMAGES },
{ "nodes per processor" , 8, 9, npp }, { "nodes per processor" , 8, 9, npp },
}; };
printf(" Extended APIC ID (0x8000001e/ecx):\n"); printf(" Extended APIC ID (0x8000001e/ecx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_8000001f_eax(unsigned int value) print_8000001f_eax(unsigned int value)
{ {
// This is undocumented as of 17-May-2018, so names are tentative. // This is undocumented as of 17-May-2018, so names are tentative.
static named_item names[] static named_item names[]
= { { "SME: secure memory encryption support" , 0, 0, bools }, = { { "SME: secure memory encryption support" , 0, 0, bools },
{ "SEV: secure encrypted virtualize support", 1, 1, bools }, { "SEV: secure encrypted virtualize support", 1, 1, bools },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_80860001_eax(unsigned int value) print_80860001_eax(unsigned int value)
{ {
static ccstring family[16] = { NULL, static ccstring family[1<<4] = { NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
"Transmeta Crusoe" }; "Transmeta Crusoe" };
static named_item names[] static named_item names[]
= { { "generation" , 8, 11, family }, = { { "generation" , 8, 11, family },
{ "model" , 4, 7, NIL_IMAGES }, { "model" , 4, 7, NIL_IMAGES },
{ "stepping" , 0, 3, NIL_IMAGES }, { "stepping" , 0, 3, NIL_IMAGES },
}; };
printf(" Transmeta processor signature (0x80860001/eax):\n"); printf(" Transmeta processor signature (0x80860001/eax):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
print_synth_transmeta(" (simple synth)", value, NULL); print_synth_transmeta(" (simple synth)", value, NULL);
} }
static void static void
print_80860001_edx(unsigned int value) print_80860001_edx(unsigned int value)
{ {
static named_item names[] static named_item names[]
= { { "recovery CMS active" , 0, 0, bools }, = { { "recovery CMS active" , 0, 0, bools },
{ "LongRun" , 1, 1, bools }, { "LongRun" , 1, 1, bools },
{ "LongRun Table Interface LRTI (CMS 4.2)" , 3, 3, bools }, { "LongRun Table Interface LRTI (CMS 4.2)" , 3, 3, bools },
{ "persistent translation technology 1.x" , 7, 7, bools }, { "persistent translation technology 1.x" , 7, 7, bools },
{ "persistent translation technology 2.0" , 8, 8, bools }, { "persistent translation technology 2.0" , 8, 8, bools },
{ "processor break events" , 12, 12, bools }, { "processor break events" , 12, 12, bools },
}; };
printf(" Transmeta feature flags (0x80860001/edx):\n"); printf(" Transmeta feature flags (0x80860001/edx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_transmeta_proc_rev_meaning(unsigned int proc_rev) print_transmeta_proc_rev_meaning(unsigned int proc_rev)
{ {
switch (proc_rev & 0xffff0000) { switch (proc_rev & 0xffff0000) {
case 0x01010000: case 0x01010000:
printf("(TM3200)"); printf("(TM3200)");
break; break;
skipping to change at line 6140 skipping to change at line 6619
{ "advanced cryptography engine (ACE)enabled", 7, 7, bools }, { "advanced cryptography engine (ACE)enabled", 7, 7, bools },
{ "montgomery multiplier/hash (ACE2)" , 8, 8, bools }, { "montgomery multiplier/hash (ACE2)" , 8, 8, bools },
{ "montgomery multiplier/hash (ACE2) enabled", 9, 9, bools }, { "montgomery multiplier/hash (ACE2) enabled", 9, 9, bools },
{ "padlock hash engine (PHE)" , 10, 10, bools }, { "padlock hash engine (PHE)" , 10, 10, bools },
{ "padlock hash engine (PHE) enabled" , 11, 11, bools }, { "padlock hash engine (PHE) enabled" , 11, 11, bools },
{ "padlock montgomery mult. (PMM)" , 12, 12, bools }, { "padlock montgomery mult. (PMM)" , 12, 12, bools },
{ "padlock montgomery mult. (PMM) enabled" , 13, 13, bools }, { "padlock montgomery mult. (PMM) enabled" , 13, 13, bools },
}; };
printf(" extended feature flags (0xc0000001/edx):\n"); printf(" extended feature flags (0xc0000001/edx):\n");
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 0); /* max_len => */ 0);
} }
static void static void
print_c0000002_eax(unsigned int value) print_c0000002_eax(unsigned int value)
{ {
// This information is from Juerg Haefliger. // This information is from Juerg Haefliger.
// TODO: figure out how to decode the rest of this // TODO: figure out how to decode the rest of this
static named_item names[] static named_item names[]
= { { "core temperature (degrees C)" , 8, 15, NIL_IMAGES }, = { { "core temperature (degrees C)" , 8, 15, NIL_IMAGES },
}; };
print_names(value, names, LENGTH(names, named_item), print_names(value, names, LENGTH(names),
/* max_len => */ 28); /* max_len => */ 28);
} }
static void static void
print_c0000002_ebx(unsigned int value) print_c0000002_ebx(unsigned int value)
{ {
// This information is from Juerg Haefliger. // This information is from Juerg Haefliger.
// TODO: figure out how to decode the rest of this // TODO: figure out how to decode the rest of this
printf(" input voltage (mV) = %d (0x%0x)\n", printf(" input voltage (mV) = %d (0x%0x)\n",
(BIT_EXTRACT_LE(value, 0, 8) << 4) + 700, (BIT_EXTRACT_LE(value, 0, 8) << 4) + 700,
skipping to change at line 6319 skipping to change at line 6798
} else if (IS_VENDOR_ID(words, "GenuineTMx86")) { } else if (IS_VENDOR_ID(words, "GenuineTMx86")) {
stash->vendor = VENDOR_TRANSMETA; stash->vendor = VENDOR_TRANSMETA;
} else if (IS_VENDOR_ID(words, "SiS SiS SiS ")) { } else if (IS_VENDOR_ID(words, "SiS SiS SiS ")) {
stash->vendor = VENDOR_SIS; stash->vendor = VENDOR_SIS;
} else if (IS_VENDOR_ID(words, "Geode by NSC")) { } else if (IS_VENDOR_ID(words, "Geode by NSC")) {
stash->vendor = VENDOR_NSC; stash->vendor = VENDOR_NSC;
} else if (IS_VENDOR_ID(words, "Vortex86 SoC")) { } else if (IS_VENDOR_ID(words, "Vortex86 SoC")) {
stash->vendor = VENDOR_VORTEX; stash->vendor = VENDOR_VORTEX;
} else if (IS_VENDOR_ID(words, "Genuine RDC")) { } else if (IS_VENDOR_ID(words, "Genuine RDC")) {
stash->vendor = VENDOR_RDC; stash->vendor = VENDOR_RDC;
} else if (IS_VENDOR_ID(words, "HygonGenuine")) {
stash->vendor = VENDOR_HYGON;
} }
} else if (reg == 1) { } else if (reg == 1) {
stash->val_1_eax = words[WORD_EAX]; stash->val_1_eax = words[WORD_EAX];
stash->val_1_ebx = words[WORD_EBX]; stash->val_1_ebx = words[WORD_EBX];
stash->val_1_ecx = words[WORD_ECX]; stash->val_1_ecx = words[WORD_ECX];
stash->val_1_edx = words[WORD_EDX]; stash->val_1_edx = words[WORD_EDX];
} else if (reg == 4) { } else if (reg == 4) {
stash->saw_4 = TRUE; stash->saw_4 = TRUE;
if (try == 0) { if (try == 0) {
stash->val_4_eax = words[WORD_EAX]; stash->val_4_eax = words[WORD_EAX];
} }
} else if (reg == 0xb) { } else if (reg == 0xb) {
stash->saw_b = TRUE; stash->saw_b = TRUE;
if (try < sizeof(stash->val_b_eax) / sizeof(stash->val_b_eax[0])) { if (try < LENGTH(stash->val_b_eax)) {
stash->val_b_eax[try] = words[WORD_EAX]; stash->val_b_eax[try] = words[WORD_EAX];
} }
if (try < sizeof(stash->val_b_ebx) / sizeof(stash->val_b_ebx[0])) { if (try < LENGTH(stash->val_b_ebx)) {
stash->val_b_ebx[try] = words[WORD_EBX]; stash->val_b_ebx[try] = words[WORD_EBX];
} }
} else if (reg == 0x1f) {
stash->saw_1f = TRUE;
if (try < LENGTH(stash->val_1f_eax)) {
stash->val_1f_eax[try] = words[WORD_EAX];
}
if (try < LENGTH(stash->val_1f_ebx)) {
stash->val_1f_ebx[try] = words[WORD_EBX];
}
if (try < LENGTH(stash->val_1f_ecx)) {
stash->val_1f_ecx[try] = words[WORD_ECX];
}
} else if (reg == 0x40000000) { } else if (reg == 0x40000000) {
if (IS_HYPERVISOR_ID(words, "VMwareVMware")) { if (IS_HYPERVISOR_ID(words, "VMwareVMware")) {
stash->hypervisor = HYPERVISOR_VMWARE; stash->hypervisor = HYPERVISOR_VMWARE;
} else if (IS_HYPERVISOR_ID(words, "XenVMMXenVMM")) { } else if (IS_HYPERVISOR_ID(words, "XenVMMXenVMM")) {
stash->hypervisor = HYPERVISOR_XEN; stash->hypervisor = HYPERVISOR_XEN;
} else if (IS_HYPERVISOR_ID(words, "KVMKVMKVM\0\0\0")) { } else if (IS_HYPERVISOR_ID(words, "KVMKVMKVM\0\0\0")) {
stash->hypervisor = HYPERVISOR_KVM; stash->hypervisor = HYPERVISOR_KVM;
} else if (IS_HYPERVISOR_ID(words, "Microsoft Hv")) { } else if (IS_HYPERVISOR_ID(words, "Microsoft Hv")) {
stash->hypervisor = HYPERVISOR_MICROSOFT; stash->hypervisor = HYPERVISOR_MICROSOFT;
} }
} else if (reg == 0x80000008) { } else if (reg == 0x80000008) {
stash->val_80000008_ecx = words[WORD_ECX]; stash->val_80000008_ecx = words[WORD_ECX];
} else if (reg == 0x8000001e) {
stash->val_8000001e_ebx = words[WORD_EBX];
} else if (reg == 0x80860003) { } else if (reg == 0x80860003) {
memcpy(&stash->transmeta_info[0], words, sizeof(unsigned int)*WORD_NUM); memcpy(&stash->transmeta_info[0], words, sizeof(unsigned int)*WORD_NUM);
} else if (reg == 0x80860004) { } else if (reg == 0x80860004) {
memcpy(&stash->transmeta_info[16], words, sizeof(unsigned int)*WORD_NUM); memcpy(&stash->transmeta_info[16], words, sizeof(unsigned int)*WORD_NUM);
} else if (reg == 0x80860005) { } else if (reg == 0x80860005) {
memcpy(&stash->transmeta_info[32], words, sizeof(unsigned int)*WORD_NUM); memcpy(&stash->transmeta_info[32], words, sizeof(unsigned int)*WORD_NUM);
} else if (reg == 0x80860006) { } else if (reg == 0x80860006) {
memcpy(&stash->transmeta_info[48], words, sizeof(unsigned int)*WORD_NUM); memcpy(&stash->transmeta_info[48], words, sizeof(unsigned int)*WORD_NUM);
} }
skipping to change at line 6489 skipping to change at line 6983
printf(" Conversion factor from IA32_QM_CTR to bytes = %u\n", printf(" Conversion factor from IA32_QM_CTR to bytes = %u\n",
words[WORD_EBX]); words[WORD_EBX]);
printf(" Maximum range of RMID = %u\n", printf(" Maximum range of RMID = %u\n",
words[WORD_ECX]); words[WORD_ECX]);
print_f_1_edx(words[WORD_EDX]); print_f_1_edx(words[WORD_EDX]);
} else { } else {
print_reg_raw(reg, try, words); print_reg_raw(reg, try, words);
} }
} else if (reg == 0x10) { } else if (reg == 0x10) {
if (try == 0) { if (try == 0) {
printf(" Resource Director Technology allocation (0x10/0):\n"); printf(" Resource Director Technology Allocation (0x10/0):\n");
print_10_0_ebx(words[WORD_EBX]); print_10_0_ebx(words[WORD_EBX]);
} else if (try == 1 || try == 2) { } else if (try == 1 || try == 2) {
if (try == 1) { if (try == 1) {
printf(" L3 Cache Allocation Technology (0x10/1):\n"); printf(" L3 Cache Allocation Technology (0x10/1):\n");
} else if (try == 2) { } else if (try == 2) {
printf(" L2 Cache Allocation Technology (0x10/2):\n"); printf(" L2 Cache Allocation Technology (0x10/2):\n");
} }
print_10_n_eax(words[WORD_EAX]); print_10_n_eax(words[WORD_EAX]);
printf(" Bit-granular map of isolation/contention = 0x%08x\n", printf(" Bit-granular map of isolation/contention = 0x%08x\n",
words[WORD_EBX]); words[WORD_EBX]);
print_10_n_ecx(words[WORD_ECX]); print_10_n_ecx(words[WORD_ECX]);
print_10_n_edx(words[WORD_EDX]); print_10_n_edx(words[WORD_EDX]);
} else if (try == 3) {
printf(" Memory Bandwidth Allocation (0x10/3):\n");
print_10_3_eax(words[WORD_EAX]);
print_10_3_ecx(words[WORD_ECX]);
print_10_n_edx(words[WORD_EDX]);
} else { } else {
print_reg_raw(reg, try, words); print_reg_raw(reg, try, words);
} }
} else if (reg == 0x12) { } else if (reg == 0x12) {
if (try == 0) { if (try == 0) {
printf(" Software Guard Extensions (SGX) capability (0x12/0):\n"); printf(" Software Guard Extensions (SGX) capability (0x12/0):\n");
print_12_0_eax(words[WORD_EAX]); print_12_0_eax(words[WORD_EAX]);
print_12_0_ebx(words[WORD_EBX]); print_12_0_ebx(words[WORD_EBX]);
print_12_0_edx(words[WORD_EDX]); print_12_0_edx(words[WORD_EDX]);
} else if (try == 1) { } else if (try == 1) {
skipping to change at line 6526 skipping to change at line 7025
words[WORD_ECX], words[WORD_ECX],
words[WORD_EBX], words[WORD_EBX],
words[WORD_EAX]); words[WORD_EAX]);
} else { } else {
if ((words[WORD_EAX] & 0xf) == 1) { if ((words[WORD_EAX] & 0xf) == 1) {
printf(" SGX EPC enumeration (0x12/n):\n"); printf(" SGX EPC enumeration (0x12/n):\n");
printf(" section physical address = 0x%08x%08x\n", printf(" section physical address = 0x%08x%08x\n",
words[WORD_EBX], words[WORD_EAX] & 0xfffff000); words[WORD_EBX], words[WORD_EAX] & 0xfffff000);
printf(" section size = 0x%08x%08x\n", printf(" section size = 0x%08x%08x\n",
words[WORD_EDX], words[WORD_ECX] & 0xfffff000); words[WORD_EDX], words[WORD_ECX] & 0xfffff000);
print_12_n_1_ecx(words[WORD_ECX]); print_12_n_ecx(words[WORD_ECX]);
} else { } else {
print_reg_raw(reg, try, words); print_reg_raw(reg, try, words);
} }
} }
} else if (reg == 0x14) { } else if (reg == 0x14) {
if (try == 0) { if (try == 0) {
printf(" Intel Processor Trace (0x14):\n"); printf(" Intel Processor Trace (0x14):\n");
print_14_0_ebx(words[WORD_EBX]); print_14_0_ebx(words[WORD_EBX]);
print_14_0_ecx(words[WORD_ECX]); print_14_0_ecx(words[WORD_ECX]);
} else if (try == 1) { } else if (try == 1) {
skipping to change at line 6554 skipping to change at line 7053
printf(" TSC/clock ratio = %u/%u\n", printf(" TSC/clock ratio = %u/%u\n",
words[WORD_EBX], words[WORD_EAX]); words[WORD_EBX], words[WORD_EAX]);
printf(" nominal core crystal clock = %u Hz\n", words[WORD_ECX]); printf(" nominal core crystal clock = %u Hz\n", words[WORD_ECX]);
} else if (reg == 0x16) { } else if (reg == 0x16) {
printf(" Processor Frequency Information (0x16):\n"); printf(" Processor Frequency Information (0x16):\n");
print_16_eax(words[WORD_EAX]); print_16_eax(words[WORD_EAX]);
print_16_ebx(words[WORD_EBX]); print_16_ebx(words[WORD_EBX]);
print_16_ecx(words[WORD_ECX]); print_16_ecx(words[WORD_ECX]);
} else if (reg == 0x17) { } else if (reg == 0x17) {
if (try == 0) { if (try == 0) {
printf(" system-on-chip vendor attribute (0x17/0):\n"); printf(" System-On-Chip Vendor Attribute (0x17/0):\n");
print_17_0_ebx(words[WORD_EBX]); print_17_0_ebx(words[WORD_EBX]);
printf(" project id = 0x%08x (%u)\n", printf(" project id = 0x%08x (%u)\n",
words[WORD_ECX], words[WORD_ECX]); words[WORD_ECX], words[WORD_ECX]);
printf(" stepping id = 0x%08x (%u)\n", printf(" stepping id = 0x%08x (%u)\n",
words[WORD_EDX], words[WORD_EDX]); words[WORD_EDX], words[WORD_EDX]);
} else if (try == 1) { } else if (try == 1) {
memcpy(&stash->soc_brand[0], words, sizeof(unsigned int)*WORD_NUM); memcpy(&stash->soc_brand[0], words, sizeof(unsigned int)*WORD_NUM);
} else if (try == 2) { } else if (try == 2) {
memcpy(&stash->soc_brand[16], words, sizeof(unsigned int)*WORD_NUM); memcpy(&stash->soc_brand[16], words, sizeof(unsigned int)*WORD_NUM);
} else if (try == 3) { } else if (try == 3) {
memcpy(&stash->soc_brand[32], words, sizeof(unsigned int)*WORD_NUM); memcpy(&stash->soc_brand[32], words, sizeof(unsigned int)*WORD_NUM);
printf(" SoC brand = \"%s\"\n", stash->soc_brand); printf(" SoC brand = \"%s\"\n", stash->soc_brand);
} else { } else {
print_reg_raw(reg, try, words); print_reg_raw(reg, try, words);
} }
} else if (reg == 0x18) { } else if (reg == 0x18) {
printf(" deterministic address translation parameters (0x18/0):\n"); printf(" Deterministic Address Translation Parameters (0x18/%d):\n",
try);
print_18_n_ebx(words[WORD_EBX]); print_18_n_ebx(words[WORD_EBX]);
printf(" number of sets = 0x%08x (%u)\n", printf(" number of sets = 0x%08x (%u)\n",
words[WORD_ECX], words[WORD_ECX]); words[WORD_ECX], words[WORD_ECX]);
print_18_n_edx(words[WORD_EDX]); print_18_n_edx(words[WORD_EDX]);
} else if (reg == 0x1a) {
printf(" Hybrid Information (0x1a/0)\n");
print_1a_0_eax(words[WORD_EAX]);
} else if (reg == 0x1b) { } else if (reg == 0x1b) {
printf(" PCONFIG information (0x1b/n):\n"); printf(" PCONFIG information (0x1b/n):\n");
print_1b_n_eax(words[WORD_EAX]); print_1b_n_eax(words[WORD_EAX]);
printf(" identifier of target %d = 0x%08x (%u)\n", printf(" identifier of target %d = 0x%08x (%u)\n",
3 * try + 1, words[WORD_EBX], words[WORD_EBX]); 3 * try + 1, words[WORD_EBX], words[WORD_EBX]);
printf(" identifier of target %d = 0x%08x (%u)\n", printf(" identifier of target %d = 0x%08x (%u)\n",
3 * try + 2, words[WORD_ECX], words[WORD_ECX]); 3 * try + 2, words[WORD_ECX], words[WORD_ECX]);
printf(" identifier of target %d = 0x%08x (%u)\n", printf(" identifier of target %d = 0x%08x (%u)\n",
3 * try + 3, words[WORD_EDX], words[WORD_EDX]); 3 * try + 3, words[WORD_EDX], words[WORD_EDX]);
} else if (reg == 0x1f) {
if (try == 0) {
// This is invariant across subleaves, so print it only once
printf(" x2APIC ID of logical processor = 0x%x (%u)\n",
words[WORD_EDX], words[WORD_EDX]);
}
printf(" --- level %d ---\n", try);
print_1f_ecx(words[WORD_ECX]);
print_1f_eax(words[WORD_EAX]);
print_1f_ebx(words[WORD_EBX]);
} else if (reg == 0x40000000) { } else if (reg == 0x40000000) {
// max already set to words[WORD_EAX] // max already set to words[WORD_EAX]
printf(" hypervisor_id = \"%-4.4s%-4.4s%-4.4s\"\n", printf(" hypervisor_id = \"%-4.4s%-4.4s%-4.4s\"\n",
(const char*)&words[WORD_EBX], (const char*)&words[WORD_EBX],
(const char*)&words[WORD_ECX], (const char*)&words[WORD_ECX],
(const char*)&words[WORD_EDX]); (const char*)&words[WORD_EDX]);
} else if (reg == 0x40000001 && stash->hypervisor == HYPERVISOR_XEN) { } else if (reg == 0x40000001 && stash->hypervisor == HYPERVISOR_XEN) {
printf(" hypervisor version (0x40000001/eax):\n"); printf(" hypervisor version (0x40000001/eax):\n");
printf(" version = %d.%d\n", printf(" version = %d.%d\n",
BIT_EXTRACT_LE(words[WORD_EAX], 16, 32), BIT_EXTRACT_LE(words[WORD_EAX], 16, 32),
BIT_EXTRACT_LE(words[WORD_EAX], 0, 16)); BIT_EXTRACT_LE(words[WORD_EAX], 0, 16));
} else if (reg == 0x40000001 && stash->hypervisor == HYPERVISOR_KVM) { } else if (reg == 0x40000001 && stash->hypervisor == HYPERVISOR_KVM) {
print_40000001_eax_kvm(words[WORD_EAX]); print_40000001_eax_kvm(words[WORD_EAX]);
print_40000001_edx_kvm(words[WORD_EAX]);
} else if (reg == 0x40000001 && stash->hypervisor == HYPERVISOR_MICROSOFT) { } else if (reg == 0x40000001 && stash->hypervisor == HYPERVISOR_MICROSOFT) {
printf(" hypervisor interface identification (0x40000001/eax):\n"); printf(" hypervisor interface identification (0x40000001/eax):\n");
printf(" version = \"%-4.4s\"\n", printf(" version = \"%-4.4s\"\n",
(const char*)&words[WORD_EAX]); (const char*)&words[WORD_EAX]);
} else if (reg == 0x40000002 && stash->hypervisor == HYPERVISOR_XEN) { } else if (reg == 0x40000002 && stash->hypervisor == HYPERVISOR_XEN) {
printf(" hypervisor features (0x40000002):\n"); printf(" hypervisor features (0x40000002):\n");
printf(" number of hypercall-transfer pages = 0x%0x (%u)\n", printf(" number of hypercall-transfer pages = 0x%0x (%u)\n",
words[WORD_EAX], words[WORD_EAX]); words[WORD_EAX], words[WORD_EAX]);
printf(" MSR base address = 0x%0x\n", printf(" MSR base address = 0x%0x\n",
words[WORD_EBX]); words[WORD_EBX]);
skipping to change at line 6622 skipping to change at line 7136
printf(" tsc mode = 0x%0x (%u)\n", printf(" tsc mode = 0x%0x (%u)\n",
words[WORD_EBX], words[WORD_EBX]); words[WORD_EBX], words[WORD_EBX]);
printf(" tsc frequency (kHz) = %u\n", printf(" tsc frequency (kHz) = %u\n",
words[WORD_ECX]); words[WORD_ECX]);
printf(" incarnation = 0x%0x (%u)\n", printf(" incarnation = 0x%0x (%u)\n",
words[WORD_EDX], words[WORD_EDX]); words[WORD_EDX], words[WORD_EDX]);
} else if (reg == 0x40000003 && stash->hypervisor == HYPERVISOR_XEN } else if (reg == 0x40000003 && stash->hypervisor == HYPERVISOR_XEN
&& try == 1) { && try == 1) {
unsigned long long vtsc_offset unsigned long long vtsc_offset
= ((unsigned long long)words[WORD_EAX] = ((unsigned long long)words[WORD_EAX]
+ ((unsigned long long)words[WORD_EAX] << 32)); + ((unsigned long long)words[WORD_EBX] << 32));
printf(" vtsc offset = 0x%0llx (%llu)\n", vtsc_offset, vtsc_offset) ; printf(" vtsc offset = 0x%0llx (%llu)\n", vtsc_offset, vtsc_offset) ;
printf(" vtsc mul_frac = 0x%0x (%u)\n", printf(" vtsc mul_frac = 0x%0x (%u)\n",
words[WORD_ECX], words[WORD_ECX]); words[WORD_ECX], words[WORD_ECX]);
printf(" vtsc shift = 0x%0x (%u)\n", printf(" vtsc shift = 0x%0x (%u)\n",
words[WORD_EDX], words[WORD_EDX]); words[WORD_EDX], words[WORD_EDX]);
} else if (reg == 0x40000003 && stash->hypervisor == HYPERVISOR_XEN } else if (reg == 0x40000003 && stash->hypervisor == HYPERVISOR_XEN
&& try == 2) { && try == 2) {
printf(" cpu frequency (kHZ) = %u\n", words[WORD_EAX]); printf(" cpu frequency (kHZ) = %u\n", words[WORD_EAX]);
} else if (reg == 0x40000002 && stash->hypervisor == HYPERVISOR_MICROSOFT) { } else if (reg == 0x40000002 && stash->hypervisor == HYPERVISOR_MICROSOFT) {
printf(" hypervisor system identity (0x40000002):\n"); printf(" hypervisor system identity (0x40000002):\n");
skipping to change at line 6647 skipping to change at line 7161
printf(" service pack = %d\n", words[WORD_ECX]); printf(" service pack = %d\n", words[WORD_ECX]);
printf(" service branch = %d\n", printf(" service branch = %d\n",
BIT_EXTRACT_LE(words[WORD_EDX], 24, 32)); BIT_EXTRACT_LE(words[WORD_EDX], 24, 32));
printf(" service number = %d\n", printf(" service number = %d\n",
BIT_EXTRACT_LE(words[WORD_EDX], 0, 24)); BIT_EXTRACT_LE(words[WORD_EDX], 0, 24));
} else if (reg == 0x40000003 && stash->hypervisor == HYPERVISOR_MICROSOFT) { } else if (reg == 0x40000003 && stash->hypervisor == HYPERVISOR_MICROSOFT) {
print_40000003_eax_microsoft(words[WORD_EAX]); print_40000003_eax_microsoft(words[WORD_EAX]);
print_40000003_ebx_microsoft(words[WORD_EBX]); print_40000003_ebx_microsoft(words[WORD_EBX]);
print_40000003_ecx_microsoft(words[WORD_ECX]); print_40000003_ecx_microsoft(words[WORD_ECX]);
print_40000003_edx_microsoft(words[WORD_EDX]); print_40000003_edx_microsoft(words[WORD_EDX]);
} else if (reg == 0x40000004 && stash->hypervisor == HYPERVISOR_XEN) {
print_40000004_eax_xen(words[WORD_EAX]);
printf(" vcpu id = 0x%x (%u)\n",
words[WORD_EBX], words[WORD_EBX]);
printf(" domain id = 0x%x (%u)\n",
words[WORD_ECX], words[WORD_ECX]);
} else if (reg == 0x40000004 && stash->hypervisor == HYPERVISOR_MICROSOFT) { } else if (reg == 0x40000004 && stash->hypervisor == HYPERVISOR_MICROSOFT) {
print_40000004_eax_microsoft(words[WORD_EAX]); print_40000004_eax_microsoft(words[WORD_EAX]);
printf(" maximum number of spinlock retry attempts = 0x%0x (%u)\n", printf(" maximum number of spinlock retry attempts = 0x%0x (%u)\n",
words[WORD_EBX], words[WORD_EBX]); words[WORD_EBX], words[WORD_EBX]);
} else if (reg == 0x40000005 && stash->hypervisor == HYPERVISOR_XEN
&& try == 0) {
print_40000005_0_ebx_xen(words[WORD_EBX]);
} else if (reg == 0x40000005 && stash->hypervisor == HYPERVISOR_MICROSOFT) { } else if (reg == 0x40000005 && stash->hypervisor == HYPERVISOR_MICROSOFT) {
printf(" hypervisor implementation limits (0x40000005):\n"); printf(" hypervisor implementation limits (0x40000005):\n");
printf(" maximum number of virtual processors " printf(" maximum number of virtual processors "
" = 0x%0x (%u)\n", " = 0x%0x (%u)\n",
words[WORD_EAX], words[WORD_EAX]); words[WORD_EAX], words[WORD_EAX]);
printf(" maximum number of logical processors " printf(" maximum number of logical processors "
" = 0x%0x (%u)\n", " = 0x%0x (%u)\n",
words[WORD_EBX], words[WORD_EBX]); words[WORD_EBX], words[WORD_EBX]);
printf(" maximum number of physical interrupt vectors for remapping" printf(" maximum number of physical interrupt vectors for remapping"
" = 0x%0x (%u)\n", " = 0x%0x (%u)\n",
skipping to change at line 6850 skipping to change at line 7373
** times. Insulate this tool from all that by calling the system ** times. Insulate this tool from all that by calling the system
** service directly. ** service directly.
*/ */
unsigned int mask[MAX_CPUS / (sizeof(unsigned int)*8)]; unsigned int mask[MAX_CPUS / (sizeof(unsigned int)*8)];
bzero(&mask, sizeof(mask)); bzero(&mask, sizeof(mask));
mask[cpu / (sizeof(unsigned int)*8)] mask[cpu / (sizeof(unsigned int)*8)]
= (1 << cpu % (sizeof(unsigned int)*8)); = (1 << cpu % (sizeof(unsigned int)*8));
int status; int status;
status = syscall(__NR_sched_setaffinity, 0, sizeof(mask), &mask); status = syscall(__NR_sched_setaffinity, 0, sizeof(mask), &mask);
#elif defined(__sun)
pthread_t thread = pthread_self();
int status = processor_bind(P_LWPID, thread, cpu, NULL);
#else #else
cpu_set_t cpuset; cpu_set_t cpuset;
CPU_ZERO(&cpuset); CPU_ZERO(&cpuset);
CPU_SET(cpu, &cpuset); CPU_SET(cpu, &cpuset);
int status; int status;
status = sched_setaffinity(0, sizeof(cpu_set_t), &cpuset); status = sched_setaffinity(0, sizeof(cpu_set_t), &cpuset);
#endif #endif
if (status == -1) { if (status == -1) {
if (cpu > 0) { if (cpu > 0) {
if (errno == EINVAL) return -1; if (errno == EINVAL) return -1;
skipping to change at line 7045 skipping to change at line 7571
} }
return TRUE; return TRUE;
} }
static void static void
print_header (unsigned int reg, print_header (unsigned int reg,
unsigned int try, unsigned int try,
boolean raw) boolean raw)
{ {
if (!raw && try == 0) { if (!raw) {
if (reg == 2) { if (reg == 2 && try == 0) {
printf(" cache and TLB information (2):\n"); printf(" cache and TLB information (2):\n");
} else if (reg == 4) { } else if (reg == 4 && try == 0) {
printf(" deterministic cache parameters (4):\n"); printf(" deterministic cache parameters (4):\n");
} else if (reg == 7) { } else if (reg == 7 && try == 0) {
printf(" extended feature flags (7):\n"); printf(" extended feature flags (7):\n");
} else if (reg == 0xb) { } else if (reg == 0xb && try == 0) {
printf(" x2APIC features / processor topology (0xb):\n"); printf(" x2APIC features / processor topology (0xb):\n");
} else if (reg == 0x1f && try == 0) {
printf(" V2 extended topology (0x1f):\n");
} else if (reg == 0x40000003 && try == 0) { } else if (reg == 0x40000003 && try == 0) {
printf(" hypervisor time features (0x40000003/00):\n"); printf(" hypervisor time features (0x40000003/00):\n");
} else if (reg == 0x40000003 && try == 1) { } else if (reg == 0x40000003 && try == 1) {
printf(" hypervisor time scale & offset (0x40000003/01):\n"); printf(" hypervisor time scale & offset (0x40000003/01):\n");
} else if (reg == 0x40000003 && try == 2) { } else if (reg == 0x40000003 && try == 2) {
printf(" hypervisor time physical cpu frequency (0x40000003/02):\n"); printf(" hypervisor time physical cpu frequency (0x40000003/02):\n");
} else if (reg == 0x8000001d) { } else if (reg == 0x8000001d && try == 0) {
printf(" Cache Properties (0x8000001d):\n"); printf(" Cache Properties (0x8000001d):\n");
} }
} }
} }
static void static void
do_real_one(unsigned int reg, do_real_one(unsigned int reg,
unsigned int try, unsigned int try,
boolean one_cpu, boolean one_cpu,
boolean inst, boolean inst,
boolean raw, boolean raw,
boolean debug) boolean debug UNUSED)
{ {
unsigned int cpu; unsigned int cpu;
for (cpu = 0;; cpu++) { for (cpu = 0;; cpu++) {
int cpuid_fd = -1; int cpuid_fd = -1;
code_stash_t stash = NIL_STASH; code_stash_t stash = NIL_STASH;
if (one_cpu && cpu > 0) break; if (one_cpu && cpu > 0) break;
cpuid_fd = real_setup(cpu, one_cpu, inst); cpuid_fd = real_setup(cpu, one_cpu, inst);
skipping to change at line 7273 skipping to change at line 7801
for (;;) { for (;;) {
print_header(reg, try, raw); print_header(reg, try, raw);
print_reg(reg, words, raw, try, &stash); print_reg(reg, words, raw, try, &stash);
if (try == 0) { if (try == 0) {
max_tries = words[WORD_EAX]; max_tries = words[WORD_EAX];
} }
try++; try++;
if (try > max_tries) break; if (try > max_tries) break;
real_get(cpuid_fd, reg, words, try, FALSE); real_get(cpuid_fd, reg, words, try, FALSE);
} }
} else if (reg == 0x1f) {
print_header(reg, 0, raw);
print_reg(reg, words, raw, 0, &stash);
unsigned int try;
for (try = 1; try < 256; try++) {
real_get(cpuid_fd, reg, words, try, FALSE);
print_reg(reg, words, raw, try, &stash);
if (BIT_EXTRACT_LE(words[WORD_ECX], 8, 16) == 0) break;
}
} else { } else {
print_reg(reg, words, raw, 0, &stash); print_reg(reg, words, raw, 0, &stash);
} }
} }
if (BIT_EXTRACT_LE(stash.val_1_ecx, 31, 32)) { if (BIT_EXTRACT_LE(stash.val_1_ecx, 31, 32)) {
max = 0x40000000; max = 0x40000000;
for (reg = 0x40000000; reg <= max; reg++) { for (reg = 0x40000000; reg <= max; reg++) {
boolean success; boolean success;
unsigned int words[WORD_NUM]; unsigned int words[WORD_NUM];
success = real_get(cpuid_fd, reg, words, 0, TRUE); success = real_get(cpuid_fd, reg, words, 0, TRUE);
if (!success) break; if (!success) break;
if (reg == 0x40000000) { if (reg == 0x40000000) {
max = words[WORD_EAX]; max = words[WORD_EAX];
} }
if (reg == 0x40000003 && stash.hypervisor == HYPERVISOR_XEN) { if (reg == 0x40000003 && stash.hypervisor == HYPERVISOR_XEN) {
unsigned int try = 0; unsigned int try = 0;
for (; try <= 2; try++) { while (try <= 2) {
print_header(reg, try, raw); print_header(reg, try, raw);
print_reg(reg, words, raw, try, &stash); print_reg(reg, words, raw, try, &stash);
try++; try++;
real_get(cpuid_fd, reg, words, try, FALSE); real_get(cpuid_fd, reg, words, try, FALSE);
} }
} else { } else {
print_reg(reg, words, raw, 0, &stash); print_reg(reg, words, raw, 0, &stash);
} }
if (reg == 0x40000000 if (reg == 0x40000000
skipping to change at line 7427 skipping to change at line 7964
} }
while (!feof(file)) { while (!feof(file)) {
char buffer[88]; char buffer[88];
char* ptr; char* ptr;
int status; int status;
unsigned int reg; unsigned int reg;
unsigned int try; unsigned int try;
unsigned int words[WORD_NUM]; unsigned int words[WORD_NUM];
ptr = fgets(buffer, LENGTH(buffer, char), file); ptr = fgets(buffer, LENGTH(buffer), file);
if (ptr == NULL && errno == 0) break; if (ptr == NULL && errno == 0) break;
if (ptr == NULL) { if (ptr == NULL) {
if (errno != EPIPE) { if (errno != EPIPE) {
fprintf(stderr, fprintf(stderr,
"%s: unable to read a line of text from %s;" "%s: unable to read a line of text from %s;"
" errno = %d (%s)\n", " errno = %d (%s)\n",
program, filename, errno, strerror(errno)); program, filename, errno, strerror(errno));
} }
exit(1); exit(1);
} }
skipping to change at line 7567 skipping to change at line 8104
int longindex; int longindex;
int opt = getopt_long(argc, argv, shortopts, longopts, &longindex); int opt = getopt_long(argc, argv, shortopts, longopts, &longindex);
if (opt == EOF) break; if (opt == EOF) break;
switch (opt) { switch (opt) {
case 'h': case 'h':
case 'H': case 'H':
usage(); usage();
/*NOTREACHED*/ /*NOTREACHED*/
break;
case '1': case '1':
opt_one_cpu = TRUE; opt_one_cpu = TRUE;
break; break;
case 'i': case 'i':
opt_inst = TRUE; opt_inst = TRUE;
break; break;
case 'k': case 'k':
opt_kernel = TRUE; opt_kernel = TRUE;
break; break;
case 'r': case 'r':
skipping to change at line 7620 skipping to change at line 8158
"%s: argument to -s/--subleaf not understood: %s\n", "%s: argument to -s/--subleaf not understood: %s\n",
program, argv[optind-1]); program, argv[optind-1]);
exit(1); exit(1);
} }
} }
break; break;
case '?': case '?':
default: default:
if (optopt == '\0') { if (optopt == '\0') {
fprintf(stderr, fprintf(stderr,
"%s: unrecogized option: %s\n", program, argv[optind-1]); "%s: unrecognized option: %s\n", program, argv[optind-1]);
} else { } else {
fprintf(stderr, fprintf(stderr,
"%s: unrecognized option letter: %c\n", program, optopt); "%s: unrecognized option letter: %c\n", program, optopt);
} }
usage(); usage();
/*NOTREACHED*/ /*NOTREACHED*/
} }
} }
if (optind < argc) { if (optind < argc) {
 End of changes. 249 change blocks. 
703 lines changed or deleted 1344 lines changed or added

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