"Fossies" - the Fresh Open Source Software Archive  

Source code changes of the file "lib/Basic/Targets/X86.cpp" between
cfe-8.0.1.src.tar.xz and cfe-9.0.0.src.tar.xz

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X86.cpp  (cfe-8.0.1.src.tar.xz):X86.cpp  (cfe-9.0.0.src.tar.xz)
//===--- X86.cpp - Implement X86 target feature support -------------------===// //===--- X86.cpp - Implement X86 target feature support -------------------===//
// //
// The LLVM Compiler Infrastructure // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// // See https://llvm.org/LICENSE.txt for license information.
// This file is distributed under the University of Illinois Open Source // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file implements X86 TargetInfo objects. // This file implements X86 TargetInfo objects.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "X86.h" #include "X86.h"
#include "clang/Basic/Builtins.h" #include "clang/Basic/Builtins.h"
#include "clang/Basic/Diagnostic.h" #include "clang/Basic/Diagnostic.h"
skipping to change at line 119 skipping to change at line 118
// X86_64 always has SSE2. // X86_64 always has SSE2.
if (getTriple().getArch() == llvm::Triple::x86_64) if (getTriple().getArch() == llvm::Triple::x86_64)
setFeatureEnabledImpl(Features, "sse2", true); setFeatureEnabledImpl(Features, "sse2", true);
const CPUKind Kind = getCPUKind(CPU); const CPUKind Kind = getCPUKind(CPU);
// Enable X87 for all X86 processors but Lakemont. // Enable X87 for all X86 processors but Lakemont.
if (Kind != CK_Lakemont) if (Kind != CK_Lakemont)
setFeatureEnabledImpl(Features, "x87", true); setFeatureEnabledImpl(Features, "x87", true);
// Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards
// compatibility.
if (Kind >= CK_i586 || Kind == CK_Generic)
setFeatureEnabledImpl(Features, "cx8", true);
switch (Kind) { switch (Kind) {
case CK_Generic: case CK_Generic:
case CK_i386: case CK_i386:
case CK_i486: case CK_i486:
case CK_i586: case CK_i586:
case CK_Pentium: case CK_Pentium:
case CK_PentiumPro: case CK_PentiumPro:
case CK_i686:
case CK_Lakemont: case CK_Lakemont:
break; break;
case CK_PentiumMMX: case CK_PentiumMMX:
case CK_Pentium2: case CK_Pentium2:
case CK_K6: case CK_K6:
case CK_WinChipC6: case CK_WinChipC6:
setFeatureEnabledImpl(Features, "mmx", true); setFeatureEnabledImpl(Features, "mmx", true);
break; break;
case CK_Cooperlake:
// CPX inherits all CLX features plus AVX512BF16
setFeatureEnabledImpl(Features, "avx512bf16", true);
LLVM_FALLTHROUGH;
case CK_Cascadelake:
// CLX inherits all SKX features plus AVX512VNNI
setFeatureEnabledImpl(Features, "avx512vnni", true);
LLVM_FALLTHROUGH;
case CK_SkylakeServer:
setFeatureEnabledImpl(Features, "avx512f", true);
setFeatureEnabledImpl(Features, "avx512cd", true);
setFeatureEnabledImpl(Features, "avx512dq", true);
setFeatureEnabledImpl(Features, "avx512bw", true);
setFeatureEnabledImpl(Features, "avx512vl", true);
setFeatureEnabledImpl(Features, "clwb", true);
setFeatureEnabledImpl(Features, "pku", true);
// SkylakeServer cores inherits all SKL features, except SGX
goto SkylakeCommon;
case CK_IcelakeServer: case CK_IcelakeServer:
setFeatureEnabledImpl(Features, "pconfig", true); setFeatureEnabledImpl(Features, "pconfig", true);
setFeatureEnabledImpl(Features, "wbnoinvd", true); setFeatureEnabledImpl(Features, "wbnoinvd", true);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case CK_IcelakeClient: case CK_IcelakeClient:
setFeatureEnabledImpl(Features, "vaes", true); setFeatureEnabledImpl(Features, "vaes", true);
setFeatureEnabledImpl(Features, "gfni", true); setFeatureEnabledImpl(Features, "gfni", true);
setFeatureEnabledImpl(Features, "vpclmulqdq", true); setFeatureEnabledImpl(Features, "vpclmulqdq", true);
setFeatureEnabledImpl(Features, "avx512bitalg", true); setFeatureEnabledImpl(Features, "avx512bitalg", true);
setFeatureEnabledImpl(Features, "avx512vbmi2", true); setFeatureEnabledImpl(Features, "avx512vbmi2", true);
setFeatureEnabledImpl(Features, "avx512vnni", true);
setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
setFeatureEnabledImpl(Features, "rdpid", true); setFeatureEnabledImpl(Features, "rdpid", true);
setFeatureEnabledImpl(Features, "clwb", true);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case CK_Cannonlake: case CK_Cannonlake:
setFeatureEnabledImpl(Features, "avx512ifma", true);
setFeatureEnabledImpl(Features, "avx512vbmi", true);
setFeatureEnabledImpl(Features, "sha", true);
LLVM_FALLTHROUGH;
case CK_Cascadelake:
//Cannonlake has no VNNI feature inside while Icelake has
if (Kind != CK_Cannonlake)
// CLK inherits all SKX features plus AVX512_VNNI
setFeatureEnabledImpl(Features, "avx512vnni", true);
LLVM_FALLTHROUGH;
case CK_SkylakeServer:
setFeatureEnabledImpl(Features, "avx512f", true); setFeatureEnabledImpl(Features, "avx512f", true);
setFeatureEnabledImpl(Features, "avx512cd", true); setFeatureEnabledImpl(Features, "avx512cd", true);
setFeatureEnabledImpl(Features, "avx512dq", true); setFeatureEnabledImpl(Features, "avx512dq", true);
setFeatureEnabledImpl(Features, "avx512bw", true); setFeatureEnabledImpl(Features, "avx512bw", true);
setFeatureEnabledImpl(Features, "avx512vl", true); setFeatureEnabledImpl(Features, "avx512vl", true);
setFeatureEnabledImpl(Features, "avx512ifma", true);
setFeatureEnabledImpl(Features, "avx512vbmi", true);
setFeatureEnabledImpl(Features, "pku", true); setFeatureEnabledImpl(Features, "pku", true);
if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB setFeatureEnabledImpl(Features, "sha", true);
setFeatureEnabledImpl(Features, "clwb", true);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case CK_SkylakeClient: case CK_SkylakeClient:
setFeatureEnabledImpl(Features, "sgx", true);
// SkylakeServer cores inherits all SKL features, except SGX
SkylakeCommon:
setFeatureEnabledImpl(Features, "xsavec", true); setFeatureEnabledImpl(Features, "xsavec", true);
setFeatureEnabledImpl(Features, "xsaves", true); setFeatureEnabledImpl(Features, "xsaves", true);
setFeatureEnabledImpl(Features, "mpx", true); setFeatureEnabledImpl(Features, "mpx", true);
if (Kind != CK_SkylakeServer
&& Kind != CK_Cascadelake)
// SKX/CLX inherits all SKL features, except SGX
setFeatureEnabledImpl(Features, "sgx", true);
setFeatureEnabledImpl(Features, "clflushopt", true); setFeatureEnabledImpl(Features, "clflushopt", true);
setFeatureEnabledImpl(Features, "aes", true); setFeatureEnabledImpl(Features, "aes", true);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case CK_Broadwell: case CK_Broadwell:
setFeatureEnabledImpl(Features, "rdseed", true); setFeatureEnabledImpl(Features, "rdseed", true);
setFeatureEnabledImpl(Features, "adx", true); setFeatureEnabledImpl(Features, "adx", true);
setFeatureEnabledImpl(Features, "prfchw", true); setFeatureEnabledImpl(Features, "prfchw", true);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case CK_Haswell: case CK_Haswell:
setFeatureEnabledImpl(Features, "avx2", true); setFeatureEnabledImpl(Features, "avx2", true);
skipping to change at line 218 skipping to change at line 233
case CK_Nehalem: case CK_Nehalem:
setFeatureEnabledImpl(Features, "sse4.2", true); setFeatureEnabledImpl(Features, "sse4.2", true);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case CK_Penryn: case CK_Penryn:
setFeatureEnabledImpl(Features, "sse4.1", true); setFeatureEnabledImpl(Features, "sse4.1", true);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case CK_Core2: case CK_Core2:
setFeatureEnabledImpl(Features, "ssse3", true); setFeatureEnabledImpl(Features, "ssse3", true);
setFeatureEnabledImpl(Features, "sahf", true); setFeatureEnabledImpl(Features, "sahf", true);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case CK_Nocona:
setFeatureEnabledImpl(Features, "cx16", true);
LLVM_FALLTHROUGH;
case CK_Yonah: case CK_Yonah:
case CK_Prescott: case CK_Prescott:
case CK_Nocona:
setFeatureEnabledImpl(Features, "sse3", true); setFeatureEnabledImpl(Features, "sse3", true);
setFeatureEnabledImpl(Features, "cx16", true);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case CK_PentiumM: case CK_PentiumM:
case CK_Pentium4: case CK_Pentium4:
case CK_x86_64: case CK_x86_64:
setFeatureEnabledImpl(Features, "sse2", true); setFeatureEnabledImpl(Features, "sse2", true);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case CK_Pentium3: case CK_Pentium3:
case CK_C3_2: case CK_C3_2:
setFeatureEnabledImpl(Features, "sse", true); setFeatureEnabledImpl(Features, "sse", true);
setFeatureEnabledImpl(Features, "fxsr", true); setFeatureEnabledImpl(Features, "fxsr", true);
skipping to change at line 351 skipping to change at line 367
setFeatureEnabledImpl(Features, "ssse3", true); setFeatureEnabledImpl(Features, "ssse3", true);
setFeatureEnabledImpl(Features, "sse4a", true); setFeatureEnabledImpl(Features, "sse4a", true);
setFeatureEnabledImpl(Features, "lzcnt", true); setFeatureEnabledImpl(Features, "lzcnt", true);
setFeatureEnabledImpl(Features, "popcnt", true); setFeatureEnabledImpl(Features, "popcnt", true);
setFeatureEnabledImpl(Features, "prfchw", true); setFeatureEnabledImpl(Features, "prfchw", true);
setFeatureEnabledImpl(Features, "cx16", true); setFeatureEnabledImpl(Features, "cx16", true);
setFeatureEnabledImpl(Features, "fxsr", true); setFeatureEnabledImpl(Features, "fxsr", true);
setFeatureEnabledImpl(Features, "sahf", true); setFeatureEnabledImpl(Features, "sahf", true);
break; break;
case CK_ZNVER2:
setFeatureEnabledImpl(Features, "clwb", true);
setFeatureEnabledImpl(Features, "rdpid", true);
setFeatureEnabledImpl(Features, "wbnoinvd", true);
LLVM_FALLTHROUGH;
case CK_ZNVER1: case CK_ZNVER1:
setFeatureEnabledImpl(Features, "adx", true); setFeatureEnabledImpl(Features, "adx", true);
setFeatureEnabledImpl(Features, "aes", true); setFeatureEnabledImpl(Features, "aes", true);
setFeatureEnabledImpl(Features, "avx2", true); setFeatureEnabledImpl(Features, "avx2", true);
setFeatureEnabledImpl(Features, "bmi", true); setFeatureEnabledImpl(Features, "bmi", true);
setFeatureEnabledImpl(Features, "bmi2", true); setFeatureEnabledImpl(Features, "bmi2", true);
setFeatureEnabledImpl(Features, "clflushopt", true); setFeatureEnabledImpl(Features, "clflushopt", true);
setFeatureEnabledImpl(Features, "clzero", true); setFeatureEnabledImpl(Features, "clzero", true);
setFeatureEnabledImpl(Features, "cx16", true); setFeatureEnabledImpl(Features, "cx16", true);
setFeatureEnabledImpl(Features, "f16c", true); setFeatureEnabledImpl(Features, "f16c", true);
skipping to change at line 419 skipping to change at line 440
} }
if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
return false; return false;
// Can't do this earlier because we need to be able to explicitly enable // Can't do this earlier because we need to be able to explicitly enable
// or disable these features and the things that they depend upon. // or disable these features and the things that they depend upon.
// Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
auto I = Features.find("sse4.2"); auto I = Features.find("sse4.2");
if (I != Features.end() && I->getValue() && if (I != Features.end() && I->getValue() &&
std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end())
FeaturesVec.end())
Features["popcnt"] = true; Features["popcnt"] = true;
// Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
I = Features.find("3dnow"); I = Features.find("3dnow");
if (I != Features.end() && I->getValue() && if (I != Features.end() && I->getValue() &&
std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == llvm::find(FeaturesVec, "-prfchw") == FeaturesVec.end())
FeaturesVec.end())
Features["prfchw"] = true; Features["prfchw"] = true;
// Additionally, if SSE is enabled and mmx is not explicitly disabled, // Additionally, if SSE is enabled and mmx is not explicitly disabled,
// then enable MMX. // then enable MMX.
I = Features.find("sse"); I = Features.find("sse");
if (I != Features.end() && I->getValue() && if (I != Features.end() && I->getValue() &&
std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end())
FeaturesVec.end())
Features["mmx"] = true; Features["mmx"] = true;
return true; return true;
} }
void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
X86SSEEnum Level, bool Enabled) { X86SSEEnum Level, bool Enabled) {
if (Enabled) { if (Enabled) {
switch (Level) { switch (Level) {
case AVX512F: case AVX512F:
Features["avx512f"] = Features["fma"] = Features["f16c"] = true; Features["avx512f"] = true;
Features["fma"] = true;
Features["f16c"] = true;
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case AVX2: case AVX2:
Features["avx2"] = true; Features["avx2"] = true;
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case AVX: case AVX:
Features["avx"] = true; Features["avx"] = true;
Features["xsave"] = true; Features["xsave"] = true;
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case SSE42: case SSE42:
Features["sse4.2"] = true; Features["sse4.2"] = true;
skipping to change at line 485 skipping to change at line 505
} }
return; return;
} }
switch (Level) { switch (Level) {
case NoSSE: case NoSSE:
case SSE1: case SSE1:
Features["sse"] = false; Features["sse"] = false;
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case SSE2: case SSE2:
Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = Features["sse2"] = Features["pclmul"] = Features["aes"] = false;
Features["gfni"] = false; Features["sha"] = Features["gfni"] = false;
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case SSE3: case SSE3:
Features["sse3"] = false; Features["sse3"] = false;
setXOPLevel(Features, NoXOP, false); setXOPLevel(Features, NoXOP, false);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case SSSE3: case SSSE3:
Features["ssse3"] = false; Features["ssse3"] = false;
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case SSE41: case SSE41:
Features["sse4.1"] = false; Features["sse4.1"] = false;
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case SSE42: case SSE42:
Features["sse4.2"] = false; Features["sse4.2"] = false;
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case AVX: case AVX:
Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = Features["fma"] = Features["avx"] = Features["f16c"] = false;
Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false Features["xsave"] = Features["xsaveopt"] = Features["vaes"] = false;
; Features["vpclmulqdq"] = false;
setXOPLevel(Features, FMA4, false); setXOPLevel(Features, FMA4, false);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case AVX2: case AVX2:
Features["avx2"] = false; Features["avx2"] = false;
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case AVX512F: case AVX512F:
Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = false;
Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = false;
Features["avx512vl"] = Features["avx512vbmi"] = Features["avx512vl"] = Features["avx512vbmi"] = false;
Features["avx512ifma"] = Features["avx512vpopcntdq"] = Features["avx512ifma"] = Features["avx512vpopcntdq"] = false;
Features["avx512bitalg"] = Features["avx512vnni"] = Features["avx512bitalg"] = Features["avx512vnni"] = false;
Features["avx512vbmi2"] = false; Features["avx512vbmi2"] = Features["avx512bf16"] = false;
Features["avx512vp2intersect"] = false;
break; break;
} }
} }
void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
MMX3DNowEnum Level, bool Enabled) { MMX3DNowEnum Level, bool Enabled) {
if (Enabled) { if (Enabled) {
switch (Level) { switch (Level) {
case AMD3DNowAthlon: case AMD3DNowAthlon:
Features["3dnowa"] = true; Features["3dnowa"] = true;
skipping to change at line 643 skipping to change at line 665
} }
} else if (Name == "gfni") { } else if (Name == "gfni") {
if (Enabled) if (Enabled)
setSSELevel(Features, SSE2, Enabled); setSSELevel(Features, SSE2, Enabled);
} else if (Name == "avx") { } else if (Name == "avx") {
setSSELevel(Features, AVX, Enabled); setSSELevel(Features, AVX, Enabled);
} else if (Name == "avx2") { } else if (Name == "avx2") {
setSSELevel(Features, AVX2, Enabled); setSSELevel(Features, AVX2, Enabled);
} else if (Name == "avx512f") { } else if (Name == "avx512f") {
setSSELevel(Features, AVX512F, Enabled); setSSELevel(Features, AVX512F, Enabled);
} else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || } else if (Name.startswith("avx512")) {
Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
Name == "avx512vbmi" || Name == "avx512ifma" ||
Name == "avx512vpopcntdq" || Name == "avx512bitalg" ||
Name == "avx512vnni" || Name == "avx512vbmi2") {
if (Enabled) if (Enabled)
setSSELevel(Features, AVX512F, Enabled); setSSELevel(Features, AVX512F, Enabled);
// Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled. // Enable BWI instruction if certain features are being enabled.
if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled) if ((Name == "avx512vbmi" || Name == "avx512vbmi2" ||
Name == "avx512bitalg" || Name == "avx512bf16") && Enabled)
Features["avx512bw"] = true; Features["avx512bw"] = true;
// Also disable VBMI/VBMI2/BITALG if BWI is being disabled. // Also disable some features if BWI is being disabled.
if (Name == "avx512bw" && !Enabled) if (Name == "avx512bw" && !Enabled) {
Features["avx512vbmi"] = Features["avx512vbmi2"] = Features["avx512vbmi"] = false;
Features["avx512vbmi2"] = false;
Features["avx512bitalg"] = false; Features["avx512bitalg"] = false;
Features["avx512bf16"] = false;
}
} else if (Name == "fma") { } else if (Name == "fma") {
if (Enabled) if (Enabled)
setSSELevel(Features, AVX, Enabled); setSSELevel(Features, AVX, Enabled);
else else
setSSELevel(Features, AVX512F, Enabled); setSSELevel(Features, AVX512F, Enabled);
} else if (Name == "fma4") { } else if (Name == "fma4") {
setXOPLevel(Features, FMA4, Enabled); setXOPLevel(Features, FMA4, Enabled);
} else if (Name == "xop") { } else if (Name == "xop") {
setXOPLevel(Features, XOP, Enabled); setXOPLevel(Features, XOP, Enabled);
} else if (Name == "sse4a") { } else if (Name == "sse4a") {
skipping to change at line 746 skipping to change at line 768
} else if (Feature == "+f16c") { } else if (Feature == "+f16c") {
HasF16C = true; HasF16C = true;
} else if (Feature == "+gfni") { } else if (Feature == "+gfni") {
HasGFNI = true; HasGFNI = true;
} else if (Feature == "+avx512cd") { } else if (Feature == "+avx512cd") {
HasAVX512CD = true; HasAVX512CD = true;
} else if (Feature == "+avx512vpopcntdq") { } else if (Feature == "+avx512vpopcntdq") {
HasAVX512VPOPCNTDQ = true; HasAVX512VPOPCNTDQ = true;
} else if (Feature == "+avx512vnni") { } else if (Feature == "+avx512vnni") {
HasAVX512VNNI = true; HasAVX512VNNI = true;
} else if (Feature == "+avx512bf16") {
HasAVX512BF16 = true;
} else if (Feature == "+avx512er") { } else if (Feature == "+avx512er") {
HasAVX512ER = true; HasAVX512ER = true;
} else if (Feature == "+avx512pf") { } else if (Feature == "+avx512pf") {
HasAVX512PF = true; HasAVX512PF = true;
} else if (Feature == "+avx512dq") { } else if (Feature == "+avx512dq") {
HasAVX512DQ = true; HasAVX512DQ = true;
} else if (Feature == "+avx512bitalg") { } else if (Feature == "+avx512bitalg") {
HasAVX512BITALG = true; HasAVX512BITALG = true;
} else if (Feature == "+avx512bw") { } else if (Feature == "+avx512bw") {
HasAVX512BW = true; HasAVX512BW = true;
} else if (Feature == "+avx512vl") { } else if (Feature == "+avx512vl") {
HasAVX512VL = true; HasAVX512VL = true;
} else if (Feature == "+avx512vbmi") { } else if (Feature == "+avx512vbmi") {
HasAVX512VBMI = true; HasAVX512VBMI = true;
} else if (Feature == "+avx512vbmi2") { } else if (Feature == "+avx512vbmi2") {
HasAVX512VBMI2 = true; HasAVX512VBMI2 = true;
} else if (Feature == "+avx512ifma") { } else if (Feature == "+avx512ifma") {
HasAVX512IFMA = true; HasAVX512IFMA = true;
} else if (Feature == "+avx512vp2intersect") {
HasAVX512VP2INTERSECT = true;
} else if (Feature == "+sha") { } else if (Feature == "+sha") {
HasSHA = true; HasSHA = true;
} else if (Feature == "+mpx") { } else if (Feature == "+mpx") {
HasMPX = true; HasMPX = true;
} else if (Feature == "+shstk") { } else if (Feature == "+shstk") {
HasSHSTK = true; HasSHSTK = true;
} else if (Feature == "+movbe") { } else if (Feature == "+movbe") {
HasMOVBE = true; HasMOVBE = true;
} else if (Feature == "+sgx") { } else if (Feature == "+sgx") {
HasSGX = true; HasSGX = true;
} else if (Feature == "+cx8") {
HasCX8 = true;
} else if (Feature == "+cx16") { } else if (Feature == "+cx16") {
HasCX16 = true; HasCX16 = true;
} else if (Feature == "+fxsr") { } else if (Feature == "+fxsr") {
HasFXSR = true; HasFXSR = true;
} else if (Feature == "+xsave") { } else if (Feature == "+xsave") {
HasXSAVE = true; HasXSAVE = true;
} else if (Feature == "+xsaveopt") { } else if (Feature == "+xsaveopt") {
HasXSAVEOPT = true; HasXSAVEOPT = true;
} else if (Feature == "+xsavec") { } else if (Feature == "+xsavec") {
HasXSAVEC = true; HasXSAVEC = true;
skipping to change at line 820 skipping to change at line 848
} else if (Feature == "+movdiri") { } else if (Feature == "+movdiri") {
HasMOVDIRI = true; HasMOVDIRI = true;
} else if (Feature == "+movdir64b") { } else if (Feature == "+movdir64b") {
HasMOVDIR64B = true; HasMOVDIR64B = true;
} else if (Feature == "+pconfig") { } else if (Feature == "+pconfig") {
HasPCONFIG = true; HasPCONFIG = true;
} else if (Feature == "+ptwrite") { } else if (Feature == "+ptwrite") {
HasPTWRITE = true; HasPTWRITE = true;
} else if (Feature == "+invpcid") { } else if (Feature == "+invpcid") {
HasINVPCID = true; HasINVPCID = true;
} else if (Feature == "+enqcmd") {
HasENQCMD = true;
} }
X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
.Case("+avx512f", AVX512F) .Case("+avx512f", AVX512F)
.Case("+avx2", AVX2) .Case("+avx2", AVX2)
.Case("+avx", AVX) .Case("+avx", AVX)
.Case("+sse4.2", SSE42) .Case("+sse4.2", SSE42)
.Case("+sse4.1", SSE41) .Case("+sse4.1", SSE41)
.Case("+ssse3", SSSE3) .Case("+ssse3", SSSE3)
.Case("+sse3", SSE3) .Case("+sse3", SSE3)
skipping to change at line 868 skipping to change at line 898
SimdDefaultAlign = SimdDefaultAlign =
hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
return true; return true;
} }
/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
/// definitions for this particular subtarget. /// definitions for this particular subtarget.
void X86TargetInfo::getTargetDefines(const LangOptions &Opts, void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const { MacroBuilder &Builder) const {
// Inline assembly supports X86 flag outputs.
Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
std::string CodeModel = getTargetOpts().CodeModel; std::string CodeModel = getTargetOpts().CodeModel;
if (CodeModel == "default") if (CodeModel == "default")
CodeModel = "small"; CodeModel = "small";
Builder.defineMacro("__code_model_" + CodeModel + "_"); Builder.defineMacro("__code_model_" + CodeModel + "_");
// Target identification. // Target identification.
if (getTriple().getArch() == llvm::Triple::x86_64) { if (getTriple().getArch() == llvm::Triple::x86_64) {
Builder.defineMacro("__amd64__"); Builder.defineMacro("__amd64__");
Builder.defineMacro("__amd64"); Builder.defineMacro("__amd64");
Builder.defineMacro("__x86_64"); Builder.defineMacro("__x86_64");
Builder.defineMacro("__x86_64__"); Builder.defineMacro("__x86_64__");
if (getTriple().getArchName() == "x86_64h") { if (getTriple().getArchName() == "x86_64h") {
Builder.defineMacro("__x86_64h"); Builder.defineMacro("__x86_64h");
Builder.defineMacro("__x86_64h__"); Builder.defineMacro("__x86_64h__");
} }
} else { } else {
DefineStd(Builder, "i386", Opts); DefineStd(Builder, "i386", Opts);
} }
Builder.defineMacro("__SEG_GS");
Builder.defineMacro("__SEG_FS");
Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
// Subtarget options. // Subtarget options.
// FIXME: We are hard-coding the tune parameters based on the CPU, but they // FIXME: We are hard-coding the tune parameters based on the CPU, but they
// truly should be based on -mtune options. // truly should be based on -mtune options.
switch (CPU) { switch (CPU) {
case CK_Generic: case CK_Generic:
break; break;
case CK_i386: case CK_i386:
// The rest are coming from the i386 define above. // The rest are coming from the i386 define above.
Builder.defineMacro("__tune_i386__"); Builder.defineMacro("__tune_i386__");
break; break;
skipping to change at line 921 skipping to change at line 959
break; break;
case CK_Pentium3: case CK_Pentium3:
case CK_PentiumM: case CK_PentiumM:
Builder.defineMacro("__tune_pentium3__"); Builder.defineMacro("__tune_pentium3__");
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case CK_Pentium2: case CK_Pentium2:
case CK_C3_2: case CK_C3_2:
Builder.defineMacro("__tune_pentium2__"); Builder.defineMacro("__tune_pentium2__");
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case CK_PentiumPro: case CK_PentiumPro:
case CK_i686:
defineCPUMacros(Builder, "i686"); defineCPUMacros(Builder, "i686");
defineCPUMacros(Builder, "pentiumpro"); defineCPUMacros(Builder, "pentiumpro");
break; break;
case CK_Pentium4: case CK_Pentium4:
defineCPUMacros(Builder, "pentium4"); defineCPUMacros(Builder, "pentium4");
break; break;
case CK_Yonah: case CK_Yonah:
case CK_Prescott: case CK_Prescott:
case CK_Nocona: case CK_Nocona:
defineCPUMacros(Builder, "nocona"); defineCPUMacros(Builder, "nocona");
skipping to change at line 960 skipping to change at line 999
break; break;
case CK_Nehalem: case CK_Nehalem:
case CK_Westmere: case CK_Westmere:
case CK_SandyBridge: case CK_SandyBridge:
case CK_IvyBridge: case CK_IvyBridge:
case CK_Haswell: case CK_Haswell:
case CK_Broadwell: case CK_Broadwell:
case CK_SkylakeClient: case CK_SkylakeClient:
case CK_SkylakeServer: case CK_SkylakeServer:
case CK_Cascadelake: case CK_Cascadelake:
case CK_Cooperlake:
case CK_Cannonlake: case CK_Cannonlake:
case CK_IcelakeClient: case CK_IcelakeClient:
case CK_IcelakeServer: case CK_IcelakeServer:
// FIXME: Historically, we defined this legacy name, it would be nice to // FIXME: Historically, we defined this legacy name, it would be nice to
// remove it at some point. We've never exposed fine-grained names for // remove it at some point. We've never exposed fine-grained names for
// recent primary x86 CPUs, and we should keep it that way. // recent primary x86 CPUs, and we should keep it that way.
defineCPUMacros(Builder, "corei7"); defineCPUMacros(Builder, "corei7");
break; break;
case CK_KNL: case CK_KNL:
defineCPUMacros(Builder, "knl"); defineCPUMacros(Builder, "knl");
skipping to change at line 1031 skipping to change at line 1071
break; break;
case CK_BDVER3: case CK_BDVER3:
defineCPUMacros(Builder, "bdver3"); defineCPUMacros(Builder, "bdver3");
break; break;
case CK_BDVER4: case CK_BDVER4:
defineCPUMacros(Builder, "bdver4"); defineCPUMacros(Builder, "bdver4");
break; break;
case CK_ZNVER1: case CK_ZNVER1:
defineCPUMacros(Builder, "znver1"); defineCPUMacros(Builder, "znver1");
break; break;
case CK_ZNVER2:
defineCPUMacros(Builder, "znver2");
break;
case CK_Geode: case CK_Geode:
defineCPUMacros(Builder, "geode"); defineCPUMacros(Builder, "geode");
break; break;
} }
// Target properties. // Target properties.
Builder.defineMacro("__REGISTER_PREFIX__", ""); Builder.defineMacro("__REGISTER_PREFIX__", "");
// Define __NO_MATH_INLINES on linux/x86 so that we don't get inline // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
// functions in glibc header files that use FP Stack inline asm which the // functions in glibc header files that use FP Stack inline asm which the
skipping to change at line 1127 skipping to change at line 1170
if (HasGFNI) if (HasGFNI)
Builder.defineMacro("__GFNI__"); Builder.defineMacro("__GFNI__");
if (HasAVX512CD) if (HasAVX512CD)
Builder.defineMacro("__AVX512CD__"); Builder.defineMacro("__AVX512CD__");
if (HasAVX512VPOPCNTDQ) if (HasAVX512VPOPCNTDQ)
Builder.defineMacro("__AVX512VPOPCNTDQ__"); Builder.defineMacro("__AVX512VPOPCNTDQ__");
if (HasAVX512VNNI) if (HasAVX512VNNI)
Builder.defineMacro("__AVX512VNNI__"); Builder.defineMacro("__AVX512VNNI__");
if (HasAVX512BF16)
Builder.defineMacro("__AVX512BF16__");
if (HasAVX512ER) if (HasAVX512ER)
Builder.defineMacro("__AVX512ER__"); Builder.defineMacro("__AVX512ER__");
if (HasAVX512PF) if (HasAVX512PF)
Builder.defineMacro("__AVX512PF__"); Builder.defineMacro("__AVX512PF__");
if (HasAVX512DQ) if (HasAVX512DQ)
Builder.defineMacro("__AVX512DQ__"); Builder.defineMacro("__AVX512DQ__");
if (HasAVX512BITALG) if (HasAVX512BITALG)
Builder.defineMacro("__AVX512BITALG__"); Builder.defineMacro("__AVX512BITALG__");
if (HasAVX512BW) if (HasAVX512BW)
Builder.defineMacro("__AVX512BW__"); Builder.defineMacro("__AVX512BW__");
if (HasAVX512VL) if (HasAVX512VL)
Builder.defineMacro("__AVX512VL__"); Builder.defineMacro("__AVX512VL__");
if (HasAVX512VBMI) if (HasAVX512VBMI)
Builder.defineMacro("__AVX512VBMI__"); Builder.defineMacro("__AVX512VBMI__");
if (HasAVX512VBMI2) if (HasAVX512VBMI2)
Builder.defineMacro("__AVX512VBMI2__"); Builder.defineMacro("__AVX512VBMI2__");
if (HasAVX512IFMA) if (HasAVX512IFMA)
Builder.defineMacro("__AVX512IFMA__"); Builder.defineMacro("__AVX512IFMA__");
if (HasAVX512VP2INTERSECT)
Builder.defineMacro("__AVX512VP2INTERSECT__");
if (HasSHA) if (HasSHA)
Builder.defineMacro("__SHA__"); Builder.defineMacro("__SHA__");
if (HasFXSR) if (HasFXSR)
Builder.defineMacro("__FXSR__"); Builder.defineMacro("__FXSR__");
if (HasXSAVE) if (HasXSAVE)
Builder.defineMacro("__XSAVE__"); Builder.defineMacro("__XSAVE__");
if (HasXSAVEOPT) if (HasXSAVEOPT)
Builder.defineMacro("__XSAVEOPT__"); Builder.defineMacro("__XSAVEOPT__");
if (HasXSAVEC) if (HasXSAVEC)
skipping to change at line 1193 skipping to change at line 1239
if (HasMOVDIRI) if (HasMOVDIRI)
Builder.defineMacro("__MOVDIRI__"); Builder.defineMacro("__MOVDIRI__");
if (HasMOVDIR64B) if (HasMOVDIR64B)
Builder.defineMacro("__MOVDIR64B__"); Builder.defineMacro("__MOVDIR64B__");
if (HasPCONFIG) if (HasPCONFIG)
Builder.defineMacro("__PCONFIG__"); Builder.defineMacro("__PCONFIG__");
if (HasPTWRITE) if (HasPTWRITE)
Builder.defineMacro("__PTWRITE__"); Builder.defineMacro("__PTWRITE__");
if (HasINVPCID) if (HasINVPCID)
Builder.defineMacro("__INVPCID__"); Builder.defineMacro("__INVPCID__");
if (HasENQCMD)
Builder.defineMacro("__ENQCMD__");
// Each case falls through to the previous one here. // Each case falls through to the previous one here.
switch (SSELevel) { switch (SSELevel) {
case AVX512F: case AVX512F:
Builder.defineMacro("__AVX512F__"); Builder.defineMacro("__AVX512F__");
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case AVX2: case AVX2:
Builder.defineMacro("__AVX2__"); Builder.defineMacro("__AVX2__");
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case AVX: case AVX:
skipping to change at line 1265 skipping to change at line 1313
case AMD3DNow: case AMD3DNow:
Builder.defineMacro("__3dNOW__"); Builder.defineMacro("__3dNOW__");
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case MMX: case MMX:
Builder.defineMacro("__MMX__"); Builder.defineMacro("__MMX__");
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case NoMMX3DNow: case NoMMX3DNow:
break; break;
} }
if (CPU >= CK_i486) { if (CPU >= CK_i486 || CPU == CK_Generic) {
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
} }
if (CPU >= CK_i586) if (HasCX8)
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
if (HasCX16) if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
if (HasFloat128) if (HasFloat128)
Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
} }
bool X86TargetInfo::isValidFeatureName(StringRef Name) const { bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
return llvm::StringSwitch<bool>(Name) return llvm::StringSwitch<bool>(Name)
.Case("3dnow", true) .Case("3dnow", true)
.Case("3dnowa", true) .Case("3dnowa", true)
.Case("adx", true) .Case("adx", true)
.Case("aes", true) .Case("aes", true)
.Case("avx", true) .Case("avx", true)
.Case("avx2", true) .Case("avx2", true)
.Case("avx512f", true) .Case("avx512f", true)
.Case("avx512cd", true) .Case("avx512cd", true)
.Case("avx512vpopcntdq", true) .Case("avx512vpopcntdq", true)
.Case("avx512vnni", true) .Case("avx512vnni", true)
.Case("avx512bf16", true)
.Case("avx512er", true) .Case("avx512er", true)
.Case("avx512pf", true) .Case("avx512pf", true)
.Case("avx512dq", true) .Case("avx512dq", true)
.Case("avx512bitalg", true) .Case("avx512bitalg", true)
.Case("avx512bw", true) .Case("avx512bw", true)
.Case("avx512vl", true) .Case("avx512vl", true)
.Case("avx512vbmi", true) .Case("avx512vbmi", true)
.Case("avx512vbmi2", true) .Case("avx512vbmi2", true)
.Case("avx512ifma", true) .Case("avx512ifma", true)
.Case("avx512vp2intersect", true)
.Case("bmi", true) .Case("bmi", true)
.Case("bmi2", true) .Case("bmi2", true)
.Case("cldemote", true) .Case("cldemote", true)
.Case("clflushopt", true) .Case("clflushopt", true)
.Case("clwb", true) .Case("clwb", true)
.Case("clzero", true) .Case("clzero", true)
.Case("cx16", true) .Case("cx16", true)
.Case("enqcmd", true)
.Case("f16c", true) .Case("f16c", true)
.Case("fma", true) .Case("fma", true)
.Case("fma4", true) .Case("fma4", true)
.Case("fsgsbase", true) .Case("fsgsbase", true)
.Case("fxsr", true) .Case("fxsr", true)
.Case("gfni", true) .Case("gfni", true)
.Case("invpcid", true) .Case("invpcid", true)
.Case("lwp", true) .Case("lwp", true)
.Case("lzcnt", true) .Case("lzcnt", true)
.Case("mmx", true) .Case("mmx", true)
skipping to change at line 1369 skipping to change at line 1420
bool X86TargetInfo::hasFeature(StringRef Feature) const { bool X86TargetInfo::hasFeature(StringRef Feature) const {
return llvm::StringSwitch<bool>(Feature) return llvm::StringSwitch<bool>(Feature)
.Case("adx", HasADX) .Case("adx", HasADX)
.Case("aes", HasAES) .Case("aes", HasAES)
.Case("avx", SSELevel >= AVX) .Case("avx", SSELevel >= AVX)
.Case("avx2", SSELevel >= AVX2) .Case("avx2", SSELevel >= AVX2)
.Case("avx512f", SSELevel >= AVX512F) .Case("avx512f", SSELevel >= AVX512F)
.Case("avx512cd", HasAVX512CD) .Case("avx512cd", HasAVX512CD)
.Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
.Case("avx512vnni", HasAVX512VNNI) .Case("avx512vnni", HasAVX512VNNI)
.Case("avx512bf16", HasAVX512BF16)
.Case("avx512er", HasAVX512ER) .Case("avx512er", HasAVX512ER)
.Case("avx512pf", HasAVX512PF) .Case("avx512pf", HasAVX512PF)
.Case("avx512dq", HasAVX512DQ) .Case("avx512dq", HasAVX512DQ)
.Case("avx512bitalg", HasAVX512BITALG) .Case("avx512bitalg", HasAVX512BITALG)
.Case("avx512bw", HasAVX512BW) .Case("avx512bw", HasAVX512BW)
.Case("avx512vl", HasAVX512VL) .Case("avx512vl", HasAVX512VL)
.Case("avx512vbmi", HasAVX512VBMI) .Case("avx512vbmi", HasAVX512VBMI)
.Case("avx512vbmi2", HasAVX512VBMI2) .Case("avx512vbmi2", HasAVX512VBMI2)
.Case("avx512ifma", HasAVX512IFMA) .Case("avx512ifma", HasAVX512IFMA)
.Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
.Case("bmi", HasBMI) .Case("bmi", HasBMI)
.Case("bmi2", HasBMI2) .Case("bmi2", HasBMI2)
.Case("cldemote", HasCLDEMOTE) .Case("cldemote", HasCLDEMOTE)
.Case("clflushopt", HasCLFLUSHOPT) .Case("clflushopt", HasCLFLUSHOPT)
.Case("clwb", HasCLWB) .Case("clwb", HasCLWB)
.Case("clzero", HasCLZERO) .Case("clzero", HasCLZERO)
.Case("cx8", HasCX8)
.Case("cx16", HasCX16) .Case("cx16", HasCX16)
.Case("enqcmd", HasENQCMD)
.Case("f16c", HasF16C) .Case("f16c", HasF16C)
.Case("fma", HasFMA) .Case("fma", HasFMA)
.Case("fma4", XOPLevel >= FMA4) .Case("fma4", XOPLevel >= FMA4)
.Case("fsgsbase", HasFSGSBASE) .Case("fsgsbase", HasFSGSBASE)
.Case("fxsr", HasFXSR) .Case("fxsr", HasFXSR)
.Case("gfni", HasGFNI) .Case("gfni", HasGFNI)
.Case("invpcid", HasINVPCID) .Case("invpcid", HasINVPCID)
.Case("lwp", HasLWP) .Case("lwp", HasLWP)
.Case("lzcnt", HasLZCNT) .Case("lzcnt", HasLZCNT)
.Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
skipping to change at line 1530 skipping to change at line 1585
void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
StringRef WholeList = StringRef WholeList =
llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name))
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
#include "clang/Basic/X86Target.def" #include "clang/Basic/X86Target.def"
.Default(""); .Default("");
WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
} }
std::string X86TargetInfo::getCPUKindCanonicalName(CPUKind Kind) const {
switch (Kind) {
case CK_Generic:
return "";
#define PROC(ENUM, STRING, IS64BIT) \
case CK_##ENUM: \
return STRING;
#include "clang/Basic/X86Target.def"
}
llvm_unreachable("Invalid CPUKind");
}
// We can't use a generic validation scheme for the cpus accepted here // We can't use a generic validation scheme for the cpus accepted here
// versus subtarget cpus accepted in the target attribute because the // versus subtarget cpus accepted in the target attribute because the
// variables intitialized by the runtime only support the below currently // variables intitialized by the runtime only support the below currently
// rather than the full range of cpus. // rather than the full range of cpus.
bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
return llvm::StringSwitch<bool>(FeatureStr) return llvm::StringSwitch<bool>(FeatureStr)
#define X86_VENDOR(ENUM, STRING) .Case(STRING, true) #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
#define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \
.Cases(STR, ALIAS, true) .Cases(STR, ALIAS, true)
#define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
#define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
#include "llvm/Support/X86TargetParser.def" #include "llvm/Support/X86TargetParser.def"
.Default(false); .Default(false);
} }
static unsigned matchAsmCCConstraint(const char *&Name) {
auto RV = llvm::StringSwitch<unsigned>(Name)
.Case("@cca", 4)
.Case("@ccae", 5)
.Case("@ccb", 4)
.Case("@ccbe", 5)
.Case("@ccc", 4)
.Case("@cce", 4)
.Case("@ccz", 4)
.Case("@ccg", 4)
.Case("@ccge", 5)
.Case("@ccl", 4)
.Case("@ccle", 5)
.Case("@ccna", 5)
.Case("@ccnae", 6)
.Case("@ccnb", 5)
.Case("@ccnbe", 6)
.Case("@ccnc", 5)
.Case("@ccne", 5)
.Case("@ccnz", 5)
.Case("@ccng", 5)
.Case("@ccnge", 6)
.Case("@ccnl", 5)
.Case("@ccnle", 6)
.Case("@ccno", 5)
.Case("@ccnp", 5)
.Case("@ccns", 5)
.Case("@cco", 4)
.Case("@ccp", 4)
.Case("@ccs", 4)
.Default(0);
return RV;
}
bool X86TargetInfo::validateAsmConstraint( bool X86TargetInfo::validateAsmConstraint(
const char *&Name, TargetInfo::ConstraintInfo &Info) const { const char *&Name, TargetInfo::ConstraintInfo &Info) const {
switch (*Name) { switch (*Name) {
default: default:
return false; return false;
// Constant constraints. // Constant constraints.
case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
// instructions. // instructions.
case 'Z': // 32-bit unsigned integer constant for use with zero-extending case 'Z': // 32-bit unsigned integer constant for use with zero-extending
// x86_64 instructions. // x86_64 instructions.
skipping to change at line 1639 skipping to change at line 1716
case 'Q': // Any register accessible as [r]h: a, b, c, and d. case 'Q': // Any register accessible as [r]h: a, b, c, and d.
case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
case 'l': // "Index" registers: any general register that can be used as an case 'l': // "Index" registers: any general register that can be used as an
// index in a base+index memory access. // index in a base+index memory access.
Info.setAllowsRegister(); Info.setAllowsRegister();
return true; return true;
// Floating point constant constraints. // Floating point constant constraints.
case 'C': // SSE floating point constant. case 'C': // SSE floating point constant.
case 'G': // x87 floating point constant. case 'G': // x87 floating point constant.
return true; return true;
case '@':
// CC condition changes.
if (auto Len = matchAsmCCConstraint(Name)) {
Name += Len - 1;
Info.setAllowsRegister();
return true;
}
return false;
} }
} }
bool X86TargetInfo::validateOutputSize(StringRef Constraint, bool X86TargetInfo::validateOutputSize(StringRef Constraint,
unsigned Size) const { unsigned Size) const {
// Strip off constraint modifiers. // Strip off constraint modifiers.
while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
Constraint = Constraint.substr(1); Constraint = Constraint.substr(1);
return validateOperandSize(Constraint, Size); return validateOperandSize(Constraint, Size);
skipping to change at line 1710 skipping to change at line 1795
return Size <= 256U; return Size <= 256U;
return Size <= 128U; return Size <= 128U;
} }
return true; return true;
} }
std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
switch (*Constraint) { switch (*Constraint) {
case '@':
if (auto Len = matchAsmCCConstraint(Constraint)) {
std::string Converted = "{" + std::string(Constraint, Len) + "}";
Constraint += Len - 1;
return Converted;
}
return std::string(1, *Constraint);
case 'a': case 'a':
return std::string("{ax}"); return std::string("{ax}");
case 'b': case 'b':
return std::string("{bx}"); return std::string("{bx}");
case 'c': case 'c':
return std::string("{cx}"); return std::string("{cx}");
case 'd': case 'd':
return std::string("{dx}"); return std::string("{dx}");
case 'S': case 'S':
return std::string("{si}"); return std::string("{si}");
skipping to change at line 1772 skipping to change at line 1864
return IS64BIT || getTriple().getArch() == llvm::Triple::x86; return IS64BIT || getTriple().getArch() == llvm::Triple::x86;
#include "clang/Basic/X86Target.def" #include "clang/Basic/X86Target.def"
} }
llvm_unreachable("Unhandled CPU kind"); llvm_unreachable("Unhandled CPU kind");
} }
void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
#define PROC(ENUM, STRING, IS64BIT) \ #define PROC(ENUM, STRING, IS64BIT) \
if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \
Values.emplace_back(STRING); Values.emplace_back(STRING);
// Go through CPUKind checking to ensure that the alias is de-aliased and // For aliases we need to lookup the CPUKind to check get the 64-bit ness.
// 64 bit-ness is checked.
#define PROC_ALIAS(ENUM, ALIAS) \ #define PROC_ALIAS(ENUM, ALIAS) \
if (checkCPUKind(getCPUKind(ALIAS))) \ if (checkCPUKind(CK_##ENUM)) \
Values.emplace_back(ALIAS); Values.emplace_back(ALIAS);
#include "clang/Basic/X86Target.def" #include "clang/Basic/X86Target.def"
} }
X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const {
return llvm::StringSwitch<CPUKind>(CPU) return llvm::StringSwitch<CPUKind>(CPU)
#define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM)
#define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM)
#include "clang/Basic/X86Target.def" #include "clang/Basic/X86Target.def"
.Default(CK_Generic); .Default(CK_Generic);
 End of changes. 54 change blocks. 
70 lines changed or deleted 160 lines changed or added

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