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Source code changes of the file "lib/Basic/Targets/AArch64.cpp" between
cfe-8.0.1.src.tar.xz and cfe-9.0.0.src.tar.xz

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AArch64.cpp  (cfe-8.0.1.src.tar.xz):AArch64.cpp  (cfe-9.0.0.src.tar.xz)
//===--- AArch64.cpp - Implement AArch64 target feature support -----------===// //===--- AArch64.cpp - Implement AArch64 target feature support -----------===//
// //
// The LLVM Compiler Infrastructure // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// // See https://llvm.org/LICENSE.txt for license information.
// This file is distributed under the University of Illinois Open Source // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file implements AArch64 TargetInfo objects. // This file implements AArch64 TargetInfo objects.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "AArch64.h" #include "AArch64.h"
#include "clang/Basic/TargetBuiltins.h" #include "clang/Basic/TargetBuiltins.h"
#include "clang/Basic/TargetInfo.h" #include "clang/Basic/TargetInfo.h"
skipping to change at line 122 skipping to change at line 121
MacroBuilder &Builder) const { MacroBuilder &Builder) const {
Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
} }
void AArch64TargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts, void AArch64TargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts,
MacroBuilder &Builder) const { MacroBuilder &Builder) const {
// Also include the ARMv8.1 defines // Also include the ARMv8.1 defines
getTargetDefinesARMV81A(Opts, Builder); getTargetDefinesARMV81A(Opts, Builder);
} }
void AArch64TargetInfo::getTargetDefinesARMV83A(const LangOptions &Opts,
MacroBuilder &Builder) const {
Builder.defineMacro("__ARM_FEATURE_JCVT", "1");
// Also include the Armv8.2 defines
getTargetDefinesARMV82A(Opts, Builder);
}
void AArch64TargetInfo::getTargetDefinesARMV84A(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Also include the Armv8.3 defines
// FIXME: Armv8.4 makes some extensions mandatory. Handle them here.
getTargetDefinesARMV83A(Opts, Builder);
}
void AArch64TargetInfo::getTargetDefinesARMV85A(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Also include the Armv8.4 defines
// FIXME: Armv8.5 makes some extensions mandatory. Handle them here.
getTargetDefinesARMV84A(Opts, Builder);
}
void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts, void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const { MacroBuilder &Builder) const {
// Target identification. // Target identification.
Builder.defineMacro("__aarch64__"); Builder.defineMacro("__aarch64__");
// For bare-metal. // For bare-metal.
if (getTriple().getOS() == llvm::Triple::UnknownOS && if (getTriple().getOS() == llvm::Triple::UnknownOS &&
getTriple().isOSBinFormatELF()) getTriple().isOSBinFormatELF())
Builder.defineMacro("__ELF__"); Builder.defineMacro("__ELF__");
// Target properties. // Target properties.
skipping to change at line 178 skipping to change at line 198
Twine(Opts.WCharSize ? Opts.WCharSize : 4)); Twine(Opts.WCharSize ? Opts.WCharSize : 4));
Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? "1" : "4"); Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? "1" : "4");
if (FPU & NeonMode) { if (FPU & NeonMode) {
Builder.defineMacro("__ARM_NEON", "1"); Builder.defineMacro("__ARM_NEON", "1");
// 64-bit NEON supports half, single and double precision operations. // 64-bit NEON supports half, single and double precision operations.
Builder.defineMacro("__ARM_NEON_FP", "0xE"); Builder.defineMacro("__ARM_NEON_FP", "0xE");
} }
if (FPU & SveMode) if (HasCRC)
Builder.defineMacro("__ARM_FEATURE_SVE", "1");
if (CRC)
Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
if (Crypto) if (HasCrypto)
Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
if (Unaligned) if (HasUnaligned)
Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
if ((FPU & NeonMode) && HasFullFP16) if ((FPU & NeonMode) && HasFullFP16)
Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1"); Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");
if (HasFullFP16) if (HasFullFP16)
Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1"); Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
if (HasDotProd) if (HasDotProd)
Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1"); Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
if (HasMTE)
Builder.defineMacro("__ARM_FEATURE_MEMORY_TAGGING", "1");
if ((FPU & NeonMode) && HasFP16FML) if ((FPU & NeonMode) && HasFP16FML)
Builder.defineMacro("__ARM_FEATURE_FP16FML", "1"); Builder.defineMacro("__ARM_FEATURE_FP16FML", "1");
switch (ArchKind) { switch (ArchKind) {
default: default:
break; break;
case llvm::AArch64::ArchKind::ARMV8_1A: case llvm::AArch64::ArchKind::ARMV8_1A:
getTargetDefinesARMV81A(Opts, Builder); getTargetDefinesARMV81A(Opts, Builder);
break; break;
case llvm::AArch64::ArchKind::ARMV8_2A: case llvm::AArch64::ArchKind::ARMV8_2A:
getTargetDefinesARMV82A(Opts, Builder); getTargetDefinesARMV82A(Opts, Builder);
break; break;
case llvm::AArch64::ArchKind::ARMV8_3A:
getTargetDefinesARMV83A(Opts, Builder);
break;
case llvm::AArch64::ArchKind::ARMV8_4A:
getTargetDefinesARMV84A(Opts, Builder);
break;
case llvm::AArch64::ArchKind::ARMV8_5A:
getTargetDefinesARMV85A(Opts, Builder);
break;
} }
// All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
} }
ArrayRef<Builtin::Info> AArch64TargetInfo::getTargetBuiltins() const { ArrayRef<Builtin::Info> AArch64TargetInfo::getTargetBuiltins() const {
skipping to change at line 233 skipping to change at line 262
bool AArch64TargetInfo::hasFeature(StringRef Feature) const { bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
return Feature == "aarch64" || Feature == "arm64" || Feature == "arm" || return Feature == "aarch64" || Feature == "arm64" || Feature == "arm" ||
(Feature == "neon" && (FPU & NeonMode)) || (Feature == "neon" && (FPU & NeonMode)) ||
(Feature == "sve" && (FPU & SveMode)); (Feature == "sve" && (FPU & SveMode));
} }
bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
DiagnosticsEngine &Diags) { DiagnosticsEngine &Diags) {
FPU = FPUMode; FPU = FPUMode;
CRC = 0; HasCRC = false;
Crypto = 0; HasCrypto = false;
Unaligned = 1; HasUnaligned = true;
HasFullFP16 = 0; HasFullFP16 = false;
HasDotProd = 0; HasDotProd = false;
HasFP16FML = 0; HasFP16FML = false;
HasMTE = false;
ArchKind = llvm::AArch64::ArchKind::ARMV8A; ArchKind = llvm::AArch64::ArchKind::ARMV8A;
for (const auto &Feature : Features) { for (const auto &Feature : Features) {
if (Feature == "+neon") if (Feature == "+neon")
FPU |= NeonMode; FPU |= NeonMode;
if (Feature == "+sve") if (Feature == "+sve")
FPU |= SveMode; FPU |= SveMode;
if (Feature == "+crc") if (Feature == "+crc")
CRC = 1; HasCRC = true;
if (Feature == "+crypto") if (Feature == "+crypto")
Crypto = 1; HasCrypto = true;
if (Feature == "+strict-align") if (Feature == "+strict-align")
Unaligned = 0; HasUnaligned = false;
if (Feature == "+v8.1a") if (Feature == "+v8.1a")
ArchKind = llvm::AArch64::ArchKind::ARMV8_1A; ArchKind = llvm::AArch64::ArchKind::ARMV8_1A;
if (Feature == "+v8.2a") if (Feature == "+v8.2a")
ArchKind = llvm::AArch64::ArchKind::ARMV8_2A; ArchKind = llvm::AArch64::ArchKind::ARMV8_2A;
if (Feature == "+v8.3a")
ArchKind = llvm::AArch64::ArchKind::ARMV8_3A;
if (Feature == "+v8.4a")
ArchKind = llvm::AArch64::ArchKind::ARMV8_4A;
if (Feature == "+v8.5a")
ArchKind = llvm::AArch64::ArchKind::ARMV8_5A;
if (Feature == "+fullfp16") if (Feature == "+fullfp16")
HasFullFP16 = 1; HasFullFP16 = true;
if (Feature == "+dotprod") if (Feature == "+dotprod")
HasDotProd = 1; HasDotProd = true;
if (Feature == "+fp16fml") if (Feature == "+fp16fml")
HasFP16FML = 1; HasFP16FML = true;
if (Feature == "+mte")
HasMTE = true;
} }
setDataLayout(); setDataLayout();
return true; return true;
} }
TargetInfo::CallingConvCheckResult TargetInfo::CallingConvCheckResult
AArch64TargetInfo::checkCallingConvention(CallingConv CC) const { AArch64TargetInfo::checkCallingConvention(CallingConv CC) const {
switch (CC) { switch (CC) {
skipping to change at line 312 skipping to change at line 350
// 32-bit floating point regsisters // 32-bit floating point regsisters
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
"s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22",
"s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
// 64-bit floating point regsisters // 64-bit floating point regsisters
"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11", "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11",
"d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
"d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
// Vector registers // Neon vector registers
"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11",
"v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22",
"v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
// SVE vector registers
"z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10",
"z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21",
"z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
// SVE predicate registers
"p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10",
"p11", "p12", "p13", "p14", "p15"
}; };
ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
return llvm::makeArrayRef(GCCRegNames); return llvm::makeArrayRef(GCCRegNames);
} }
const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
{{"w31"}, "wsp"}, {{"w31"}, "wsp"},
{{"x31"}, "sp"}, {{"x31"}, "sp"},
// GCC rN registers are aliases of xN registers. // GCC rN registers are aliases of xN registers.
skipping to change at line 532 skipping to change at line 579
return CCCR_Warning; return CCCR_Warning;
} }
} }
MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(const llvm::Triple &Triple, MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(const llvm::Triple &Triple,
const TargetOptions &Opts) const TargetOptions &Opts)
: WindowsARM64TargetInfo(Triple, Opts) { : WindowsARM64TargetInfo(Triple, Opts) {
TheCXXABI.set(TargetCXXABI::Microsoft); TheCXXABI.set(TargetCXXABI::Microsoft);
} }
void MicrosoftARM64TargetInfo::getVisualStudioDefines(
const LangOptions &Opts, MacroBuilder &Builder) const {
WindowsTargetInfo<AArch64leTargetInfo>::getVisualStudioDefines(Opts, Builder);
Builder.defineMacro("_M_ARM64", "1");
}
void MicrosoftARM64TargetInfo::getTargetDefines(const LangOptions &Opts, void MicrosoftARM64TargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const { MacroBuilder &Builder) const {
WindowsTargetInfo::getTargetDefines(Opts, Builder); WindowsARM64TargetInfo::getTargetDefines(Opts, Builder);
getVisualStudioDefines(Opts, Builder); Builder.defineMacro("_M_ARM64", "1");
} }
TargetInfo::CallingConvKind TargetInfo::CallingConvKind
MicrosoftARM64TargetInfo::getCallingConvKind(bool ClangABICompat4) const { MicrosoftARM64TargetInfo::getCallingConvKind(bool ClangABICompat4) const {
return CCK_MicrosoftWin64; return CCK_MicrosoftWin64;
} }
unsigned MicrosoftARM64TargetInfo::getMinGlobalAlign(uint64_t TypeSize) const {
unsigned Align = WindowsARM64TargetInfo::getMinGlobalAlign(TypeSize);
// MSVC does size based alignment for arm64 based on alignment section in
// below document, replicate that to keep alignment consistent with object
// files compiled by MSVC.
// https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions
if (TypeSize >= 512) { // TypeSize >= 64 bytes
Align = std::max(Align, 128u); // align type at least 16 bytes
} else if (TypeSize >= 64) { // TypeSize >= 8 bytes
Align = std::max(Align, 64u); // align type at least 8 butes
} else if (TypeSize >= 16) { // TypeSize >= 2 bytes
Align = std::max(Align, 32u); // align type at least 4 bytes
}
return Align;
}
MinGWARM64TargetInfo::MinGWARM64TargetInfo(const llvm::Triple &Triple, MinGWARM64TargetInfo::MinGWARM64TargetInfo(const llvm::Triple &Triple,
const TargetOptions &Opts) const TargetOptions &Opts)
: WindowsARM64TargetInfo(Triple, Opts) { : WindowsARM64TargetInfo(Triple, Opts) {
TheCXXABI.set(TargetCXXABI::GenericAArch64); TheCXXABI.set(TargetCXXABI::GenericAArch64);
} }
DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(const llvm::Triple &Triple, DarwinAArch64TargetInfo::DarwinAArch64TargetInfo(const llvm::Triple &Triple,
const TargetOptions &Opts) const TargetOptions &Opts)
: DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) {
Int64Type = SignedLongLong; Int64Type = SignedLongLong;
 End of changes. 20 change blocks. 
32 lines changed or deleted 90 lines changed or added

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